Semiconductor packaging structure
By setting a protective layer on the back of the chip and combining the design of the underfill layer and the die seal layer, the chip heat dissipation and packaging problems in the prior art are solved, and higher yields and performance are achieved.
Patent Information
- Application Number
- CN202421788974.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-07-25
- Publication Date
- 2025-06-20
- Estimated Expiration
- 2034-07-25
AI Technical Summary
While improving the heat dissipation performance of the chip, the prior art can easily lead to chip damage, packaging layer layering and warping problems, and is especially suitable for thicker chips, while thinner chips are easily damaged during grinding.
A semiconductor package structure is adopted, in which a protective layer is provided on the back of the chip to avoid the grinding process, combined with the underfill layer and the die seal layer, forming a contact surface to improve heat dissipation performance and reduce warping.
It effectively avoids chip damage, improves heat dissipation performance, reduces warping of the package, and is suitable for chips of different thicknesses.
Smart Images
Figure CN223006765U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a semiconductor packaging structure. Background Art
[0002] Figure 1 and Figure 2 FIG. 1 shows a cross-sectional view of an electronic product 1 according to different embodiments of the prior art. As the computing power of the electronic product 1 increases, the issue of heat dissipation of the chip 2 has been increasingly emphasized. In the past, the commonly used method was to expose the back crystal surface 3 of the chip 2, so that heat could be dissipated through the exposed back crystal surface 3 to avoid temperature rise. There are two methods used. The first is to stick tape on the back crystal surface, and the tape can be removed at the end of the encapsulation (molding) stage to expose the back crystal surface 3; the second is to use a grinding method to expose the back crystal surface 3 after the chip 1 is encapsulated. For the method using tape, the characteristics of the tape need to be considered, and during encapsulation, the encapsulation layer 4 will seep into / extend to the edge position between the back crystal surface 3 and the tape, which will affect heat dissipation and electrical properties, and delamination problems are likely to occur between the encapsulation layer 4 and the side wall of the chip 2; for the grinding method, it is necessary to consider that the chip 2 will be damaged (crack) 5 due to grinding and the uneven grinding will affect the consistency.
[0003] Moreover, the solution of exposing the back crystal surface 3 is usually applicable to relatively thick chips 2 and not applicable to relatively thin chips 2, because relatively thin chips are more likely to be damaged due to grinding, resulting in process treatment and quality problems. Summary of the Utility Model
[0004] Aiming at the problems existing in the related art, the purpose of the utility model is to provide a semiconductor packaging structure to at least improve the yield and performance of the semiconductor packaging structure.
[0005] To achieve the above purpose, the utility model provides a semiconductor packaging structure, including: a semiconductor chip, including an active surface and a back surface located on the opposite side of the active surface; a protective layer provided on the back surface; a bottom fill layer covering the active surface and part of the side surfaces of the semiconductor chip; a molding layer covering part of the side surfaces of the semiconductor chip and intersecting with the protective layer to form a contact surface, and the contact surface is not coplanar with the side surface of the semiconductor chip.
[0006] In some embodiments, the projection of the molding layer in the vertical direction overlaps with the bottom fill layer.
[0007] In some embodiments, the contact surface is a curved surface, and the protective layer gradually becomes wider in the direction away from the active surface.
[0008] In some embodiments, the projection of the molding layer in the vertical direction does not overlap with the semiconductor chip.
[0009] In some embodiments, the underfill layer does not contact the back surface of the semiconductor chip.
[0010] In some embodiments, the top surface of the protective layer is higher than the top surface of the encapsulation layer.
[0011] In some embodiments, the encapsulation layer and the semiconductor chip define an included angle, and the included angle is an acute angle.
[0012] In some embodiments, the included angle is filled with the underfill layer.
[0013] In some embodiments, the thickness of the protective layer is less than the thickness of the semiconductor chip.
[0014] In some embodiments, the protective layer is made of an insulating and thermally conductive material.
[0015] In some embodiments, the side surfaces of the semiconductor substrate and the encapsulation layer are coplanar.
[0016] In some embodiments, the protective layer completely covers the back surface of the semiconductor chip.
[0017] In some embodiments, the semiconductor package structure further includes: solder balls located on the active surface of the semiconductor chip.
[0018] In some embodiments, the underfill layer encapsulates the solder balls.
[0019] Embodiments of the present application further include a semiconductor package structure, including: a semiconductor chip including an active surface and a back surface located on the opposite side of the active surface; a protective layer completely covering the back surface; an encapsulation layer covering a part of the side surfaces of the semiconductor chip and intersecting with the protective layer to form a contact surface, and the contact surface is inclined with respect to the side surface of the semiconductor chip.
[0020] In some embodiments, the maximum horizontal dimension of the protective layer is greater than the horizontal dimension of the back surface of the semiconductor chip.
[0021] In some embodiments, the minimum horizontal dimension of the protective layer is equal to the horizontal dimension of the back surface of the semiconductor chip.
[0022] In some embodiments, the minimum horizontal dimension of the protective layer is located at the position where it contacts the semiconductor chip.
[0023] In some embodiments, the semiconductor package structure further includes: an underfill layer covering the active surface and part of the side surfaces of the semiconductor chip, and the encapsulation layer covers the underfill layer.
[0024] In some embodiments, the contact surface between the underfill layer and the encapsulation layer is a curved surface.
[0025] The beneficial technical effects of the present utility model are as follows:
[0026] Embodiments of the present application provide a protective layer on the back surface of a semiconductor chip, and the protective layer remains in the product, eliminating the need for the back surface of the semiconductor chip to undergo a grinding process, preventing damage to the semiconductor chip. The protective layer also reduces the warping of the semiconductor package while assisting in heat dissipation of the semiconductor chip. BRIEF DESCRIPTION OF THE DRAWINGS
[0027] Figure 1 and Figure 2 FIGS. show cross-sectional views of electronic products of different prior art embodiments.
[0028] Figure 3 FIG. shows a semiconductor substrate according to an embodiment of the present application.
[0029] Figure 4 FIG. shows bonding a semiconductor chip to a semiconductor substrate.
[0030] Figure 5 FIG. shows forming a film on the protective layer.
[0031] Figure 6 FIG. shows forming a molding compound layer.
[0032] Figure 7 FIG. shows removing Figure 6 the film in to obtain a structure.
[0033] Figure 8 FIG. shows a semiconductor package structure according to an embodiment of the present application.
[0034] Figure 9 FIG. shows Figure 8 a semiconductor package structure of a different embodiment.
[0035] Figure 10 FIG. shows an electron micrograph of a part of a semiconductor package structure according to an embodiment of the present application.
[0036] Figure 11 FIG. shows a warped product in a frowning face shape.
[0037] Figure 12 FIG. shows a warped product in a smiling face shape. DETAILED DESCRIPTION
[0038] To better understand the spirit of the embodiments of the present application, the following further describes some preferred embodiments of the present application.
[0039] Embodiments of the present application will be described in detail below. Throughout the specification of the present application, components that are the same or similar and have the same or similar functions are denoted by like reference numerals. The embodiments of the related drawings described herein are illustrative, diagrammatic, and are used to provide a basic understanding of the present application. The embodiments of the present application should not be construed as a limitation of the present application.
[0040] As used herein, the terms "substantially", "essentially", "substantive" and "about" are used to describe and account for minor variations. When used in conjunction with an event or circumstance, the terms can refer to instances where the event or circumstance occurs precisely and instances where the event or circumstance occurs very nearly.
[0041] In this specification, unless specifically specified or limited otherwise, relative terms such as "central", "longitudinal", "lateral", "front", "rear", "right", "left", "inner", "outer", "lower", "higher", "horizontal", "vertical", "above", "below", "upper", "lower", "top", "bottom" and their derivatives (such as "horizontally", "downwardly", "upwardly", etc.) should be construed as referring to the directions described in the discussion or depicted in the drawings. These relative terms are for convenience of description only and do not require the present application to be constructed or operated in a particular direction.
[0042] For ease of description, "first", "second", "third", etc. may be used herein to distinguish different components of a figure or a series of figures. "First", "second", "third", etc. are not intended to describe corresponding components.
[0043] Figures 3 to 8 The formation process of the semiconductor package structure 100 according to an embodiment of the present application is shown.
[0044] See Figure 3 , a semiconductor substrate 70 is provided. In some embodiments, the thickness of the semiconductor substrate 70 is from 0.08 mm to 0.1 mm.
[0045] See Figure 4, for example, the solder balls 60 of the semiconductor chip 10 are bonded to the semiconductor substrate 70 through a flip chip bonding (FCB) process, a bottom fill layer 30 is formed between the active surface 101 of the semiconductor chip 10 and the semiconductor substrate 70, the bottom fill layer 30 encapsulates the solder balls 60, and a protective layer 20 covering the back surface 102 of the semiconductor chip 10 is formed, for example, through a lamination process. In some embodiments, the semiconductor chip 10 is a wafer level package (WLP), a thin power management die [e.g., a power management integrated circuit (PMIC) die], etc. In some embodiments, the bottom fill layer 30 is a capillary underfill (CUF).
[0046] See Figure 5 , a film 80 is formed on the protective layer 20, and a part of the protective layer 20 is recessed into the film 80.
[0047] See Figure 6 , a molding compound layer 40 is formed between the film 80 and the semiconductor substrate 70. The film 80 is removed to obtain Figure 7 the structure shown.
[0048] See Figure 8 , for example, a second solder ball 90 is formed under the semiconductor substrate 70 through a solder ball bond placement (SBBP) process, and the semiconductor package structure 100 according to the embodiment of the present application is obtained. Figures 3 to 8 Taking a single unit of the semiconductor package structure 100 as an example, during production, a continuous plurality of units of the semiconductor package structure 100 are formed together and after the Figure 8 step, a singulation process (e.g., cutting) is performed to form Figure 8 a single unit of the semiconductor package structure 100 shown.
[0049] Figure 9 shows a semiconductor package structure 100 of an embodiment different from Figure 8 , in which the bottom fill layer 30 extends onto the side surface 103 of the semiconductor chip 10.
[0050] Figure 10 shows an electron microscope image of a part of the semiconductor package structure 100 according to the embodiment of the present application, in which the outlines of the components are additionally shown with white dotted lines.
[0051] See Figure 10, an embodiment of the present application provides a semiconductor package structure 100, including: a semiconductor chip 10, including an active surface 101 and a back surface 102 located on the opposite side of the active surface 101; a protective layer 20 disposed on the back surface 102; an underfill layer 30 covering the active surface 101 and a part of the side surface 103 of the semiconductor chip 10; a molding compound layer 40 covering a part of the side surface 103 of the semiconductor chip 10 and intersecting with the protective layer 20 to form a contact surface 50, and the contact surface 50 is not coplanar with the side surface 103 of the semiconductor chip 10. In the embodiment of the present application, a protective layer 20 is disposed on the back surface
crystal back (BSC)
[0052] In some embodiments, the projection of the molding compound layer 40 in the vertical direction overlaps with the underfill layer 30.
[0053] In some embodiments, the contact surface 50 is a curved surface, and the protective layer 20 gradually widens in the direction away from the active surface 101. In some embodiments, the contact surface 50 is in contact with the side surface 103 of the semiconductor chip 10. That is to say, the bottom surface of the protective layer 20 coincides with the back surface 102 of the semiconductor 10, and the edge of the protective layer 20 (i.e., the contact surface 50) is inclined outward, which can prevent the molding compound layer 40 from seeping onto the back surface 102 of the semiconductor chip 10 and the protective layer 20 when the molding compound layer 40 is formed. In some embodiments, in Figure 4 In the step of forming the protective layer 20, the side surface of the protective layer 20 with the above shape is formed, for example, the edge of the protective layer 20 is cut at an inclined angle.
[0054] In some embodiments, the projection of the molding compound layer 40 in the vertical direction does not overlap with the semiconductor chip 10.
[0055] In some embodiments, the underfill layer 30 does not contact the back surface 102 of the semiconductor chip 10.
[0056] In some embodiments, the top surface of the protective layer 20 is higher than the top surface of the molding compound layer 40. In some embodiments, the height difference between the top surface of the protective layer 20 and the top surface of the molding compound layer 40 is 5.56 μm. In some embodiments, the thickness of the molding compound layer 40 is 272 μm. In some embodiments, the thickness of the protective layer 20 is 23.4 μm. In some embodiments, the thickness between the active surface 101 and the back surface 102 of the semiconductor chip 10 is 187 μm. In some embodiments, the distance between the active surface 101 of the semiconductor chip 10 and the semiconductor substrate 70 is 66.3 μm.
[0057] In some embodiments, the molding compound layer 40 and the semiconductor chip 10 define an included angle α, and the included angle α is an acute angle.
[0058] In some embodiments, the included angle α is filled with the underfill layer 30.
[0059] In some embodiments, the thickness of the protective layer 20 is less than the thickness of the semiconductor chip 10.
[0060] In some embodiments, the protective layer 20 is a material that is insulating and thermally conductive. In some embodiments, the protective layer 20 is a thermal interface material (TIM). In some embodiments, the protective layer 20 is a coating.
[0061] In some embodiments, the sides of the semiconductor substrate 70 and the sides of the encapsulation layer 40 are coplanar.
[0062] In some embodiments, the protective layer 20 completely covers the back surface 102 of the semiconductor chip 10.
[0063] In some embodiments, the semiconductor package structure 100 further includes: solder balls 60, located on the active surface 101 of the semiconductor chip 10.
[0064] In some embodiments, the underfill layer 30 encapsulates the solder balls 60.
[0065] Embodiments of the present application further include a semiconductor package structure 100, including: a semiconductor chip 10, including an active surface 101 and a back surface 102 located on the opposite side of the active surface 101; a protective layer 20, completely covering the back surface 102; an encapsulation layer 40, encapsulating a partial side surface 103 of the semiconductor chip 10, and intersecting with the protective layer 20 to form a contact surface 50, and the contact surface 50 is inclined with respect to the side surface 103 of the semiconductor chip 10.
[0066] In some embodiments, the maximum horizontal dimension of the protective layer 20 is greater than the horizontal dimension of the back surface 102 of the semiconductor chip 10.
[0067] In some embodiments, the minimum horizontal dimension of the protective layer 20 is equal to the horizontal dimension of the back surface 102 of the semiconductor chip 10.
[0068] In some embodiments, the minimum horizontal dimension of the protective layer 20 is located at the position in contact with the semiconductor chip 10.
[0069] In some embodiments, the semiconductor package structure 100 further includes: an underfill layer 30, encapsulating the active surface 101 and a partial side surface 103 of the semiconductor chip 10, and the encapsulation layer 40 encapsulates the underfill layer 30.
[0070] In some embodiments, the contact surface 50 between the underfill layer 30 and the encapsulation layer 40 is a curved surface.
[0071] Embodiments of the present application provide assistance to the back surface 102 of the semiconductor chip 10. The protective layer 20 can ensure the heat dissipation of the semiconductor chip 10 and protect the back surface 102 and edges of the semiconductor chip 10 from damage.
[0072] The protective layer 20 of the embodiments of the present application also reduces the warpage of the semiconductor package 100. Before the singulation step, the semiconductor package 100 is, for example, a strip package. For the strip package, the present application designs corresponding to Figures 8 to 10 the experimental group of the shown embodiment, where the thickness of the semiconductor chip 10 is 7 mil and the thickness of the protective layer 20 is 1 mil. After the step of bonding the semiconductor chip 10 to the semiconductor substrate 70, the warpage of the strip package is 0 mm; after the step of forming the underfill layer 30, the warpage of the strip package is 0 mm; after the step of forming the molding layer 40, the warpage of the strip package is 4 mm; after the step of forming the second solder ball 90, the warpage of the strip package is 6 mm.
[0073] In addition, two control groups of strip packages corresponding to the prior art Figure 1 and Figure 2 shown embodiments are provided. In control group 1, the thickness of chip 2 is 8 mil; in control group 2, the thickness of chip 1 is 6 mil, and the thickness of the encapsulation layer 4 infiltrated into the back crystal of chip 1 is 0.29 mil. After the step of bonding chip 2 to the semiconductor substrate 6, the warpage of both control group 1 and control group 2 is 0 mm; after the step of forming the underfill layer 7, the warpage of control group 1 is -1 mm and the warpage of control group 2 is 0 mm; after the step of forming the encapsulation layer 4, the warpage of both control group 1 and control group 2 is 4.5 mm; after the step of forming the solder ball 9, the warpage of both control group 1 and control group 2 is 18 mm. Among them, when the above warpage is a positive number, it means it presents a frowning face shape as shown by the warped product 110 in Figure 11 , and when the above warpage is a negative number, it means it presents a smiling face shape as shown by the warped product 110 in Figure 12 . The embodiments of the present application use the protective layer 20 to reduce the warpage of the strip package by 12 mm.
[0074] The above are only the preferred embodiments of the present utility model and are not used to limit the present utility model. For those skilled in the art, the present utility model can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.
Claims
1. A semiconductor packaging structure, characterized in that: include: A semiconductor chip including an active surface and a back surface located on an opposite side of the active surface; A protective layer, disposed on the back surface; A bottom filling layer covering the active surface and part of the side surface of the semiconductor chip; The molding layer covers a part of the side surface of the semiconductor chip and intersects with the protection layer to form a contact surface, wherein the contact surface is not coplanar with the side surface of the semiconductor chip.
2. The semiconductor package structure according to claim 1, wherein: A projection of the molding layer in a vertical direction overlaps with the bottom filling layer.
3. The semiconductor package structure according to claim 2, characterized in that: The contact surface is a curved surface, and the protection layer gradually widens in a direction away from the active surface.
4. The semiconductor package structure according to claim 1, wherein: A projection of the molding layer along a vertical direction does not overlap with the semiconductor chip.
5. The semiconductor package structure according to claim 1, wherein: The underfill layer does not contact the backside of the semiconductor chip.
6. The semiconductor package structure according to claim 1, wherein: The top surface of the protection layer is higher than the top surface of the molding layer.
7. The semiconductor package structure according to claim 1, wherein: The molding layer and the semiconductor chip define an angle, and the angle is an acute angle.
8. The semiconductor package structure according to claim 7, characterized in that: The included angle is filled by the bottom filling layer.
9. The semiconductor package structure according to claim 1, wherein: The thickness of the protection layer is smaller than the thickness of the semiconductor chip.
10. The semiconductor package structure according to claim 1, wherein: The protective layer is an insulating and thermally conductive material.