Trench gate super junction VDMOS device

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses a trench gate super junction VDMOS device, comprising a VDMOS device composed of a plurality of VDMOS cells, the VDMOS device comprising a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode; the semiconductor epitaxial layer comprises a substrate layer, a diffusion layer, a P well layer and a heavily doped N well layer, and the N well layer is isolated from the diffusion layer through the P well layer; wherein the P-well layer comprises a lightly doped P-well layer I, a heavily doped P-well layer I and a heavily doped P-well layer II; the diffusion layer forms a first lightly doped diffusion layer, a second lightly doped diffusion layer and a third lightly doped diffusion layer through ion implantation of phosphorus elements with different concentrations. According to the utility model, the heavily-doped P-well layer I is formed by ion implantation between adjacent VDMOS cells, and the lightly-doped layer has a lower charge conduction effect, so that when the switching tube is conducted, due to the constraint of the lightly-doped layer and the heavily-doped P-well layer I, the injection of unbalanced carriers is reduced, and reverse recovery charges are reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically to a trench-gate superjunction VDMOS device. Background Art

[0002] VDMOSFET devices have significant advantages of high frequency and low loss, and are widely used in fields such as electric vehicles, photovoltaic inverters, and charging piles. The semiconductor material silicon carbide has characteristics such as a wide bandgap, a high breakdown field strength, a high thermal conductivity, a high saturated electron drift velocity, and stable physical and chemical properties, and can be applied to high temperature, high frequency, high power, and extreme environments.

[0003] A prior patent discloses a shield-gate trench MOSFET (publication number CN116093163A), which includes an N-type heavily doped substrate, an N-type lightly doped epitaxial drift layer, a P-type diffusion region, an N-type heavily doped diffusion region, a deep trench and a shallow trench constructed in the vertical direction. A shield-gate polysilicon and a control-gate polysilicon are constructed in the deep trench, and are isolated from the trench edge by an isolation field oxide and a gate oxide respectively. A control-gate polysilicon is constructed in the shallow trench and is isolated from the trench edge by a gate oxide. A metal electrode is constructed in the device to isolate oxygen. In the technology disclosed in this patent, since the VDMOS device has an alternating PN column structure inside, the non-equilibrium carrier concentration in the voltage-resistant layer is higher during conduction, and current and voltage overshoots are likely to occur during the reverse recovery process. Moreover, if a P-type material is directly filled in the diffusion layer for suppression, the diffusion layer charges of each cell will not communicate with each other, which easily causes the problem of increased loss of cells in a single region. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a trench-gate superjunction VDMOS device, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a trench-gate superjunction VDMOS device includes a VDMOS device composed of a plurality of VDMOS cells. The VDMOS device includes a drain, a semiconductor epitaxial layer, a metal source, and a gate;

[0006] The semiconductor epitaxial layer includes a substrate layer, a diffusion layer, a P-well layer, and a heavily doped N-well layer, wherein the N-well layer is isolated from the diffusion layer by the P-well layer;

[0007] Among them, the P-well layer includes a lightly doped P-well layer 1, a heavily doped P-well layer 1, and a heavily doped P-well layer 2;

[0008] The substrate layer includes a conducting substrate layer and a suppressing substrate layer;

[0009] The diffusion layer forms a lightly doped diffusion layer 1, a lightly doped diffusion layer 2, a lightly doped diffusion layer 3, a heavily doped diffusion layer, and a lightly doped layer by ion implantation of phosphorus elements with different concentrations.

[0010] Furthermore, when a gate voltage is applied to the gate, a depletion layer JFET region is formed inside the diffusion layer, where the JFET region is located between two adjacent heavily doped P-well layers 1.

[0011] Furthermore, when the gate accesses the gate voltage, the charges inside the lightly doped P-well layer 1 gather towards the gate under the intervention of the gate electric field and form a charge channel.

[0012] Furthermore, after the charge channel connects the heavily doped N-well layer and the diffusion layer, its drain and the metal source return to the conducting state.

[0013] Furthermore, the heavily doped P-well layer 1 and the heavily doped P-well layer 2 between adjacent VDMOS cells are integrated as a whole.

[0014] Furthermore, high-energy impurities are doped into the suppression substrate layer, where the energy level of the high-energy impurities is at least above the valence band bottom by.eV, and the impurity material can specifically be In, Ti, or Zn.

[0015] Furthermore, the lightly doped P-well layer 1 is doped with low-concentration boron ions by ion implantation.

[0016] Furthermore, the heavily doped N-well layer (7) and the heavily doped diffusion layer (305) are doped with high-concentration phosphorus ions by ion implantation; the lightly doped diffusion layer 3 (304), the lightly doped diffusion layer 2 (303), the lightly doped layer (302), and the lightly doped diffusion layer 1 (301) are doped with low-concentration phosphorus ions by ion implantation.

[0017] Furthermore, a gate oxide layer is deposited between the surface of the gate, the metal source, and the semiconductor epitaxial layer.

[0018] The beneficial effects of a trench-gate superjunction VDMOS device of the present utility model are as follows:

[0019] 1. In the present utility model, a heavily doped P-well layer 1 is formed by ion implantation between adjacent VDMOS cells, and since the lightly doped layer has a relatively low charge conduction effect, when the switching transistor conducts, due to the constraints of the lightly doped layer and the heavily doped P-well layer 1, the injection of non-equilibrium carriers is reduced, and the reverse recovery charge is decreased.

[0020] 2. The utility model forms a lightly doped layer by implanting low-concentration impurities between adjacent VDMOS cells. In this way, the lightly doped layer can reduce the injection of non-equilibrium carriers, and at the same time, it also retains the ability of charges to flow mutually in the diffusion layers of adjacent cells, avoiding uneven charge conduction between cells when the VDMOS device is turned on and exacerbating the device loss.

[0021] 3. The utility model divides multiple levels by implanting ions with different concentrations into the diffusion layer, and the doping concentration is higher closer to the gate position. In this way, it can not only reduce the on-resistance after the formation of the charge channel, but also improve the voltage tolerance of the VDMOS device. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The following further describes the present utility model in detail with reference to the drawings and specific implementation methods.

[0023] Figure 1 It is a schematic diagram of the JFET region in the present utility model;

[0024] Figure 2 It is a schematic diagram of the structure of a single VDMOS cell in the present utility model;

[0025] Figure 3 It is a schematic diagram of the structure of the VDMOS device in the present utility model.

[0026] In the figure: 1. Drain; 2. Substrate layer; 3. Diffusion layer; 4. Metal source; 5. Gate oxide layer; 6. Gate; 7. Heavily doped N-well layer; 8. Lightly doped P-well layer 1; 9. Heavily doped P-well layer 1; 10. Heavily doped P-well layer 2; 201. Conductive substrate layer; 202. Inhibiting substrate layer; 203. Impurities; 301. Lightly doped diffusion layer 1; 302. Lightly doped layer; 303. Lightly doped diffusion layer 2; 304. Lightly doped diffusion layer 3; 305. Heavily doped diffusion layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0028] As Figure 1As shown in the figure, a trench-gate superjunction VDMOS device includes a VDMOS device composed of a plurality of VDMOS cells. The VDMOS device includes a drain 1, a semiconductor epitaxial layer, a metal source 4, and a gate 6. The semiconductor epitaxial layer includes a substrate layer 2, a diffusion layer 3, a P-well layer, and a heavily doped N-well layer 7. Among them, the N-well layer is isolated from the diffusion layer 3 by the P-well layer. A gate oxide layer 5 is deposited between the surface of the gate 6, the metal source 4, and the semiconductor epitaxial layer. The gate oxide layer 5 is used to isolate the gate charge from entering the interior of the semiconductor epitaxial layer, ensuring the formation of the gate electric field and the intervention of the charge inside the P-well layer. When a gate voltage is applied to the gate 6, a depletion layer JFET region is formed inside the diffusion layer 3. The JFET region is located between two adjacent heavily doped P-well layers 9. If a positive gate voltage is applied, a reverse depletion layer is formed between the gate 6 and the substrate 1, blocking the transmission of free carriers, thereby reducing the charge density in the channel. When the reverse depletion layer expands to a certain extent, the channel region is truncated, and the current cannot pass, reaching the cut-off state.

[0029] Among them, the P-well layer includes a lightly doped P-well layer 8, a heavily doped P-well layer 9, and a heavily doped P-well layer 10. The substrate layer 2 includes a conducting substrate layer 201 and a suppressing substrate layer 202. The diffusion layer 3 is formed by ion implantation of different concentrations of phosphorus elements to form a lightly doped diffusion layer 301, a lightly doped diffusion layer 303, a lightly doped diffusion layer 304, a heavily doped diffusion layer 305, and a lightly doped layer 302. The lightly doped layer 302 is formed by injecting low-concentration impurities between adjacent VDMOS cells. In this way, the lightly doped layer 302 can reduce the injection of non-equilibrium carriers and at the same time retain the charge flow between the diffusion layers 3 of adjacent cells, avoiding uneven charge conduction between cells when the VDMOS device is turned on and exacerbating the device loss.

[0030] In this embodiment, as Figure 2 shown, the doping concentration of the lightly doped P-well layer 8 is 6.3 - 8.7×10 16 mol / cm 3 .

[0031] The doping concentrations of the heavily doped N-well layer 7 and the heavily doped diffusion layer 305 are both 2.2 - 5.4×10 18 mol / cm 3 ;

[0032] The doping concentration of the lightly doped diffusion layer 304 is 8.2 - 9.7×10 16 mol / cm 3 ;

[0033] The doping concentration of the lightly doped diffusion layer 303 is 4 - 7×10 16 mol / cm 3 ;

[0034] The doping concentration of the lightly doped layer 302 is 1.7 - 3×10 15 mol / cm 3 ;

[0035] The doping concentration of the first lightly doped diffusion layer 301 is 1 - 2.7×10 16 mol / cm 3 .

[0036] In this embodiment, as Figure 2 shown, when the gate 6 is connected to the gate voltage, the charges inside the first lightly doped P-well layer 8 gather towards the gate 6 under the intervention of the gate electric field and form a charge channel. After the charge channel connects the heavily doped N-well layer 7 and the diffusion layer 3, its drain 1 and the metal source 4 resume the conducting state, where the diffusion layer 3 and the substrate layer 2 are conductively connected to each other, and the substrate layer 2 is in ohmic contact with the drain 1, while the heavily doped N-well layer 7 is directly in ohmic contact with the metal source 4.

[0037] In this embodiment, as Figure 3 shown, the first heavily doped P-well layer 9 and the second heavily doped P-well layer 10 between adjacent VDMOS cells are integrated as a whole. This integrated design can greatly reduce the manufacturing difficulty of the VDMOS device and can be formed only by ion implantation. The incorporation of high-energy-level impurities 203 into the substrate layer 202 is inhibited, where the energy level of the high-energy-level impurities 203 is at least 0.4 eV above the valence band bottom, and the material of the impurities 203 can specifically be In, Ti, or Zn. The high-energy-level impurities 203 can restrict the drain charges to mainly gather within the corresponding cells, and the high-energy-level impurities 203 will also generate an ionization layer to further restrict the charges to mainly flow along the direction of the gate electric field.

[0038] Certainly, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples either. Changes, modifications, additions, or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also belong to the protection scope of the present invention.

Claims

1. A trench gate super junction VDMOS device, characterized in that: A VDMOS device composed of a plurality of VDMOS cells, wherein the VDMOS device comprises a drain (1), a semiconductor epitaxial layer, a metal source (4) and a gate (6); The semiconductor epitaxial layer comprises a substrate layer (2), a diffusion layer (3), a P-well layer and a heavily doped N-well layer (7), wherein the N-well layer and the diffusion layer (3) are isolated from each other by the P-well layer; Wherein, the P-well layer includes a lightly doped P-well layer 1 (8), a heavily doped P-well layer 1 (9) and a heavily doped P-well layer 2 (10); The substrate layer (2) comprises a conductive substrate layer (201) and an inhibiting substrate layer (202); The diffusion layer (3) is formed into a lightly doped diffusion layer 1 (301), a lightly doped diffusion layer 2 (303), a lightly doped diffusion layer 3 (304), a heavily doped diffusion layer (305) and a lightly doped layer (302) by ion implantation of phosphorus elements of different concentrations.

2. The trench gate super junction VDMOS device according to claim 1, characterized in that: When the gate (6) applies a gate voltage, a depletion layer JFET region is formed inside the diffusion layer (3), wherein the JFET region is located between two adjacent heavily doped P-well layers (9).

3. The trench gate super junction VDMOS device according to claim 2, characterized in that: Furthermore, when the gate (6) is connected to a gate voltage, the internal charges of the lightly doped P-well layer (8) gather toward the gate (6) under the intervention of the gate electric field and form a charge channel.

4. The trench gate super junction VDMOS device according to claim 3, characterized in that: After the charge channel is connected to the heavily doped N-well layer (7) and the diffusion layer (3), the drain (1) and the metal source (4) are restored to a conducting state.

5. The trench gate super junction VDMOS device according to claim 1, characterized in that: The heavily doped P well layer 1 (9) and the heavily doped P well layer 2 (10) between adjacent VDMOS cells are integrated as one.

6. The trench-gate superjunction VDMOS device according to claim 1, characterized in that: A gate oxide layer (5) is deposited between the surface of the gate (6), the metal source (4) and the semiconductor epitaxial layer.

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