Semiconductor cellular structure, semiconductor device, electronic apparatus, and vehicle

Abstract

The utility model discloses a semiconductor cellular structure, a semiconductor device, an electronic device and a vehicle. The semiconductor cellular structure comprises a plurality of drift regions of a first conductive type and a plurality of doped regions of a second conductive type. The doped regions and the drift regions are alternately arranged in the transverse direction of the semiconductor cellular structure to form a super junction structure, and the drift regions are higher than the doped regions in the longitudinal direction of the semiconductor cellular structure to form grooves with the upper surfaces of the doped regions as groove bottoms; and the Schottky metal layer covers the upper surface of each drift region and each groove. The semiconductor cellular structure provided by the utility model can give consideration to high voltage resistance of reverse working and low conduction voltage drop of forward working of a device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and in particular to a semiconductor cell structure, as well as a semiconductor device, an electronic device and a vehicle including the semiconductor cell structure. Background Art

[0002] In the prior art, semiconductor devices such as diodes, specifically, silicon carbide Schottky diodes for example, mainly include a planar structure or a trench structure. However, neither of these two structures can take into account both the problems of high reverse breakdown voltage and low forward conduction voltage drop. Summary of the Utility Model

[0003] The utility model aims to at least solve one of the technical problems existing in the prior art. To this end, an object of the utility model is to propose a semiconductor cell structure. By adopting this semiconductor cell structure, the advantages of high reverse breakdown voltage and low forward conduction voltage drop of the device can be taken into account.

[0004] A second object of the utility model is to propose a semiconductor device.

[0005] A third object of the utility model is to propose an electronic device.

[0006] A fourth object of the present utility model is to propose a vehicle.

[0007] To achieve the above object, the semiconductor cell structure proposed in the first aspect embodiment of the utility model includes: a plurality of drift regions of a first conductivity type; a plurality of doping regions of a second conductivity type, and the plurality of doping regions and the plurality of drift regions are alternately arranged along the transverse direction of the semiconductor cell structure to form a superjunction structure. Wherein, in the longitudinal direction of the semiconductor cell structure, the height of the drift region is greater than the height of the doping region to form a trench with the upper surface of the doping region as the bottom of the trench; a Schottky metal layer, and the Schottky metal layer covers the upper surface of each drift region and each trench.

[0008] According to the semiconductor cell structure of the utility model, by forming a doping region of a second conductivity type at the position corresponding to the bottom of the trench of the Schottky metal layer, a superjunction structure is formed with the drift region of a first conductivity type. The superjunction structure will form a depletion layer under the action of an electric field, thereby preventing the flow of current, which can increase the breakdown voltage and improve the reverse breakdown voltage performance. And by adopting a trench structure, the Schottky contact area of the drift region is increased, which can increase the current path during forward operation and reduce the voltage drop during forward conduction. Therefore, the semiconductor cell structure of the utility model can take into account the high breakdown voltage during reverse operation and the low conduction voltage drop during forward operation of the device.

[0009] In some embodiments, the width of the doped region along the transverse direction is greater than the width of the trench metal layer along the transverse direction, where the trench metal layer is the portion of the Schottky metal layer within the trench.

[0010] In some embodiments, the doped region is wider than the trench metal layer along the transverse direction on one side corresponding to the trench metal layer.

[0011] In some embodiments, the doped region is wider than the trench metal layer along the transverse direction on both sides corresponding to the trench metal layer.

[0012] In some embodiments, the semiconductor cell structure further includes: a substrate layer of a first conductivity type, and the superjunction structure is located on the front surface of the substrate layer.

[0013] In some embodiments, the semiconductor cell structure further includes: an ohmic metal layer, and the ohmic metal layer is located on the back surface of the substrate layer away from the superjunction structure.

[0014] In some embodiments, the superjunction structure includes: a first drift region of the first conductivity type, a second drift region of the first conductivity type, and a third drift region of the first conductivity type, and the first drift region, the second drift region, and the third drift region are arranged at intervals along the transverse direction.

[0015] In some embodiments, the superjunction structure further includes: a first doped region of the second conductivity type and a second doped region of the second conductivity type, and the first drift region, the first doped region, the second drift region, the second doped region, and the third drift region are arranged and connected in sequence along the transverse direction.

[0016] To achieve the above object, a semiconductor device according to an embodiment of the second aspect of the present invention includes at least one of the above semiconductor cell structures.

[0017] According to the semiconductor device of the embodiment of the present invention, by adopting the semiconductor cell structure of the above embodiment, the high breakdown voltage during the reverse operation of the device and the low on-state voltage drop during the forward operation can be taken into account, and the device performance can be improved.

[0018] In some embodiments, the semiconductor device includes a plurality of the semiconductor cell structures, and the plurality of semiconductor cell structures are arranged along the transverse direction of the device.

[0019] In some embodiments, the semiconductor device includes a silicon carbide diode.

[0020] To achieve the above object, an electronic device according to an embodiment of the third aspect of the present invention includes at least one of the above semiconductor devices.

[0021] An electronic device according to an embodiment of the present utility model, by adopting the semiconductor device of the above embodiment, the semiconductor device can take into account the low conduction voltage drop in the forward operation and the high breakdown voltage in the reverse operation, improving the device performance.

[0022] To achieve the above object, a vehicle proposed in the fourth aspect embodiment of the present utility model includes the above-mentioned electronic device.

[0023] A vehicle according to an embodiment of the present utility model, by adopting the electronic device of the above embodiment, the semiconductor device of the electronic device can take into account the low conduction voltage drop in the forward operation and the high breakdown voltage in the reverse operation, improving the stability of the vehicle when using this electronic device.

[0024] The additional aspects and advantages of the present utility model will be partially given in the following description, partially become obvious from the following description, or be understood through the practice of the present utility model. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above and / or additional aspects and advantages of the present utility model will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, wherein:

[0026] Figure 1 is a cross-sectional schematic diagram of a semiconductor cell structure according to an embodiment of the present utility model;

[0027] Figure 2 is a flowchart of the preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0028] Figure 3 is a schematic diagram of the first preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0029] Figure 4 is a schematic diagram of the second preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0030] Figure 5 is a schematic diagram of the third preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0031] Figure 6 is a schematic diagram of the fourth preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0032] Figure 7 is a schematic diagram of the fifth preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0033] Figure 8 is a schematic diagram of the sixth preparation process of a semiconductor cell structure according to an embodiment of the present utility model;

[0034] Figure 9 It is a schematic diagram of the seventh step in the preparation process of a semiconductor cell structure according to an embodiment of the present invention;

[0035] Figure 10 It is a block diagram of a semiconductor device according to an embodiment of the present invention;

[0036] Figure 11 It is a block diagram of an electronic device according to an embodiment of the present invention;

[0037] Figure 12 It is a block diagram of a vehicle according to an embodiment of the present invention.

[0038] Reference numerals:

[0039] Vehicle 1000;

[0040] Electronic device 200;

[0041] Semiconductor device 100;

[0042] Semiconductor cell structure 10;

[0043] Substrate layer 1, drift region 2, doping region 3, trench 4, Schottky metal layer 5, ohmic metal layer 6, first drift region 11, first doping region 21, second drift region 12, second doping region 22, and third drift region 13. Detailed implementation manners

[0044] The embodiments of the present invention will be described in detail below. The embodiments described with reference to the drawings are exemplary. The embodiments of the present invention will be described in detail below.

[0045] Reference will be made below to Figures 1-9 Describe a semiconductor cell structure according to an embodiment of the present invention.

[0046] Figure 1 It is a schematic diagram of a semiconductor cell structure according to an embodiment of the present invention.

[0047] As Figure 1 shown, the semiconductor cell structure 10 of the embodiment of the present invention includes a plurality of drift regions 2 of a first conductivity type, a plurality of doping regions 3 of a second conductivity type, and a Schottky metal layer 5.

[0048] Among them, the first conductivity type can be P-type or N-type, the second conductivity type can be N-type or P-type, and the conductivity types of the first conductivity type and the second conductivity type are opposite.

[0049] Multiple doping regions 3 and multiple drift regions 2 are alternately arranged along the transverse direction of the semiconductor cell structure 3, that is, the drift regions 2 of the first conductivity type and the doping regions 3 of the second conductivity type are alternately arranged. By controlling the doping concentration and the region width, the two types of semiconductor regions form a superjunction structure. Under the action of an electric field, a depletion layer will be formed in the superjunction structure, thereby preventing the flow of current, which can increase the breakdown voltage and improve the voltage withstand performance of the device.

[0050] Wherein, in the longitudinal direction of the semiconductor cell structure 10, the height of the drift region 2 is greater than the height of the doping region 3, thereby forming a trench 4 with the upper surface of the doping region 3 as the trench bottom.

[0051] The Schottky metal layer 5 covers the upper surface of each drift region 2 and each trench, that is, as Figure 1 shown, the Schottky metal layer 5 has a trench 4, and the Schottky metal layer 5 forms a Schottky contact with the drift region 2.

[0052] That is, the semiconductor cell structure 10 of the embodiment of the present invention adopts a trench structure. In this way, the Schottky contact area of the drift region 2 is increased, the current path during forward operation can be increased, and the forward conduction voltage drop can be reduced, that is, the advantage of low forward conduction voltage can be ensured.

[0053] Moreover, although the semiconductor cell structure 10 of the present application adopts a trench structure, at the same time, the doping region 3 of the second conductivity type at the bottom of the trench, such as a P pillar, can shield the electric field at the bottom of the trench of the Schottky metal layer 5, which is beneficial to reducing the reverse leakage current of the device and improving the reliability of the device.

[0054] According to the semiconductor cell structure 10 of the present invention, by forming a doping region of the second conductivity type at the position corresponding to the trench bottom of the Schottky metal layer 5, a superjunction structure is formed with the drift region of the first conductivity type. Under the action of an electric field, a depletion layer will be formed in the superjunction structure, thereby preventing the flow of current, which can increase the breakdown voltage and improve the reverse voltage withstand performance. And by adopting a trench structure, the Schottky contact area of the drift region 2 is increased, the current path during forward operation can be increased, and the forward conduction voltage drop can be reduced. Therefore, the semiconductor cell structure 10 of the present invention can take into account the high voltage withstand of the device during reverse operation and the low conduction voltage drop during forward operation.

[0055] In some embodiments, the part of the Schottky metal layer 5 corresponding to the trench can be called a trench metal layer. The width of the doping region 3 along the transverse direction is greater than the width of the trench metal layer along the transverse direction. During reverse conduction, it is beneficial to reduce the reverse leakage current of the device and improve the reliability of the device.

[0056] Furthermore, in some embodiments, the doping region 3 is wider than the trench metal layer along the transverse direction of the semiconductor cell structure on one side corresponding to the trench metal layer. In this way, it is beneficial to reduce the reverse leakage current of the device and improve the reliability of the device.

[0057] Alternatively, in some embodiments, the doped regions are wider than the trench metal layer on both sides of the corresponding trench metal layer along the lateral direction of the semiconductor cell structure. In this way, the reverse leakage current of the device can be better reduced and the reliability of the device can be improved.

[0058] As Figure 1 shown, the semiconductor cell structure 10 further includes a substrate layer 1 of the first conductivity type, and a superjunction structure, that is, a plurality of drift regions 2 and doped regions 3 alternately arranged along the lateral direction, located on the front surface of the substrate layer 1.

[0059] The semiconductor cell structure 3 further includes an ohmic metal layer 6, and the ohmic metal layer 6 is located on the back surface of the substrate layer 1 away from the superjunction structure, and the ohmic metal layer 6 forms an ohmic contact with the substrate layer 1.

[0060] In an embodiment, as Figure 1 shown, the superjunction structure is arranged such that three drift regions and two doped regions are alternately arranged along the lateral direction. It can be understood that more drift regions and doped regions can also be used to form the superjunction structure.

[0061] For example, as Figure 1 shown, the superjunction structure includes a first drift region 11, a second drift region 12, a third drift region 13, a first doped region 21, and a second doped region 22.

[0062] Among them, the first drift region 11, the second drift region 12, and the third drift region 12 are arranged at intervals along the lateral direction of the semiconductor cell structure. The first drift region 11, the first doped region 21, the second drift region 12, the second doped region 22, and the third drift region 13 are arranged and connected in sequence along the lateral direction of the semiconductor cell structure 3. And by controlling the doping concentration and width of each region, a superjunction structure is formed to achieve the effect of shielding the electric field at the bottom of the trench of the Schottky metal layer 5 and improving the reverse breakdown voltage performance.

[0063] Next, taking the SIC Schottky diode as an example, the preparation process of the semiconductor cell structure of the present invention will be described. Among them, the first conductivity type is N-type and the second conductivity type is P-type.

[0064] Figure 2 is a flowchart of the preparation process of the semiconductor cell structure according to an embodiment of the present invention. As Figure 2 shown, the preparation process includes:

[0065] S1, providing an N + -type SiC single crystal substrate.

[0066] S2, growing an N-type silicon carbide epitaxial layer on the silicon carbide substrate.

[0067] For example, an epitaxial device is used to grow an N-type silicon carbide epitaxial layer with a desired concentration and thickness on a SiC substrate as the SiC drift layer.

[0068] S3, a window is etched on the silicon carbide epitaxial layer by using photolithography technology, and then P-type doping ions are implanted into the window.

[0069] A mask is deposited on the SiC drift layer, and P-type impurities are implanted into the N-type SiC drift layer by using technologies such as photolithography and etching to form P-type silicon carbide 3. The doping concentration, width, and spacing between the P-type silicon carbides are precisely calculated to form a lateral depletion electric field during reverse operation, forming a superjunction structure.

[0070] S4, N-type silicon carbide is epitaxially grown on the wafer after the ion implantation, and then a window at the same position as the previous implantation is etched by using photolithography technology, and P-type impurities are continuously implanted. The epitaxial growth and ion implantation are repeated multiple times to form an alternating structure of P-doped regions and N-drift regions.

[0071] Specifically, after the P-type implantation is completed, the epitaxial device is continued to be used to grow an epitaxial layer with the same concentration as in step (2) above the implanted wafer. After the secondary epitaxial growth of the SiC drift layer is completed, P-type impurities are continuously implanted above the wafer by using technologies such as masks, photolithography, and etching to form P-type silicon carbide. The P-type implantation position is consistent with the position in step S3. The epitaxial growth and ion implantation technologies are recycled multiple times to form P-type and N-type SiC structures with the desired concentration and thickness.

[0072] S5, an N-type silicon carbide epitaxial layer is continuously grown on the wafer forming the superjunction structure of P-doped regions and N-drift regions.

[0073] Specifically, after the P-region SiC and the N-region SiC are formed, an N-type SiC drift layer is continuously epitaxially grown on the front side of the wafer to obtain the desired wafer.

[0074] S6, trenches are etched on the front side of the wafer. The trenches are located above the P-doped region and extend to the P layer, and the width is slightly shorter than the width of the P-doped region.

[0075] Specifically, trenches are etched on the front side of the wafer. The trenches are located directly above the P-region, the trench width is shorter than the P-region width, and the trench depth extends to the P-region.

[0076] S7, metal is deposited on the back side of the substrate to form an ohmic contact, and metal is deposited on the front side of the substrate to form a Schottky contact.

[0077] Specifically, Schottky metal is deposited on the front side of the wafer to form a Schottky contact with the N-type SiC, and then ohmic contact metal is deposited on the back side of the wafer to form an ohmic contact with the N + SiC substrate to obtain a SiC superjunction Schottky diode.

[0078] Among them, in the embodiment, N + -type substrate is heavily doped. For example, the heavy doping concentration is 1×10 18 cm -3 or more. The N-type SiC drift layer is formed by multiple epitaxial growths. The P-type SiC region is formed by multiple ion implantations. As a further improvement of the above technical solution, the concentration of the N-type SiC can be 1×10 15 cm -3 -1×10 17 cm -3 , and the thickness of the N-type single epitaxial growth does not exceed the effective depth of the P-type ion implantation. The concentration of the P-type SiC is 1×10 15 cm -3 -1×10 17 cm -3 . The superjunction structure is composed of alternating arrangements of N regions formed by N-type SiC and P regions formed by P-type SiC, and the product of the width and concentration of the N region is approximately the same as the product of the width and concentration of the P region.

[0079] In the embodiment of the present utility model, in order to reduce the forward conduction voltage drop, a trench structure is adopted, which can effectively increase the Schottky contact area, thereby increasing the overcurrent path and reducing the forward voltage drop. In the present utility model, the trench structure is arranged above the P region, and the trench width is shorter than the P region width, and the trench depth extends to the P region, which can make the P region shield the electric field at the bottom of the trench, which is beneficial to reducing the reverse leakage of the device and the reliability of the device. The present utility model can balance the performance of both reverse breakdown voltage and forward voltage drop.

[0080] Figures 3-9 The process flow for preparing a semiconductor cell structure according to an embodiment of the present utility model is as follows.

[0081] As Figure 3 shown, first, an N + -type SiC single crystal substrate is epitaxially grown with an N-type SiC epitaxial layer.

[0082] As Figure 4 shown, using technologies such as masking, photolithography, and etching, P-type impurities are implanted into the epitaxially grown SiC epitaxial layer.

[0083] As Figure 5 shown, an N-type SiC epitaxial layer is continuously epitaxially grown on the wafer after the P-type impurity implantation is completed.

[0084] As Figure 6As shown, continue to use technologies such as masking, photolithography, and etching to implant P-type impurities into the grown N-type SiC epitaxial layer at the same position on the surface as the previous P implantation; alternately use epitaxial growth and ion implantation multiple times to obtain a wafer with the desired thickness.

[0085] As Figure 7 shown, continue to epitaxially grow an N-type SiC epitaxial layer on the obtained wafer.

[0086] As Figure 8 shown, etch trenches on the front side of the wafer. The position of the trenches is directly above the P-type SiC. The width of the trenches is shorter than the width of the P-type silicon carbide, and the trench depth extends to the position of the P-type SiC.

[0087] As Figure 9 shown, deposit metal Al on the front side of the wafer to form a Schottky contact electrode with the N-type front SiC; then deposit Ni and Ag metals on the back side of the wafer to form an ohmic contact.

[0088] In the embodiment of the present invention, epitaxial growth and ion implantation are alternately used multiple times to form a superjunction structure of P-type SiC and N-type SiC, which can greatly improve the breakdown voltage of the Schottky diode and reduce its on-resistance.

[0089] To further reduce the voltage drop during the forward operation of the device, the method of etching trenches is adopted on the front side to increase the area of the Schottky contact. Moreover, the etched trenches are directly above the P-type SiC, and the width of the trenches is shorter than the width of the P-type SiC and is surrounded by the P-type SiC. When the device operates under reverse breakdown voltage conditions, the P-type can serve as an electric field shielding structure for the trenches, reducing the electric field at the bottom of the trenches, thereby reducing the leakage current during the reverse operation of the device. The lower electric field at the bottom of the trenches is also beneficial to improving the reliability of the device.

[0090] The semiconductor cell structure 10 of the embodiment of the present invention can improve the performance of the device, such as a SiC Schottky diode, during both forward and reverse operations.

[0091] Based on the semiconductor cell structure of the above embodiment, the second aspect of the embodiment of the present invention proposes a semiconductor device.

[0092] Figure 10 is a block diagram of a semiconductor device according to an embodiment of the present invention. As Figure 10 shown, the semiconductor device 100 includes at least one semiconductor cell structure 10 as in the above embodiment.

[0093] In the embodiment, the semiconductor device 100 can be a fast recovery diode, specifically, for example, it can include a SIC Schottky diode.

[0094] According to the semiconductor device 100 of the embodiment of the present utility model, by adopting the semiconductor cell structure 10 of the above embodiment, the high breakdown voltage during the reverse operation of the device and the low on-state voltage drop during the forward operation can be taken into account, improving the device performance.

[0095] In some embodiments, the semiconductor device 100 includes one semiconductor cell structure of the above embodiment or may also adopt multiple semiconductor cell structures. For example, multiple semiconductor cell structures are arranged horizontally along the device.

[0096] In an embodiment, the semiconductor device 100 may include a silicon carbide diode or a diode of other materials, which is not specifically limited herein.

[0097] Based on the semiconductor device of the above embodiment, the third aspect embodiment of the present utility model proposes an electronic device. Figure 11 It is a block diagram of an electronic device according to an embodiment of the present utility model. As Figure 11 shown, the electronic device 200 of the embodiment of the present utility model includes at least one semiconductor device of the above embodiment.

[0098] For example, the electronic device 200 may include a power device such as an IGBT device or the like.

[0099] According to the electronic device 200 of the embodiment of the present utility model, by adopting the semiconductor device 100 of the above embodiment, the semiconductor device 100 can take into account the low on-state voltage drop during the forward operation and the high breakdown voltage during the reverse operation, improving the device performance of the equipment.

[0100] Based on the electronic device of the above embodiment, the fourth aspect embodiment of the present utility model proposes a vehicle. As Figure 12 shown, the vehicle 1000 includes the electronic device 200 of the above embodiment.

[0101] According to the vehicle 1000 of the embodiment of the present utility model, by adopting the electronic device 200 of the above embodiment, the semiconductor device of the electronic device 200 can take into account the low on-state voltage drop during the forward operation and the high breakdown voltage during the reverse operation, improving the stability of the vehicle when using the electronic device 200 for operation.

[0102] In the description of this specification, the description with reference to terms such as "one embodiment", "some embodiments", "schematic embodiments", "examples", "specific examples", or "some examples" etc. means that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic expressions of the above terms do not necessarily refer to the same embodiment or example.

[0103] Although embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention. The scope of the present invention is defined by the claims and their equivalents.

Claims

1. A semiconductor cell structure, characterized in that: include: a plurality of drift regions of a first conductivity type; A plurality of doped regions of the second conductivity type, wherein the plurality of doped regions and the plurality of drift regions are alternately arranged in a lateral direction of the semiconductor cell structure to form a super junction structure, wherein in a longitudinal direction of the semiconductor cell structure, a height of the drift region is greater than a height of the doped region to form a groove with an upper surface of the doped region as a groove bottom; A Schottky metal layer covers an upper surface of each of the drift regions and each of the trenches.

2. The semiconductor cell structure according to claim 1, characterized in that: The width of the doped region along the lateral direction is greater than the width of the trench metal layer along the lateral direction, wherein the trench metal layer is a portion of the Schottky metal layer within the trench.

3. The semiconductor cell structure according to claim 2, characterized in that: The doped region is wider than the trench metal layer at a side corresponding to the trench metal layer along the lateral direction.

4. The semiconductor cell structure according to claim 2, characterized in that: The doped region is wider than the trench metal layer at both sides corresponding to the trench metal layer along the lateral direction.

5. The semiconductor cell structure according to any one of claims 1 to 4, characterized in that: The semiconductor cell structure further includes: a substrate layer of a first conductivity type, and the super junction structure is located on the front side of the substrate layer.

6. The semiconductor cell structure according to claim 5, characterized in that: The semiconductor cell structure further includes an ohmic metal layer, which is located on the back side of the substrate layer away from the super junction structure.

7. The semiconductor cell structure according to any one of claims 1 to 4, characterized in that: The super junction structure comprises: A first drift region of a first conductivity type, a second drift region of the first conductivity type and a third drift region of the first conductivity type are arranged at intervals along the lateral direction.

8. The semiconductor cell structure according to claim 7, characterized in that: The super junction structure further includes: The first doped region of the second conductivity type and the second doped region of the second conductivity type, the first drift region, the first doped region, the second drift region, the second doped region and the third drift region are sequentially arranged and connected along the transverse direction.

9. A semiconductor device, characterized in that: Comprising at least one semiconductor cell structure according to any one of claims 1 to 8.

10. The semiconductor device according to claim 9, characterized in that The semiconductor device comprises a plurality of the semiconductor cell structures, and the plurality of the semiconductor cell structures are arranged laterally along the device.

11. The semiconductor device according to claim 9 or 10, characterized in that: The semiconductor device includes a silicon carbide diode.

12. An electronic device, characterized in that: The method comprises at least one semiconductor device according to any one of claims 9 to 11.

13. A vehicle, characterized in that: The vehicle includes the electronic device of claim 12.

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