Limit current measuring device for ceramic chip

Abstract

The utility model discloses a ceramic chip limiting current measuring device in the technical field of chip testing, which comprises a ceramic chip and an output module used for outputting voltage signals, and the output module comprises a sampling resistor; the gating module is provided with three channels which are sequentially connected with the three electrodes of the ceramic chip; the acquisition module is used for acquiring voltage difference between two ends of the sampling resistor; the main control module is used for controlling the output module to output a voltage signal to the gating module and controlling three channels of the gating module to be opened in sequence so as to switch on three electrodes of the ceramic chip in sequence and calculate limiting current; the power supply module is used for providing voltage; one path of output is realized by adopting one gating module so as to control and measure limiting current of three electrodes of the ceramic chip; the size of the sampling resistor is changed by adopting the analog switch U1, so that the sampling voltage ranges finally obtained by limiting currents in different order of magnitude ranges are approximately the same, the sampling resolution is improved, and the characteristics of the ceramic chip are accurately reflected.

Description

Technical Field

[0001] The utility model relates to the technical field of chip testing, in particular to a device for measuring the ultimate current of a ceramic chip. Background Art

[0002] The manufacturing process of the nitrogen oxide sensor chip is extremely complex. After the nitrogen oxide sensor chip is manufactured, it is necessary to strictly detect its pumping current to determine whether it is qualified.

[0003] The ceramic chip has three electrodes for which the ultimate current needs to be measured. According to the characteristics of the ceramic chip, the ultimate currents of two of its electrodes are in the mA level, and the ultimate current of the other electrode is in the μA level. If it is not within this range, it indicates that the ceramic chip is unqualified.

[0004] For a qualified ceramic chip, when measuring the ultimate currents of the three electrodes within the known range of the ceramic chip, the prior art measures the current value of the nitrogen oxide sensor ceramic chip under closed-loop control, rather than the ultimate current value that the pumping electrode can reach. Therefore, it cannot accurately reflect the characteristics of the ceramic chip. Summary of the Utility Model

[0005] The purpose of this part is to outline some aspects of the embodiments of the utility model and briefly introduce some preferred embodiments. Simplifications or omissions may be made in this part, as well as in the abstract and the title of the utility model, to avoid obscuring the purpose of this part, the abstract, and the title. However, such simplifications or omissions shall not be used to limit the scope of the utility model.

[0006] Therefore, the purpose of the utility model is to provide a device for measuring the ultimate current of a ceramic chip, which uses 1 gating module to achieve 1-way output to control and measure the ultimate currents of the three electrodes of the ceramic chip; uses an analog switch U1 to change the size of the sampling resistor, so that the sampling voltage ranges obtained for the ultimate currents in different order-of-magnitude ranges are roughly the same, improving the sampling resolution; uses a three-pin voltage regulator and voltage-dividing resistors to achieve a constant output voltage of 0.5V. The circuit structure is simple, the voltage accuracy is high, and it can accurately reflect the characteristics of the ceramic chip.

[0007] To solve the above technical problems, the present utility model provides a device for measuring the ultimate current of a ceramic chip, adopting the following technical solutions: It includes a ceramic chip, and further includes an output module for outputting a voltage signal, where the output module includes a sampling resistor; a gating module having three channels sequentially connected to three electrodes of the ceramic chip; an acquisition module for acquiring the voltage difference across the sampling resistor; a main control module for controlling the output module to output a voltage signal to the gating module, controlling the three channels of the gating module to be sequentially opened to sequentially connect the three electrodes of the ceramic chip, and calculating the ultimate current based on the known sampling resistor and the voltage difference acquired by the acquisition module; and a power supply module for providing voltage.

[0008] Optionally, the output module includes a voltage regulator chip T1, voltage-dividing resistors, and an operational amplifier U2. The voltage regulator chip T1 and the operational amplifier U2 are both connected to the supply voltage VCC. The output terminal of the voltage regulator chip T1 is connected to the first equipotential pin of the operational amplifier U2 through the voltage-dividing resistors. The second equipotential pin of the operational amplifier U2 is connected to the ceramic chip through the gating module. The third equipotential pin of the operational amplifier U2 is connected to the sampling resistor.

[0009] Optionally, the voltage-dividing resistors include a resistor R5 and a resistor R6. The voltage regulator chip T1 adopts a three-pin voltage regulator. The pin 2 of the voltage regulator chip T1 is connected to the supply voltage VCC through a resistor R4. The pin 1 of the voltage regulator chip T1 is connected to the first end of the resistor R5 with the pin 2. The pin 3 of the voltage regulator chip T1 is connected to the first end of the resistor R6. The second ends of the resistor R5 and the resistor R6 are both connected to the pin 3 of the operational amplifier U2. The second ends of the resistor R5 and the resistor R6 are both connected to the first end of a capacitor C1. The second end of the capacitor C1 is connected to the first end of the resistor R6. The pin 4 of the operational amplifier U2 is connected to the first end of a capacitor C3 and the gating module. The pin 2 of the operational amplifier U2 is connected to the second end of the capacitor C3. The pin 5 of the operational amplifier U2 is connected to the supply voltage VCC. The pin 1 of the operational amplifier U2 is connected to the first end of a resistor R2. The second end of the resistor R2 is connected to the gating module. The pin 1 of the operational amplifier U2 is connected to the first end of a resistor R3. The second end of the resistor R3 is connected to a capacitor C7. The acquisition module is connected to the second end of the resistor R3.

[0010] Optionally, it further includes an analog switch U1. The pin 1 of the analog switch U1 is connected to the pin 1 of the operational amplifier U2. The pin 2 of the analog switch U1 is connected to the first end of a resistor R1. The second end of the resistor R1 is connected to the second end of the resistor R2. The pin 5 of the analog switch U1 is connected to the supply voltage VCC and a capacitor C9.

[0011] Optionally, the resistance value of the resistor R2 is 5.1 K ohms, and the resistance value of the resistor R1 is 680 ohms.

[0012] Optionally, the model of the analog switch U1 is TS5A3166DBVR.

[0013] Optionally, the model of the voltage regulator chip T1 is TL432.

[0014] Optionally, the model of the operational amplifier U2 is SGM8551.

[0015] Optionally, the model of the gating module is TS5A3359.

[0016] Optionally, the gating module includes pin 1, pin 2, pin 3, pin 5, pin 6, pin 7, and pin 8. The pin 1, pin 2, and pin 3 are correspondingly connected to three electrodes of the ceramic chip. The main control module controls the pin 5 and pin 6 of the gating module to realize the conduction of one of the three electrodes. The pin 7 is respectively connected to another equipotential pin of the operational amplifier U2, the second end of the resistor R2, and the second end of the resistor R1. The pin 8 is connected to the supply voltage VCC and the capacitor C8.

[0017] In summary, the present utility model includes at least one of the following beneficial effects:

[0018] 1. The main control module of the present utility model selects the three channels of the gating module to be opened in sequence, and finally outputs the voltage signal to the ceramic chip. One gating module is used to realize one-way output to control and measure the ultimate current of the three electrodes of the ceramic chip.

[0019] 2. The present utility model uses the analog switch U1 to change the size of the sampling resistor, so that the sampling voltage ranges obtained for the ultimate currents in different order-of-magnitude ranges are approximately the same, improving the sampling resolution.

[0020] 3. The present utility model uses a three-pin voltage regulator and a voltage-dividing resistor to realize an output voltage of a constant 0.5V. The circuit structure is simple, the voltage accuracy is high, and the characteristics of the ceramic chip are accurately reflected. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 It is the structural block diagram of the ultimate current measurement device of the ceramic chip of the present utility model;

[0023] Figure 2 This is the circuit diagram of the output module of the present utility model;

[0024] Figure 3 This is the circuit diagram of the gating module of the present utility model. Specific embodiments

[0025] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0026] In the description of the present utility model, it should be noted that the orientation or positional relationship indicated by the terms "upper", "lower", "inner", "outer", "top / bottom end", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model. In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance.

[0027] In the description of the present utility model, it should be noted that unless otherwise clearly defined and limited, the terms "installation", "provided with", "sheathed / connected", "connection", etc. should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can be the internal communication of two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0028] Embodiment 1

[0029] Referring to Figure 1 , the present utility model discloses a ceramic chip ultimate current measurement device, which includes a ceramic chip, and further includes an output module for outputting a voltage signal. The output module includes a sampling resistor; a gating module having three channels sequentially connected to the three electrodes of the ceramic chip; an acquisition module for acquiring the voltage difference across the sampling resistor; a main control module for controlling the output module to output a voltage signal to the gating module, controlling the three channels of the gating module to be sequentially opened to sequentially connect the three electrodes of the ceramic chip, and calculating the ultimate current according to the known sampling resistor and the voltage difference acquired by the acquisition module; and a power supply module for providing voltage.

[0030] Among them, the model of the voltage regulator chip T1 is TL432. The model of the operational amplifier U2 is SGM8551. The model of the gating module is TS5A3359.

[0031] With the above structure, the main control module controls the output module to output a voltage signal to the gating module. The gating module is a three - to - one module. The main control module selects and sequentially opens the three channels of the gating module. Finally, the voltage signal is output to the ceramic chip. The ceramic chip has three electrodes that need to measure the limit current. Each time, one electrode is selected to measure the limit current. The signal collected by the acquisition module is given to the main control module, and the main control module performs a series of processes to obtain the current signal.

[0032] In this embodiment, the output module includes a voltage regulator chip T1, a voltage - dividing resistor, and an operational amplifier U2. Both the voltage regulator chip T1 and the operational amplifier U2 are connected to the power supply voltage VCC. The output terminal of the voltage regulator chip T1 is connected to the first equipotential pin of the operational amplifier U2 through the voltage - dividing resistor. The second equipotential pin of the operational amplifier U2 is connected to the ceramic chip through the gating module. The third equipotential pin of the operational amplifier U2 is connected to the sampling resistor.

[0033] Specifically, referring to Figure 2 , the voltage - dividing resistor includes resistor R5 and resistor R6. The voltage regulator chip T1 uses a three - pin voltage regulator. Pin 2 of the voltage regulator chip T1 is connected to the power supply voltage VCC through resistor R4. Pin 1 of the voltage regulator chip T1 is connected to the first end of resistor R5 with pin 2. Pin 3 of the voltage regulator chip T1 is connected to the first end of resistor R6. The second ends of resistor R5 and resistor R6 are both connected to pin 3 of the operational amplifier U2. The second ends of resistor R5 and resistor R6 are both connected to the first end of capacitor C1. The second end of capacitor C1 is connected to the first end of resistor R6. Pin 4 of the operational amplifier U2 is connected to the first end of capacitor C3 and the gating module. Pin 2 of the operational amplifier U2 is connected to the second end of capacitor C3. Pin 5 of the operational amplifier U2 is connected to the power supply voltage VCC. Pin 1 of the operational amplifier U2 is connected to the first end of resistor R2. The second end of resistor R2 is connected to the gating module. Pin 1 of the operational amplifier U2 is connected to the first end of resistor R3. The second end of resistor R3 is connected to capacitor C7. The acquisition module is connected to the second end of resistor R3.

[0034] Referring to Figure 3 , specifically, in this embodiment, the gating module includes pin 1, pin 2, pin 3, pin 5, pin 6, pin 7, and pin 8. Pin 1, pin 2, and pin 3 are correspondingly connected to the three electrodes of the ceramic chip. The main control module controls pins 5 and 6 of the gating module to make one of the three electrodes conduct. Pin 7 is respectively connected to another equipotential pin of the operational amplifier U2, the second end of resistor R2, and the second end of resistor R1. Pin 8 is connected to the power supply voltage VCC and capacitor C8.

[0035] Embodiment 2

[0036] Refer to Figure 2 , based on the same concept as in the above Embodiment 1, the ceramic chip ultimate current measurement device further includes an analog switch U1, and the model of the analog switch U1 is TS5A3166DBVR. Pin 1 of the analog switch U1 is connected to pin 1 of the operational amplifier U2, pin 2 of the analog switch U1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the second end of the resistor R2, and pin 5 of the analog switch U1 is connected to the supply voltage VCC and the capacitor C9.

[0037] The mA-level electrode of the ceramic chip is collected through the resistor R1. By adding the analog switch U1, the resistors R2 and R1 can be used in parallel for collection. In this way, when collecting the uA-level electrode of the ceramic chip, the sampling voltage across the sampling resistor will be relatively small, the sampling resolution will become low, and the change in the sampling voltage caused by the same ultimate current change will become small; the sampling voltage is between 1 - 4V, improving the sampling resolution.

[0038] Working principle:

[0039] The voltage regulator chip T1 (model TL432) generates a constant voltage of 1.25V. After being divided by the resistors R5 and R6, the voltage at pin 3 of the operational amplifier U2 is 0.5V. The voltages at pins 3 and 4 of the operational amplifier U2 (model SGM8551) are equal, and pin 4 of the operational amplifier U2 is connected to the ceramic chip. Therefore, a stable voltage of 0.5V can be output from the Figure 2 VTEST node in to the ceramic chip.

[0040] The ceramic chip has three electrodes for which the ultimate current needs to be measured, namely No. 0, No. 1, and No. 2. The main control module controls the gating module to select which electrode current to collect, that is, by controlling pins 5 and 6 of the gating module, the VTEST node is connected to one of the three electrodes of the ceramic chip, so that a voltage of 0.5V can be applied to the corresponding electrode. At the same time, a current will flow through the sampling resistor, and this current is the ultimate current of this electrode;

[0041] Among them, the acquisition module is connected to the second end of the resistor R3 for acquiring the voltage Vacq. The first end of the resistor R3 and one end of the sampling resistor are fixed at 0.5V. Then the voltage difference across the sampling resistor is equal to Vacq - 0.5V.

[0042] Since the limit current ranges of the three electrodes 0, 1, and 2 of the ceramic chip are different, an analog switch U1 (model TS5A3166DBVR) is added to control the size of the sampling resistor. That is, when the analog switch U1 is closed, only the resistor R2 is connected as the sampling resistor to the circuit. At this time, the size of the sampling resistor is 5.1K. When the analog switch U1 is open, the resistors R1 and R2 are connected in parallel and then connected in series as the sampling resistor to the circuit. After calculation, the size of the sampling resistor is 600 ohms at this time. By collecting the voltage across the sampling resistor, the size of the limit current can be calculated. The limit current is equal to the voltage difference across the sampling resistor divided by the size of the sampling resistor at this time.

[0043] For example: The main control module controls the gating module to switch to the electrode of ceramic chip serial number 0. At this time, the output module outputs a voltage of 0.5V, and current flows through the sampling resistor. After waiting for 10 ms, the acquisition module acquires the voltage across the sampling resistor (one end is fixed at 0.5V) and returns the data to the main control module. The main control module calculates the limit current value, and then the gating module switches to the electrodes of ceramic chip serial numbers 1 and 2, repeating the above steps. Finally, the above steps are executed in a loop. When measuring the limit currents of electrodes with serial numbers 0 and 1, the analog switch U1 is open. When measuring the limit current of electrode with serial number 2, the analog switch U1 is closed.

[0044] The above are all the preferred embodiments of the present invention, and the protection scope of the present invention is not limited accordingly. Therefore, all equivalent changes made according to the structure, shape, and principle of the present invention should be covered within the protection scope of the present invention.

Claims

1. A ceramic chip limiting current measuring device, comprising a ceramic chip, characterized in that: Also includes An output module, used for outputting a voltage signal, wherein the output module comprises a sampling resistor; A gating module having three channels connected in sequence to three electrodes of the ceramic chip; A collection module, used for collecting the voltage difference between the two ends of the sampling resistor; The main control module is used to control the output module to output the voltage signal to the gating module, control the three channels of the gating module to be opened in sequence, so as to connect the three electrodes of the ceramic chip in sequence, and calculate the limit current according to the known sampling resistor and the voltage difference collected by the acquisition module; A power supply module is used to provide voltage.

2. A ceramic chip limiting current measuring device according to claim 1, characterized in that: The output module includes a voltage stabilizing chip T1, a voltage dividing resistor and an operational amplifier U2. The voltage stabilizing chip T1 and the operational amplifier U2 are both connected to the power supply voltage VCC. The output end of the voltage stabilizing chip T1 is connected to the first equal voltage pin of the operational amplifier U2 through the voltage dividing resistor. The second equal voltage pin of the operational amplifier U2 is connected to the ceramic chip through the selection module. The third equal voltage pin of the operational amplifier U2 is connected to the sampling resistor.

3. A ceramic chip limiting current measuring device according to claim 2, characterized in that: The voltage-dividing resistor includes a resistor R5 and a resistor R6. The voltage-stabilizing chip T1 adopts a three-pin voltage regulator. Pin 2 of the voltage-stabilizing chip T1 is connected to the power supply voltage VCC through a resistor R4. Pin 1 and pin 2 of the voltage-stabilizing chip T1 are connected to the first end of the resistor R5. Pin 3 of the voltage-stabilizing chip T1 is connected to the first end of the resistor R6. The second end of the resistor R5 and the second end of the resistor R6 are both connected to pin 3 of the operational amplifier U2. The second end of the resistor R5 and the second end of the resistor R6 are both connected to the first end of the capacitor C1. The second end of the capacitor C1 The operational amplifier U2 is connected to the first end of the resistor R6, the pin 4 of the operational amplifier U2 is connected to the first end of the capacitor C3 and the gating module, the pin 2 of the operational amplifier U2 is connected to the second end of the capacitor C3, the pin 5 of the operational amplifier U2 is connected to the power supply voltage VCC, the pin 1 of the operational amplifier U2 is connected to the first end of the resistor R2, the second end of the resistor R2 is connected to the gating module, the pin 1 of the operational amplifier U2 is connected to the first end of the resistor R3, the second end of the resistor R3 is connected to the capacitor C7, and the acquisition module is connected to the second end of the resistor R3.

4. A ceramic chip limiting current measuring device according to claim 3, characterized in that: It also includes an analog switch U1, wherein pin 1 of the analog switch U1 is connected to pin 1 of the operational amplifier U2, pin 2 of the analog switch U1 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the second end of the resistor R2, and pin 5 of the analog switch U1 is connected to the power supply voltage VCC and the capacitor C9.

5. A ceramic chip limiting current measuring device according to claim 4, characterized in that: The resistance value of the resistor R2 is 5.1K ohms, and the resistance value of the resistor R1 is 680 ohms.

6. A ceramic chip limiting current measuring device according to claim 4, characterized in that: The model of the analog switch U1 is TS5A3166DBVR.

7. A ceramic chip limiting current measuring device according to any one of claims 3 to 6, characterized in that: The model of the voltage regulator chip T1 is TL432.

8. A ceramic chip limiting current measuring device according to any one of claims 3 to 6, characterized in that: The model of the operational amplifier U2 is SGM8551.

9. A ceramic chip limiting current measuring device according to any one of claims 3 to 6, characterized in that: The model of the gating module is TS5A3359.

10. The ceramic chip limiting current measuring device according to claim 9, characterized in that: The gating module includes pin 1, pin 2, pin 3, pin 5, pin 6, pin 7 and pin 8, and pin 1, pin 2 and pin 3 correspond to the three electrodes connected to the ceramic chip. The main control module controls pin 5 and pin 6 of the gating module to realize the conduction of one of the three electrodes. Pin 7 is respectively connected to another equal voltage pin of the operational amplifier U2, the second end of the resistor R2 and the second end of the resistor R1, and pin 8 is connected to the power supply voltage VCC and the capacitor C8.

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