Double-antenna positioning and orientation time keeping system

Abstract

The utility model discloses a double-antenna positioning and orientation time keeping system, which comprises a computer, antennas, a receiver module, a chip module, a level conversion module and a buffer module, one end of the chip module is respectively connected with the receiver module, the level conversion module and the buffer module, and the level conversion module is used for converting a TTL level in the receiver module into a 232 level; the buffer module is used for outputting the positioning information obtained by the receiver module; the receiver module is connected with an antenna; and the other end of the chip module is connected with the computer. According to the utility model, through a double-antenna system, higher positioning precision and directivity can be provided. Different antenna receiving signals can determine the position and the moving direction of the target through the phase difference or the time difference. The receiver module is responsible for receiving signals from an antenna and carrying out preliminary data processing and demodulation. And the chip module is used for further processing the received signal and extracting positioning information.

Description

Technical Field

[0001] The utility model belongs to the technical field of wireless positioning, and specifically relates to a dual-antenna positioning, orientation and timekeeping system. Background Art

[0002] In the prior art, for example, the technical solution described in the patent with the publication number: CN218975790U: A positioning antenna and a positioning system, including a positioning antenna and a positioning system. The positioning antenna includes a bottom plate, an antenna unit and a control unit. The antenna unit includes a plurality of square radiation units, which are arranged on the upper surface of the bottom plate and are distributed in a zigzag shape around the center of the bottom plate, and are circularly polarized radiation units. The distance between adjacent square radiation units is less than or equal to the target distance, and the target distance is determined based on the wavelength of the electromagnetic wave with the highest frequency received or transmitted by the square radiation unit.

[0003] The existing GPS or BD2 single system has the following disadvantages: The single system has great deficiencies in signal continuity, positioning accuracy and reliability; when the navigation service of a certain system is interrupted, the GPS or BD2 of the single system cannot continue to work. Summary of the Invention

[0004] The purpose of the utility model is to provide a dual-antenna positioning, orientation and timekeeping system to solve the problem that in the prior art described in the background art, the single system has great deficiencies in signal continuity, positioning accuracy and reliability.

[0005] To solve the above technical problems, the technical solution adopted by the utility model is:

[0006] The dual-antenna positioning, orientation and timekeeping system includes a computer, an antenna, a receiver module, a chip module, a level conversion module and a buffer module; wherein, one end of the chip module is respectively connected to the receiver module, the level conversion module and the buffer module, and the level conversion module is used to convert the TTL level in the receiver module into a 232 level; the buffer module is used to output the positioning information obtained by the receiver module;

[0007] The receiver module is connected to the antenna; the other end of the chip module is connected to the computer, and the computer is used to receive positioning and orientation data;

[0008] The level conversion module includes a chip U7, a capacitor C14, a capacitor C16, a capacitor C18, a capacitor C20 and a capacitor C22; wherein, the 2nd pin of the chip U7 is connected to one end of the capacitor C16, and the other end of the capacitor C16 is connected to the 4th pin of the chip U7; the 5th pin of the chip U7 is connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to the 6th pin of the chip U7;

[0009] The 19th pin of chip U7 is connected to one end of capacitor C14, the 3rd pin of chip U7 is connected to one end of capacitor C18, and the 7th pin of chip U7 is connected to one end of capacitor C20; the other ends of capacitor C14, capacitor C18, and capacitor C20 are all grounded; the 14th pin of chip U7 is connected to the 20th pin.

[0010] According to the above technical solution, it further includes a power supply module, which is respectively connected to the receiving module, the chip module, the level conversion module, and the buffer module, and the power supply module is used to supply power to the receiving module, the chip module, the level conversion module, and the buffer module.

[0011] According to the above technical solution, the power supply module includes chip U5, resistor R8, capacitors C4, C5, C6, C7, C8, inductor L1, fuse F1, and diode T1; among them, one end of fuse F1 is respectively connected to the power supply and one end of diode T1, and the other end of fuse F1 is connected to inductor L1, one end of capacitor C4, and the 2nd pin of chip U5;

[0012] One end of inductor L1 is grounded, and the other end of inductor L1 is respectively connected to the other end of capacitor C4 and the 1st pin of chip U5;

[0013] The 4th pin of chip U5 is connected to one end of resistor R8, the other end of resistor R8 is grounded, the 7th pin of chip U5 is grounded, the 6th pin of chip U5 is respectively connected to the 5th pin of chip U5, and the one ends of capacitors C5, C6, C7, and C8, and the other ends of capacitors C5, C6, C7, and C8 are all grounded.

[0014] According to the above technical solution, the power supply module further includes chip U6, resistor R12, capacitors C9, C10, C11, C12, and C13; among them, the 1st pin of chip U6 is connected to one end of capacitor C9, and the other end of capacitor C9 is connected to the 2nd pin of chip U6;

[0015] The 7th pin of chip U6 is grounded, the 6th pin of chip U6 is respectively connected to the 5th pin of chip U6, and the one ends of capacitors C10, C11, C12, and C13, and the other ends of capacitors C10, C11, C12, and C13 are all grounded; the 4th pin of chip U6 is connected to one end of resistor R12, and the other end of resistor R12 is grounded.

[0016] According to the above technical solution, the antenna includes a first antenna and a second antenna; the receiver module includes a first receiver module and a second receiver module; among them, the first receiver module is connected to the first antenna, and the second receiver module is connected to the second antenna.

[0017] According to the above technical solution, the first receiver module includes chip U3, resistor R6, and capacitor C2. Among them, the pin 1 of chip U3 is connected to the power supply, the pin 5 of chip U3 is respectively connected to one end of resistor R6 and capacitor C2, the other end of resistor R6 is connected to the power supply, and the other end of capacitor C2 is grounded; the pin 2 of chip U3 is connected to the power supply;

[0018] The second receiver module includes chip U4, resistor R7, and capacitor C3. Among them, the pin 1 of chip U4 is connected to the power supply, the pin 5 of chip U4 is respectively connected to one end of resistor R7 and capacitor C3, the other end of resistor R7 is connected to the power supply, and the other end of capacitor C3 is grounded; the pin 2 of chip U4 is connected to the power supply.

[0019] According to the above technical solution, the buffer module includes chip U2, capacitor C1, resistor R1, resistor R2, resistor R3, resistor R4, resistor R5, and connector J1. Among them, the pin 1 of chip U2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the power supply; the pin 1 of connector J1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the power supply; the pins 2, 3, and 4 of connector J1 are respectively connected to one end of resistor R2, resistor R3, and resistor R4, and the other ends of resistor R2, resistor R3, and resistor R4 are respectively connected to the pin 13, pin 12, and pin 11 of chip U2, and the pin 5 of connector J1 is grounded;

[0020] The pin 20 of chip U2 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the pin 10 of chip U2, and the other end of capacitor C1 is grounded together with the pin 10 of chip U2.

[0021] According to the above technical solution, the level conversion module includes chip U7, capacitor C14, capacitor C16, capacitor C18, capacitor C20, and capacitor C22. Among them, the pin 2 of chip U7 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the pin 4 of chip U7; the pin 5 of chip U7 is connected to one end of capacitor C22, and the other end of capacitor C22 is connected to the pin 6 of chip U7;

[0022] The pin 19 of chip U7 is connected to one end of capacitor C14, the pin 3 of chip U7 is connected to one end of capacitor C18, and the pin 7 of chip U7 is connected to one end of capacitor C20; the other ends of capacitor C14, capacitor C18, and capacitor C20 are all grounded; the pin 14 of chip U7 is connected to the pin 20.

[0023] Compared with the prior art, the present utility model has the following beneficial effects:

[0024] In the present utility model, through a dual-antenna system, higher positioning accuracy and directivity can be provided. The signals received by different antennas can determine the position and movement direction of the target through phase difference or time difference. The receiver module is responsible for receiving the signals from the antennas and performing preliminary data processing and demodulation. The chip module further processes the received signals to extract positioning information. The function of the level conversion module is to convert the received TTL signals into RS-232 standard signals, so as to better communicate with devices such as computers and ensure the compatibility and stability of data transmission. The buffer module is used to temporarily store and output the positioning information obtained by the receiver module, facilitating subsequent data analysis and use. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 It is a schematic diagram of the overall structure of the system of the present utility model;

[0026] Figure 2 It is one of the schematic diagrams of the power supply module of the present utility model;

[0027] Figure 3 It is another schematic diagram of the power supply module of the present utility model;

[0028] Figure 4 It is a schematic diagram of the circuit of the first receiver module of the present utility model;

[0029] Figure 5 It is a schematic diagram of the circuit of the second receiver module of the present utility model;

[0030] Figure 6 It is a schematic diagram of the circuit of the buffer module of the present utility model;

[0031] Figure 7 It is a schematic diagram of the circuit of the level conversion module of the present utility model. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0032] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present utility model.

[0033] Embodiment 1

[0034] As Figure 1As shown in the figure, the dual-antenna positioning, orientation, and timekeeping system includes a computer, antennas, a receiver module, a chip module, a level conversion module, and a buffer module. One end of the chip module is respectively connected to the receiver module, the level conversion module, and the buffer module. The level conversion module is used to convert the TTL level in the receiver module into a 232 level. The buffer module is used to output the positioning information obtained by the receiver module.

[0035] The receiver module is connected to the antennas. The other end of the chip module is connected to the computer, and the computer is used to receive the positioning and orientation data.

[0036] As Figure 7 shown in the figure, the level conversion module includes chip U7, capacitor C14, capacitor C16, capacitor C18, capacitor C20, and capacitor C22. Among them, the 2nd pin of chip U7 is connected to one end of capacitor C16, and the other end of capacitor C16 is connected to the 4th pin of chip U7. The 5th pin of chip U7 is connected to one end of capacitor C22, and the other end of capacitor C22 is connected to the 6th pin of chip U7.

[0037] The 19th pin of chip U7 is connected to one end of capacitor C14, the 3rd pin of chip U7 is connected to one end of capacitor C18, and the 7th pin of chip U7 is connected to one end of capacitor C20. The other ends of capacitor C14, capacitor C18, and capacitor C20 are all grounded. The 14th pin of chip U7 is connected to the 20th pin.

[0038] In the present utility model, through the dual-antenna system, higher positioning accuracy and directivity can be provided. Signals received by different antennas can determine the position and movement direction of the target through phase difference or time difference. The receiver module is responsible for receiving signals from the antennas and performing preliminary data processing and demodulation. The chip module further processes the received signals and extracts positioning information. The function of the level conversion module is to convert the received TTL signal into an RS-232 standard signal, so as to communicate better with devices such as computers and ensure the compatibility and stability of data transmission. The buffer module is used to temporarily store and output the positioning information obtained by the receiver module, facilitating subsequent data analysis and use. It can ensure that the system can effectively process and store continuous data when received.

[0039] In the present utility model, through efficient data acquisition, processing, and transmission, precise positioning and orientation control are achieved, and it is widely applied in fields such as navigation, traffic monitoring, and geographic information systems.

[0040] Embodiment 2

[0041] This embodiment is a further refinement of Embodiment 1.

[0042] As Figure 2As shown in the figure, it further includes a power supply module, which is respectively connected to the receiving module, the chip module, the level conversion module, and the buffer module, and is used to supply power to the receiving module, the chip module, the level conversion module, and the buffer module.

[0043] The power supply module includes chip U5, resistor R8, capacitors C4, C5, C6, C7, C8, inductor L1, fuse F1, and diode T1. One end of the fuse F1 is respectively connected to the power supply and one end of the diode T1, and the other end of the fuse F1 is connected to the inductor L1, one end of the capacitor C4, and the 2nd pin of the chip U5.

[0044] One end of the inductor L1 is grounded, and the other end of the inductor L1 is respectively connected to the other end of the capacitor C4 and the 1st pin of the chip U5.

[0045] The 4th pin of the chip U5 is connected to one end of the resistor R8, the other end of the resistor R8 is grounded, the 7th pin of the chip U5 is grounded, the 6th pin of the chip U5 is respectively connected to the 5th pin of the chip U5, and one ends of the capacitors C5, C6, C7, and C8, and the other ends of the capacitors C5, C6, C7, and C8 are all grounded.

[0046] As Figure 3 shown in the figure, the power supply module further includes chip U6, resistor R12, capacitors C9, C10, C11, C12, and C13. One end of the 1st pin of the chip U6 is connected to one end of the capacitor C9, and the other end of the capacitor C9 is connected to the 2nd pin of the chip U6.

[0047] The 7th pin of the chip U6 is grounded, the 6th pin of the chip U6 is respectively connected to the 5th pin of the chip U6, and one ends of the capacitors C10, C11, C12, and C13, and the other ends of the capacitors C10, C11, C12, and C13 are all grounded. The 4th pin of the chip U6 is connected to one end of the resistor R12, and the other end of the resistor R12 is grounded.

[0048] The antenna includes a first antenna and a second antenna; the receiver module includes a first receiver module and a second receiver module. Among them, the first receiver module is connected to the first antenna, and the second receiver module is connected to the second antenna.

[0049] As Figure 4 shown in the figure, the first receiver module includes chip U3, resistor R6, and capacitor C2. The 1st pin of the chip U3 is connected to the power supply, the 5th pin of the chip U3 is respectively connected to one end of the resistor R6 and the capacitor C2, the other end of the resistor R6 is connected to the power supply, and the other end of the capacitor C2 is grounded. The 2nd pin of the chip U3 is connected to the power supply.

[0050] As Figure 5 shown, the second receiver module includes chip U4, resistor R7, and capacitor C3. Among them, the 1st pin of chip U4 is connected to the power supply, the 5th pin of chip U4 is respectively connected to one end of resistor R7 and capacitor C3, the other end of resistor R7 is connected to the power supply, and the other end of capacitor C3 is grounded; the 2nd pin of chip U4 is connected to the power supply.

[0051] As Figure 6 shown, the buffer module includes chip U2, capacitor C1, resistors R1, R2, R3, R4, R5, and connector J1. Among them, the 1st pin of chip U2 is connected to one end of resistor R5, and the other end of resistor R5 is connected to the power supply; the 1st pin of connector J1 is connected to one end of resistor R1, and the other end of resistor R1 is connected to the power supply; the 2nd, 3rd, and 4th pins of connector J1 are respectively connected to one end of resistors R2, R3, and R4, and the other ends of resistors R2, R3, and R4 are respectively connected to the 13th, 12th, and 11th pins of chip U2, and the 5th pin of connector J1 is grounded;

[0052] The 20th pin of chip U2 is connected to one end of capacitor C1, and the other end of capacitor C1 is connected to the 10th pin of chip U2, and the other end of capacitor C1 is grounded to the 10th pin of chip U2.

[0053] The working principle of the present utility model is as follows: When in use, the chip module communicates with the first receiver module and the second receiver module respectively to obtain the GPS / BD2 information received by the first receiver module and the second receiver module. Among them, the positioning information obtained by the first receiver module and the second receiver module is output through the buffer module, and other information is directly output to the computer through the serial port at 422 level.

[0054] The power supply voltage of the input system is 15 - 30VDC. One path passes through chip U5 to output 5V voltage to supply power to the chip module and the two receiver modules, and the other path passes through chip U5 to output 3.3V voltage to supply power to the level conversion module and the buffer module;

[0055] The TTL levels of the first receiver module and the second receiver module are converted into 232 levels through the level conversion module to communicate with the 232 level of the serial port of the chip module. The TTL levels of the first receiver module and the second receiver module are converted into 232 levels through the level conversion module for testing purposes.

[0056] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or further includes elements inherent to such process, method, article or device.

[0057] Finally, it should be noted that the above are only preferred embodiments of the present utility model and are not used to limit the present utility model. Although the present utility model has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or perform equivalent replacements for some of the technical features. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included within the protection scope of the present utility model.

Claims

1. Dual-antenna positioning, orientation and timing system, characterized by: It includes a computer, an antenna, a receiver module, a chip module, a level conversion module and a buffer module; one end of the chip module is connected to the receiver module, the level conversion module and the buffer module respectively, the level conversion module is used to convert the TTL level in the receiver module to the 232 level; the buffer module is used to output the positioning information obtained by the receiver module; the receiver module is connected to the antenna; the other end of the chip module is connected to the computer, and the computer is used to receive the positioning and orientation data; The level conversion module includes a chip U7, a capacitor C14, a capacitor C16, a capacitor C18, a capacitor C20 and a capacitor C22; wherein, pin 2 of the chip U7 is connected to one end of the capacitor C16, and the other end of the capacitor C16 is connected to pin 4 of the chip U7; pin 5 of the chip U7 is connected to one end of the capacitor C22, and the other end of the capacitor C22 is connected to pin 6 of the chip U7; Pin 19 of chip U7 is connected to one end of capacitor C14, pin 3 of chip U7 is connected to one end of capacitor C18, and pin 7 of chip U7 is connected to one end of capacitor C20; the other ends of capacitors C14, C18 and C20 are all grounded; pin 14 of chip U7 is connected to pin 20.

2. The dual-antenna positioning, orientation and timing system according to claim 1, characterized in that: It also includes a power module, which is respectively connected to the receiving module, the chip module, the level conversion module and the buffer module, and is used to supply power to the receiving module, the chip module, the level conversion module and the buffer module.

3. The dual-antenna positioning, orientation and timing system according to claim 2, characterized in that: The power module includes a chip U5, a resistor R8, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C8, an inductor L1, a fuse F1 and a diode T1; wherein one end of the fuse F1 is connected to the power supply and one end of the diode T1 respectively, and the other end of the fuse F1 is connected to the inductor L1, one end of the capacitor C4 and pin 2 of the chip U5; One end of the inductor L1 is grounded, and the other end of the inductor L1 is connected to the other end of the capacitor C4 and the pin 1 of the chip U5 respectively; Pin 4 of chip U5 is connected to one end of resistor R8, the other end of resistor R8 is grounded, pin 7 of chip U5 is grounded, pin 6 of chip U5 is respectively connected to pin 5 of chip U5, capacitor C5, capacitor C6, capacitor C7 and one end of capacitor C8, and the other ends of capacitor C5, capacitor C6, capacitor C7 and capacitor C8 are all grounded.

4. The dual-antenna positioning, orientation and timing system according to claim 3, characterized in that: The power module also includes a chip U6, a resistor R12, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C12 and a capacitor C13; wherein pin 1 of the chip U6 is connected to one end of the capacitor C9, and the other end of the capacitor C9 is connected to pin 2 of the chip U6; Pin No. 7 of chip U6 is grounded, pin No. 6 of chip U6 is respectively connected to pin No. 5 of chip U6, capacitor C10, capacitor C11, capacitor C12 and one end of capacitor C13, and the other ends of capacitor C10, capacitor C11, capacitor C12 and capacitor C13 are all grounded; pin No. 4 of chip U6 is connected to one end of resistor R12, and the other end of resistor R12 is grounded.

5. The dual-antenna positioning, orientation and timing system according to claim 4, characterized in that: The antenna includes a first antenna and a second antenna; the receiver module includes a first receiver module and a second receiver module; wherein the first receiver module is connected to the first antenna, and the second receiver module is connected to the second antenna.

6. The dual-antenna positioning, orientation and timing system according to claim 5, characterized in that: The first receiver module includes a chip U3, a resistor R6 and a capacitor C2; wherein the pin 1 of the chip U3 is connected to the power supply, the pin 5 of the chip U3 is connected to the resistor R6 and one end of the capacitor C2 respectively, the other end of the resistor R6 is connected to the power supply, and the other end of the capacitor C2 is grounded; the pin 2 of the chip U3 is connected to the power supply; The second receiver module includes a chip U4, a resistor R7 and a capacitor C3; wherein, pin 1 of the chip U4 is connected to a power supply, pin 5 of the chip U4 is connected to one end of the resistor R7 and the capacitor C3 respectively, the other end of the resistor R7 is connected to a power supply, and the other end of the capacitor C3 is grounded; pin 2 of the chip U4 is connected to a power supply.

7. The dual-antenna positioning, orientation and timing system according to claim 6, characterized in that: The buffer module includes a chip U2, a capacitor C1, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a connector J1; wherein, pin 1 of the chip U2 is connected to one end of the resistor R5, and the other end of the resistor R5 is connected to a power source; pin 1 of the connector J1 is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to a power source; pin 2, pin 3 and pin 4 of the connector J1 are respectively connected to one end of the resistor R2, resistor R3 and resistor R4, and the other ends of the resistor R2, resistor R3 and resistor R4 are respectively connected to pin 13, pin 12 and pin 11 of the chip U2, and pin 5 of the connector J1 is grounded; Pin No. 20 of the chip U2 is connected to one end of the capacitor C1, and the other end of the capacitor C1 is connected to pin No. 10 of the chip U2. The other end of the capacitor C1 and pin No. 10 of the chip U2 are both grounded.

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