Display panel circuit supporting multi-signal input

Abstract

The utility model relates to a display panel circuit supporting multi-signal input, which comprises a main control chip, a power supply module, a VGA input module, a DVI input module, a DP input module, an LVDS screen signal output module and an audio power amplifier module, and is characterized in that the VGA input module, the DVI input module and the DP input module are respectively connected with the main control chip and transmit image signals; the main control chip outputs an image signal to the LVDS screen signal output module, the main control chip outputs an audio signal to the audio power amplifier module, the output end of the audio power amplifier module is connected with the loudspeaker, and the power supply module outputs a power supply signal to the main control chip. The digital display device supports VGA interface, DVI interface and DP interface signal input, is high in compatibility and convenient to carry, and facilitates the display field of a large number of medical devices.

Description

Technical Field

[0001] The utility model relates to the technical field of electronic circuits, in particular to a display board circuit supporting multi-signal input. Background Art

[0002] The monitor controller combines an analog RGB input interface, a HDMI1.4a digital input interface compatible with HDCP1.4, and a DP1.2 digital input interface compatible with HDCP1.4. The embedded single-chip microcomputer is based on the industrial standard 8051 core and is externally connected with a serial flash memory. It supports 4-channel digital input, with the speed of each channel reaching 1.6 Gbps and 2.7 Gbps, supports 10-bit Gamma programming, has a maximum resolution of 1920*1200P, and a maximum refresh rate of 75HZ. It is mainly used in industries such as the medical industry, including medical device equipment, industrial control computers for human-computer interaction, etc.; it can also be applied to other industries, such as monitors, all-in-ones, and embedded application devices.

[0003] Since traditional display products are mostly used in home monitors, office monitors, or commercial monitors, most of them can only input signals through one type of interface. This has limited the medical industry and cannot meet the current medical industry market. Summary of the Utility Model

[0004] The utility model provides a display board circuit supporting multi-signal input, aiming to solve the problem that existing monitors can only receive signals of one interface type.

[0005] The utility model provides a display board circuit supporting multi-signal input, including a main control chip, a power supply module, a VGA input module, a DVI input module, a DP input module, an LVDS screen signal output module, and an audio power amplifier module. The VGA input module, DVI input module, and DP input module are respectively connected to the main control chip and transmit image signals. The main control chip outputs image signals to the LVDS screen signal output module. The main control chip outputs audio signals to the audio power amplifier module. The output end of the audio power amplifier module is connected to a speaker. The power supply module outputs power signals to the main control chip.

[0006] As a further improvement of the present utility model, the power supply module includes a power input interface DC1, a power input interface J8, a power supply chip U1, a power supply chip U2, and a power supply chip U3. The power input interface DC1 and the power input interface J8 are respectively connected to a DC 12V voltage. The power input interface DC1 is connected to a capacitor C3. The pin 1 of the power input interface DC1 and the pin 1 of the power input interface J8 are both connected to one end of a fuse F1. A fuse F2 is connected in parallel with the fuse F1. The other end of the fuse F1 outputs a 12V voltage to the power supply chip U1, the power supply chip U2, and the power supply chip U3. The power supply chip U1 outputs a 5V voltage, the power supply chip U2 outputs a 3.3V voltage, and the power supply chip U3 outputs a 0.9V voltage.

[0007] As a further improvement of the present utility model, the power supply module further includes a backlight power control interface J4. The pins 5 and 6 of the backlight power control interface J4 are connected to a 12V voltage. The pin 3 of the backlight power control interface J4 is connected to the collector of a triode Q1. The base of the triode Q1 is connected to the pin 64 of the main control chip. The pin 4 of the backlight power control interface J4 is connected to the pin 65 of the main control chip.

[0008] As a further improvement of the present utility model, the VGA input module includes a VGA interface. The DDCSCL pin of the VGA interface is connected to the pin 100 of the main control chip. The DDCSDA pin of the VGA interface is connected to the pin 101 of the main control chip. The VGA_B+ pin of the VGA interface is connected to the pin 27 of the main control chip. The VGA_B- pin of the VGA interface is connected to the pin 26 of the main control chip. The VGA_G+ pin of the VGA interface is connected to the pin 29 of the main control chip. The VGA_G- pin of the VGA interface is connected to the pin 28 of the main control chip. The VGA_R+ pin of the VGA interface is connected to the pin 32 of the main control chip. The VGA_R- pin of the VGA interface is connected to the pin 31 of the main control chip.

[0009] As a further improvement of the present utility model, the DVI input module includes a DVI interface, an anti-interference chip UX1 and an anti-interference chip UX2. The RX2- pin of the DVI interface is connected to the NC1 pin of the anti-interference chip UX1. The RX2+ pin of the DVI interface is connected to the NC2 pin of the anti-interference chip UX1. The RX1- pin of the DVI interface is connected to the NC3 pin of the anti-interference chip UX2. The RX1+ pin of the DVI interface is connected to the NC4 pin of the anti-interference chip UX2. The RX0- pin of the DVI interface is connected to the NC1 pin of the anti-interference chip UX2. The RX0+ pin of the DVI interface is connected to the NC2 pin of the anti-interference chip UX2. The RXC+ pin of the DVI interface is connected to the NC3 pin of the anti-interference chip UX1. The RXC- pin of the DVI interface is connected to the NC4 pin of the anti-interference chip UX1. The LIN4 pin of the anti-interference chip UX1 is connected to the 9th pin of the main control chip. The LIN3 pin of the anti-interference chip UX1 is connected to the 8th pin of the main control chip. The LIN2 pin of the anti-interference chip UX1 is connected to the 7th pin of the main control chip. The LIN1 pin of the anti-interference chip UX1 is connected to the 6th pin of the main control chip. The LIN4 pin of the anti-interference chip UX2 is connected to the 5th pin of the main control chip. The LIN3 pin of the anti-interference chip UX2 is connected to the 4th pin of the main control chip. The LIN2 pin of the anti-interference chip UX2 is connected to the 2nd pin of the main control chip. The LIN1 pin of the anti-interference chip UX2 is connected to the 1st pin of the main control chip.

[0010] As a further improvement of the present utility model, the DP input module includes a DP input interface, anti-interference chips UX3, UX4, and UX5. The ML_LANE3N pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX3. The ML_LANE3P pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX3. The ML_LANE2N pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX3. The ML_LANE2P pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX3. The ML_LANE1N pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX4. The ML_LANE1P pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX4. The ML_LANE0N pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX4. The ML_LANE0P pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX4. The AUX_CHP pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX5. The GND_10 pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX5. The AUX_CHN pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX5. The HOT_PLUG pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX5. The LIN4 pin of the anti-interference chip UX3 is connected to the 19th pin of the main control chip. The LIN3 pin of the anti-interference chip UX3 is connected to the 18th pin of the main control chip. The LIN2 pin of the anti-interference chip UX3 is connected to the 17th pin of the main control chip. The LIN1 pin of the anti-interference chip UX3 is connected to the 16th pin of the main control chip. The LIN4 pin of the anti-interference chip UX4 is connected to the 15th pin of the main control chip. The LIN3 pin of the anti-interference chip UX4 is connected to the 14th pin of the main control chip. The LIN2 pin of the anti-interference chip UX4 is connected to the 12th pin of the main control chip. The LIN1 pin of the anti-interference chip UX4 is connected to the 11th pin of the main control chip.

[0011] As a further improvement of the present utility model, the LVDS screen signal output module includes an LVDS screen signal output interface JP6. The 1st, 2nd, and 3rd pins of the LVDS screen signal output interface JP6 are connected to the drain of the field effect transistor Q6. The source of the field effect transistor Q6 is respectively connected to 12V, 5V, and 3.3V voltages. The gate of the field effect transistor Q6 is connected to the collector of the triode Q3. The base of the triode Q3 is connected to the 90th pin of the main control chip. The 88th pin of the main control chip is connected to the 7th pin of the LVDS screen signal output interface JP6. The 86th pin of the main control chip is connected to the 9th pin of the LVDS screen signal output interface JP6. The 84th pin of the main control chip is connected to the 11th pin of the LVDS screen signal output interface JP6. The 82nd pin of the main control chip is connected to the 15th and 27th pins of the LVDS screen signal output interface JP6. The 72nd pin of the main control chip is connected to the 21st pin of the LVDS screen signal output interface JP6. The 74th pin of the main control chip is connected to the 19th pin of the LVDS screen signal output interface JP6. The 70th pin of the main control chip is connected to the 23rd pin of the LVDS screen signal output interface JP6. The 85th pin of the main control chip is connected to the 10th pin of the LVDS screen signal output interface JP6. The 83rd pin of the main control chip is connected to the 12th pin of the LVDS screen signal output interface JP6. The 81st pin of the main control chip is connected to the 16th and 28th pins of the LVDS screen signal output interface JP6. The 79th pin of the main control chip is connected to the 18th pin of the LVDS screen signal output interface JP6. The 73rd pin of the main control chip is connected to the 20th pin of the LVDS screen signal output interface JP6. The 71st pin of the main control chip is connected to the 22nd pin of the LVDS screen signal output interface JP6. The 69th pin of the main control chip is connected to the 24th pin of the LVDS screen signal output interface JP6. The 67th pin of the main control chip is connected to the 30th pin of the LVDS screen signal output interface JP6.

[0012] As a further improvement of the present utility model, the audio power amplifier module includes an audio power amplifier chip U4 and an audio output interface J6. The 6th pin of the audio power amplifier chip U4 is connected to the 58th pin of the main control chip. The 3rd pin of the audio power amplifier chip U4 is connected to the 59th pin of the main control chip. The 7th pin of the audio power amplifier chip U4 is connected to the collector of the triode Q4. The base of the triode Q4 is connected to the 34th pin of the main control chip. The 2nd pin of the audio power amplifier chip U4 is connected to the collector of the triode Q5. The base of the triode Q5 is connected to the 63rd pin of the main control chip. The 11th pin of the audio power amplifier chip U4 is connected to the 1st pin of the audio output interface J6. The 9th pin of the audio power amplifier chip U4 is connected to the 2nd pin of the audio output interface J6. The 14th pin of the audio power amplifier chip U4 is connected to the 4th pin of the audio output interface J6. The 16th pin of the audio power amplifier chip U4 is connected to the 3rd pin of the audio output interface J6.

[0013] As a further improvement of the present utility model, it further includes a Flash chip U6. The 3rd pin of the Flash chip U6 is connected to the 96th pin of the main control chip.

[0014] As a further improvement of the present utility model, the model of the main control chip is RTD2525BR.

[0015] The beneficial effects of the present utility model are: it supports the input of VGA interface, DVI interface, and DP interface signals, has strong compatibility, is convenient to carry, and facilitates the display field of a large number of medical devices. Description of the Drawings

[0016] Figure 1 It is a relationship diagram of each module in the circuit of the present utility model;

[0017] Figure 2 It is a specific circuit connection diagram of the main control chip of the present utility model;

[0018] Figure 3 It is a specific circuit connection diagram of the power supply module of the present utility model;

[0019] Figure 4 It is a specific circuit connection diagram of the VGA input module of the present utility model;

[0020] Figure 5 It is a specific circuit connection diagram of the DVI input module of the present utility model;

[0021] Figure 6 It is a specific circuit connection diagram of the DP input module of the present utility model;

[0022] Figure 7 It is a specific circuit connection diagram of the LVDS screen signal output module of the present utility model;

[0023] Figure 8 is the specific circuit connection diagram of the Flash chip of the present utility model;

[0024] Figure 9 is the specific circuit connection diagram of the audio power amplifier module of the present utility model;

[0025] Figure 10 is the circuit connection diagram of the external expansion board of the present utility model. Specific embodiments

[0026] In order to make the objectives, technical solutions and advantages of the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments.

[0027] As Figures 1-10 shown, the present utility model provides a display board circuit supporting multi-signal input, including a main control chip, a power supply module, a VGA input module, a DVI input module, a DP input module, an LVDS screen signal output module and an audio power amplifier module. The VGA input module, the DVI input module and the DP input module are respectively connected to the main control chip and transmit image signals. The main control chip outputs image signals to the LVDS screen signal output module. The main control chip outputs audio signals to the audio power amplifier module. The output end of the audio power amplifier module is connected to a speaker. The power supply module outputs power supply signals to the main control chip.

[0028] As an embodiment of the present utility model, the power supply module includes a power input interface DC1, a power input interface J8, a power chip U1, a power chip U2 and a power chip U3. The power input interface DC1 and the power input interface J8 are respectively connected to a DC 12V voltage. The power input interface DC1 is connected to a capacitor C3. The 1 pin of the power input interface DC1 and the 1 pin of the power input interface J8 are both connected to one end of a fuse F1. A fuse F2 is connected in parallel with the fuse F1. The other end of the fuse F1 outputs 12V voltage to the power chip U1, the power chip U2 and the power chip U3. The power chip U1 outputs 5V voltage. The power chip U2 outputs 3.3V voltage. The power chip U3 outputs 0.9V voltage.

[0029] As another embodiment of the present utility model, the power supply module further includes a backlight power control interface J4. The 5th and 6th pins of the backlight power control interface J4 are connected to a 12V voltage. The 3rd pin of the backlight power control interface J4 is connected to the collector of a triode Q1. The base of the triode Q1 is connected to the 64th pin of the main control chip. The 4th pin of the backlight power control interface J4 is connected to the 65th pin of the main control chip.

[0030] As another embodiment of the present utility model, the VGA input module includes a VGA interface. The DDCSCL pin of the VGA interface is connected to pin 100 of the main control chip. The DDCSDA pin of the VGA interface is connected to pin 101 of the main control chip. The VGA_B+ pin of the VGA interface is connected to pin 27 of the main control chip. The VGA_B- pin of the VGA interface is connected to pin 26 of the main control chip. The VGA_G+ pin of the VGA interface is connected to pin 29 of the main control chip. The VGA_G- pin of the VGA interface is connected to pin 28 of the main control chip. The VGA_R+ pin of the VGA interface is connected to pin 32 of the main control chip. The VGA_R- pin of the VGA interface is connected to pin 31 of the main control chip.

[0031] As another embodiment of the present utility model, the DVI input module includes a DVI interface, an anti-interference chip UX1 and an anti-interference chip UX2. The RX2- pin of the DVI interface is connected to the NC1 pin of the anti-interference chip UX1. The RX2+ pin of the DVI interface is connected to the NC2 pin of the anti-interference chip UX1. The RX1- pin of the DVI interface is connected to the NC3 pin of the anti-interference chip UX2. The RX1+ pin of the DVI interface is connected to the NC4 pin of the anti-interference chip UX2. The RX0- pin of the DVI interface is connected to the NC1 pin of the anti-interference chip UX2. The RX0+ pin of the DVI interface is connected to the NC2 pin of the anti-interference chip UX2. The RXC+ pin of the DVI interface is connected to the NC3 pin of the anti-interference chip UX1. The RXC- pin of the DVI interface is connected to the NC4 pin of the anti-interference chip UX1. The LIN4 pin of the anti-interference chip UX1 is connected to pin 9 of the main control chip. The LIN3 pin of the anti-interference chip UX1 is connected to pin 8 of the main control chip. The LIN2 pin of the anti-interference chip UX1 is connected to pin 7 of the main control chip. The LIN1 pin of the anti-interference chip UX1 is connected to pin 6 of the main control chip. The LIN4 pin of the anti-interference chip UX2 is connected to pin 5 of the main control chip. The LIN3 pin of the anti-interference chip UX2 is connected to pin 4 of the main control chip. The LIN2 pin of the anti-interference chip UX2 is connected to pin 2 of the main control chip. The LIN1 pin of the anti-interference chip UX2 is connected to pin 1 of the main control chip.

[0032] As another embodiment of the present utility model, the DP input module includes a DP input interface, anti-interference chips UX3, UX4, and UX5. The ML_LANE3N pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX3, the ML_LANE3P pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX3, the ML_LANE2N pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX3, the ML_LANE2P pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX3, the ML_LANE1N pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX4, the ML_LANE1P pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX4, the ML_LANE0N pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX4, the ML_LANE0P pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX4, the AUX_CHP pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX5, the GND_10 pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX5, the AUX_CHN pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX5, the HOT_PLUG pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX5. The LIN4 pin of the anti-interference chip UX3 is connected to the 19th pin of the main control chip, the LIN3 pin of the anti-interference chip UX3 is connected to the 18th pin of the main control chip, the LIN2 pin of the anti-interference chip UX3 is connected to the 17th pin of the main control chip, the LIN1 pin of the anti-interference chip UX3 is connected to the 16th pin of the main control chip, the LIN4 pin of the anti-interference chip UX4 is connected to the 15th pin of the main control chip, the LIN3 pin of the anti-interference chip UX4 is connected to the 14th pin of the main control chip, the LIN2 pin of the anti-interference chip UX4 is connected to the 12th pin of the main control chip, and the LIN1 pin of the anti-interference chip UX4 is connected to the 11th pin of the main control chip.

[0033] As another embodiment of the present utility model, the LVDS screen signal output module includes an LVDS screen signal output interface JP6. The 1st, 2nd, and 3rd pins of the LVDS screen signal output interface JP6 are connected to the drain of the field effect transistor Q6. The source of the field effect transistor Q6 is respectively connected to 12V, 5V, and 3.3V voltages. The gate of the field effect transistor Q6 is connected to the collector of the triode Q3. The base of the triode Q3 is connected to the 90th pin of the main control chip. The 88th pin of the main control chip is connected to the 7th pin of the LVDS screen signal output interface JP6. The 86th pin of the main control chip is connected to the 9th pin of the LVDS screen signal output interface JP6. The 84th pin of the main control chip is connected to the 11th pin of the LVDS screen signal output interface JP6. The 82nd pin of the main control chip is connected to the 15th and 27th pins of the LVDS screen signal output interface JP6. The 72nd pin of the main control chip is connected to the 21st pin of the LVDS screen signal output interface JP6. The 74th pin of the main control chip is connected to the 19th pin of the LVDS screen signal output interface JP6. The 70th pin of the main control chip is connected to the 23rd pin of the LVDS screen signal output interface JP6. The 85th pin of the main control chip is connected to the 10th pin of the LVDS screen signal output interface JP6. The 83rd pin of the main control chip is connected to the 12th pin of the LVDS screen signal output interface JP6. The 81st pin of the main control chip is connected to the 16th and 28th pins of the LVDS screen signal output interface JP6. The 79th pin of the main control chip is connected to the 18th pin of the LVDS screen signal output interface JP6. The 73rd pin of the main control chip is connected to the 20th pin of the LVDS screen signal output interface JP6. The 71st pin of the main control chip is connected to the 22nd pin of the LVDS screen signal output interface JP6. The 69th pin of the main control chip is connected to the 24th pin of the LVDS screen signal output interface JP6. The 67th pin of the main control chip is connected to the 30th pin of the LVDS screen signal output interface JP6.

[0034] As another embodiment of the present utility model, the audio power amplifier module includes an audio power amplifier chip U4 and an audio output interface J6. The 6th pin of the audio power amplifier chip U4 is connected to the 58th pin of the main control chip. The 3rd pin of the audio power amplifier chip U4 is connected to the 59th pin of the main control chip. The 7th pin of the audio power amplifier chip U4 is connected to the collector of a triode Q4. The base of the triode Q4 is connected to the 34th pin of the main control chip. The 2nd pin of the audio power amplifier chip U4 is connected to the collector of a triode Q5. The base of the triode Q5 is connected to the 63rd pin of the main control chip. The 11th pin of the audio power amplifier chip U4 is connected to the 1st pin of the audio output interface J6. The 9th pin of the audio power amplifier chip U4 is connected to the 2nd pin of the audio output interface J6. The 14th pin of the audio power amplifier chip U4 is connected to the 4th pin of the audio output interface J6. The 16th pin of the audio power amplifier chip U4 is connected to the 3rd pin of the audio output interface J6.

[0035] As another embodiment of the present utility model, it further includes a Flash chip U6. The 3rd pin of the Flash chip U6 is connected to the 96th pin of the main control chip.

[0036] As another embodiment of the present utility model, the model of the main control chip is RTD2525BR.

[0037] The present utility model provides a display board circuit supporting multi-signal input. It adopts an RTD2525BR chip, is configured with HDMI interface, DVI interface, and DP interface. It has diverse displays, supports LVDS / EDP display screens, and supports display screens of various sizes such as 7 inches, 10.1 inches, 21 inches, etc. The setting parameters are multifunctional. It is designed with an encoder knob switch, configured with 6 buttons, and supports multi-language settings (Chinese, English, German, Japanese, etc.), and different function parameters can be set. The product is green and environmentally friendly, with ultra-low power consumption less than 0.3W when in standby and sleep states, making the display field in the medical industry more convenient.

[0038] Appendix Figure 3This is the power supply part. The power input interface DC1 and the power input interface J8 are 12V power input interfaces. The power passes through the filter capacitor C3 and then flows to the fuse F1, and then through the filter capacitors C2 and C78 to provide a stable 12V power supply, which then flows to the power chips U1, U2, U3 and the backlight power control interface J4. The power chip U1 is a voltage regulator chip that outputs 5V, and after filtering through C4, C6, and C7, it provides a stable power supply to the audio power amplifier chip U4 and the backlight power control interface J4. The power chip U2 is a voltage regulator chip that outputs 3.3V, and after filtering through C9, C11, and C12, it provides a stable power supply to the main control chip U10, the LVDS screen signal output interface JP6, the Flash chip U6, and the data storage chip U5. The power chip U3 is a voltage regulator chip that outputs 0.9V, and after filtering through C17, C19, and C20, it provides a stable power supply to the main control chip U10.

[0039] The main control chip U10 provides the BL-ADJ control signal to flow to the triode Q1, and after being amplified by the switch of the triode Q1, it flows to the backlight power control interface J4. The main control chip U10 provides the BL_EN data control signal to the backlight power control interface J4. The 12V voltage passes through L3, C13, and C14 for filtering and then is supplied to the backlight power control interface J4.

[0040] Appendix Figure 7 This is the circuit part of the LVDS screen. The main control chip U10 converts the received digital image signal into the corresponding analog signal for the LVDS screen and transmits it to the screen through the cable. The main control chip U10 outputs the screen voltage control signal, which flows to the switching triode Q3. The triode Q3 controls the on and off of the field effect transistor Q2, and the field effect transistor Q2 controls the opening or closing of the screen voltage.

[0041] Appendix Figure 2 This is the circuit part of the main control chip. The main control chip U10 uses the RTD2525BR chip, and is supplied with 3.3V through L13, L15, L17, L20, L14, L22; and 0.9V through L16, L19. The two groups of voltages of 3.3V and 0.9V are simultaneously supplied to the corresponding pins of the data storage chip U5, the Flash chip U6, and the RTD2525BR. When switching, the RTD2525BR communicates with the data storage chip U5 through the I2C communication protocol to read data information. At the same time, the RTD2525BR communicates with the Flash chip U6 through the SPI communication protocol to read data information. J3 is an external control mechanical button, and the button command provides the corresponding level signal input to the main control chip U10 through RP3 and RP2. The main control chip U10 performs internal decoding and then outputs a control signal by the main control chip U10 to achieve the function.

[0042] Appendix Figure 10It is the circuit connection diagram for external expansion. This design expands the placement positions of touch sensors on the touch screen. J2 and J14 are connected to external touch sensors.

[0043] Appendix Figure 9 It is the circuit connection diagram for audio output. The power supply chip U1 outputs 5V, which passes through L8 and is filtered by C57 and C58 before being input to the audio power amplifier chip U4; the main control chip U10 outputs an audio analog signal, which flows to R75 and R76, then to the coupling capacitors C55 and C56 and then to the audio power amplifier chip U4, and is amplified and output to the audio output interface J6 through the audio power amplifier chip U4; the main control chip U10 outputs a control signal that flows to the triode Q4, and the sound volume of the power amplifier is controlled through the triode Q4; the main control chip U10 outputs a control signal that flows to the triode Q5, and the operation and shutdown (MUTE) of the power amplifier are controlled through the triode Q5.

[0044] Appendix Figure 4 It is the specific circuit connection diagram of the VGA input module. The external device outputs a VGA analog image signal, which is connected to the VGA through a cable. The VGA analog image signal flows through some coupling capacitors and series impedance resistors to the RTD2525BR main control chip. After the main chip decodes and analyzes it, it outputs an analog image signal, which flows to the LVDS screen signal output interface JP6 and then is transmitted to the LVDS display screen.

[0045] Appendix Figure 5 It is the specific circuit connection diagram of the DVI input module. The external device outputs a DVI digital image signal, which is connected to DVI 1 through a cable. The DVI digital image signal flows through the PCB wire to the RTD2525BR main chip, passes through the anti-interference ESD devices UX1 and UX2, and then to the main chip for decoding and analysis, and then outputs an analog signal, which flows to the LVDS screen signal output interface JP6 and then is transmitted to the LVDS display screen.

[0046] Appendix Figure 6 It is the specific circuit connection diagram of the DP input module. The external device outputs a DP digital image signal, which is connected to DP2 through a cable. The DP digital image signal flows through the PCB wire to the RTD2525BR main chip, passes through the anti-interference ESD devices UX3, UX4, and UX5, and then to the main chip for decoding and analysis, and then outputs an analog signal, which flows to the LVDS screen signal output interface JP6 and then is transmitted to the LVDS display screen.

[0047] The above content is a further detailed description of the present utility model in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present utility model is only limited to these descriptions. For those of ordinary skill in the technical field to which the present utility model belongs, without departing from the concept of the present utility model, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present utility model.

Claims

1. A display panel circuit supporting multiple signal inputs, characterized in that: It includes a main control chip, a power module, a VGA input module, a DVI input module, a DP input module, an LVDS screen signal output module and an audio power amplifier module. The VGA input module, the DVI input module and the DP input module are respectively connected to the main control chip and transmit image signals. The main control chip outputs image signals to the LVDS screen signal output module, the main control chip outputs audio signals to the audio power amplifier module, the output end of the audio power amplifier module is connected to a speaker, the power module outputs a power signal to the main control chip, and the model of the main control chip is RTD2525BR.

2. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: The power module includes a power input interface DC1, a power input interface J8, a power chip U1, a power chip U2 and a power chip U3. The power input interface DC1 and the power input interface J8 are respectively connected to a DC 12V voltage. The power input interface DC1 is connected to a capacitor C3. Pin 1 of the power input interface DC1 and pin 1 of the power input interface J8 are both connected to one end of a fuse F1. Fuse F2 is connected in parallel with fuse F1. The other end of fuse F1 outputs a 12V voltage to the power chip U1, the power chip U2 and the power chip U3. The power chip U1 outputs a 5V voltage, the power chip U2 outputs a 3.3V voltage, and the power chip U3 outputs a 0.9V voltage.

3. The display panel circuit supporting multiple signal inputs according to claim 2, characterized in that: The power module also includes a backlight power control interface J4, pins 5 and 6 of the backlight power control interface J4 are connected to a 12V voltage, pin 3 of the backlight power control interface J4 is connected to the collector of the transistor Q1, the base of the transistor Q1 is connected to pin 64 of the main control chip, and pin 4 of the backlight power control interface J4 is connected to pin 65 of the main control chip.

4. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: The VGA input module includes a VGA interface, a DDCSCL pin of the VGA interface is connected to pin 100 of the main control chip, a DDCSDA pin of the VGA interface is connected to pin 101 of the main control chip, a VGA_B+ pin of the VGA interface is connected to pin 27 of the main control chip, a VGA_B- pin of the VGA interface is connected to pin 26 of the main control chip, a VGA_G+ pin of the VGA interface is connected to pin 29 of the main control chip, a VGA_G- pin of the VGA interface is connected to pin 28 of the main control chip, a VGA_R+ pin of the VGA interface is connected to pin 32 of the main control chip, and a VGA_R- pin of the VGA interface is connected to pin 31 of the main control chip.

5. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: The DVI input module includes a DVI interface, an anti-interference chip UX1 and an anti-interference chip UX2, the RX2- pin of the DVI interface is connected to the NC1 pin of the anti-interference chip UX1, the RX2+ pin of the DVI interface is connected to the NC2 pin of the anti-interference chip UX1, the RX1- pin of the DVI interface is connected to the NC3 pin of the anti-interference chip UX2, the RX1+ pin of the DVI interface is connected to the NC4 pin of the anti-interference chip UX2, the RX0- pin of the DVI interface is connected to the NC1 pin of the anti-interference chip UX2, the RX0+ pin of the DVI interface is connected to the NC2 pin of the anti-interference chip UX2, the RXC+ pin of the DVI interface is connected to the NC3 pin of the anti-interference chip UX1, and the The RXC- pin of the DVI interface is connected to the NC4 pin of the anti-interference chip UX1, the LIN4 pin of the anti-interference chip UX1 is connected to the 9 pin of the main control chip, the LIN3 pin of the anti-interference chip UX1 is connected to the 8 pin of the main control chip, the LIN2 pin of the anti-interference chip UX1 is connected to the 7 pin of the main control chip, the LIN1 pin of the anti-interference chip UX1 is connected to the 6 pin of the main control chip, the LIN4 pin of the anti-interference chip UX2 is connected to the 5 pin of the main control chip, the LIN3 pin of the anti-interference chip UX2 is connected to the 4 pin of the main control chip, the LIN2 pin of the anti-interference chip UX2 is connected to the 2 pin of the main control chip, and the LIN1 pin of the anti-interference chip UX2 is connected to the 1 pin of the main control chip.

6. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: The DP input module includes a DP input interface, an anti-interference chip UX3, an anti-interference chip UX4 and an anti-interference chip UX5, the ML_LANE3N pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX3, the ML_LANE3P pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX3, the ML_LANE2N pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX3, the ML_LANE2P pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX3, the ML_LANE1N pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX4, the ML_LANE1P pin of the DP input interface is connected to the NC3 pin of the anti-interference chip UX4, the ML_LANE0N pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX4, the ML_LANE0P pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX4, and the AUX_CHP pin of the DP input interface is connected to the NC The GND_10 pin of the DP input interface is connected to the NC4 pin of the anti-interference chip UX5, the AUX_CHN pin of the DP input interface is connected to the NC2 pin of the anti-interference chip UX5, the HOT_PLUG pin of the DP input interface is connected to the NC1 pin of the anti-interference chip UX5, the LIN4 pin of the anti-interference chip UX3 is connected to the 19 pin of the main control chip, the LIN3 pin of the anti-interference chip UX3 is connected to the 18 pin of the main control chip, the LIN2 pin of the anti-interference chip UX3 is connected to the 17 pin of the main control chip, the LIN1 pin of the anti-interference chip UX3 is connected to the 16 pin of the main control chip, the LIN4 pin of the anti-interference chip UX4 is connected to the 15 pin of the main control chip, the LIN3 pin of the anti-interference chip UX4 is connected to the 14 pin of the main control chip, the LIN2 pin of the anti-interference chip UX4 is connected to the 12 pin of the main control chip, and the LIN1 pin of the anti-interference chip UX4 is connected to the 11 pin of the main control chip.

7. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: The LVDS screen signal output module includes an LVDS screen signal output interface JP6, wherein the 1, 2, and 3 pins of the LVDS screen signal output interface JP6 are connected to the drain of the field effect tube Q6, the source of the field effect tube Q6 is connected to 12V, 5V, and 3.3V voltages respectively, the gate of the field effect tube Q6 is connected to the collector of the transistor Q3, the base of the transistor Q3 is connected to the 90 pin of the main control chip, the 88 pin of the main control chip is connected to the 7 pin of the LVDS screen signal output interface JP6, the 86 pin of the main control chip is connected to the 9 pin of the LVDS screen signal output interface JP6, the 84 pin of the main control chip is connected to the 11 pin of the LVDS screen signal output interface JP6, the 82 pin of the main control chip is connected to the 15 and 27 pins of the LVDS screen signal output interface JP6, the 72 pin of the main control chip is connected to the 21 pin of the LVDS screen signal output interface JP6, and the 74 pin of the main control chip is connected to the LVDS screen signal The 19th pin of the main control chip is connected to the LVDS screen signal output interface JP6, the 70th pin of the main control chip is connected to the 23rd pin of the LVDS screen signal output interface JP6, the 85th pin of the main control chip is connected to the 10th pin of the LVDS screen signal output interface JP6, the 83rd pin of the main control chip is connected to the 12th pin of the LVDS screen signal output interface JP6, the 81st pin of the main control chip is connected to the 16th and 28th pins of the LVDS screen signal output interface JP6, the 79th pin of the main control chip is connected to the 18th pin of the LVDS screen signal output interface JP6, the 73rd pin of the main control chip is connected to the 20th pin of the LVDS screen signal output interface JP6, the 71st pin of the main control chip is connected to the 22nd pin of the LVDS screen signal output interface JP6, the 69th pin of the main control chip is connected to the 24th pin of the LVDS screen signal output interface JP6, and the 67th pin of the main control chip is connected to the 30th pin of the LVDS screen signal output interface JP6.

8. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: The audio power amplifier module includes an audio power amplifier chip U4 and an audio output interface J6, wherein pin 6 of the audio power amplifier chip U4 is connected to pin 58 of the main control chip, pin 3 of the audio power amplifier chip U4 is connected to pin 59 of the main control chip, pin 7 of the audio power amplifier chip U4 is connected to the collector of the transistor Q4, the base of the transistor Q4 is connected to pin 34 of the main control chip, pin 2 of the audio power amplifier chip U4 is connected to the collector of the transistor Q5, the base of the transistor Q5 is connected to pin 63 of the main control chip, pin 11 of the audio power amplifier chip U4 is connected to pin 1 of the audio output interface J6, pin 9 of the audio power amplifier chip U4 is connected to pin 2 of the audio output interface J6, pin 14 of the audio power amplifier chip U4 is connected to pin 4 of the audio output interface J6, and pin 16 of the audio power amplifier chip U4 is connected to pin 3 of the audio output interface J6.

9. The display panel circuit supporting multiple signal inputs according to claim 1, characterized in that: It also includes a Flash chip U6, and the 3rd pin of the Flash chip U6 is connected to the 96th pin of the main control chip.

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