Solar self-adaptive charging management circuit

Abstract

The utility model discloses a solar energy self-adaptive charging management circuit, which relates to the charging field, and comprises a diode D1, a capacitor C1, an MOS tube MP3, an inductor L1, a resistor R1, a capacitor C2, a battery E1, a photoresistor RG and a chip U1, the positive electrode of the diode D1 is connected with a voltage VIN, the VIN pin of the chip U1, the negative electrode of the diode D1 is connected with one end of the capacitor C1, the S electrode of the MOS tube MP3, and the other end of the capacitor C1 is connected with the other end of the photoresistor RG. The beneficial effects of the utility model are that the voltage on the photoresistor is sampled and transmitted back, so that the sampling voltage under different outdoor illumination conditions is obtained, and the stronger the illumination is, the higher the voltage is, so that the self-adaption function is realized; sampled voltages under different light intensities are utilized to participate in loop control of a charging management system, automatic adjustment of charging current is achieved, and meanwhile a battery can be protected.

Description

Technical Field

[0001] The utility model relates to the field of charging, in particular to a solar adaptive charging management circuit. Background Technique

[0002] A solar charging management system is a system that utilizes solar energy resources to convert light energy into electrical energy and store it for subsequent use. Its output voltage and current are often fixed.

[0003] This causes the existing solar charging management system to have low system efficiency or even unstable system loops under different lighting conditions, which needs to be improved. Content of the Utility Model

[0004] The purpose of the utility model is to provide a solar adaptive charging management circuit to solve the problems raised in the above background technique.

[0005] To achieve the above purpose, the utility model provides the following technical solution:

[0006] A solar adaptive charging management circuit includes a diode D1, a capacitor C1, a MOS transistor MP3, an inductor L1, a resistor R1, a capacitor C2, a battery E1, a photoresistor RG, and a chip U1. The positive electrode of the diode D1 is connected to the voltage VIN and the VIN pin of the chip U1. The negative electrode of the diode D1 is connected to one end of the capacitor C1 and the S pole of the MOS transistor MP3. The other end of the capacitor C1 is grounded. The G pole of the MOS transistor MP3 is connected to the DRV pin of the chip U1. The D pole of the MOS transistor MP3 is connected to one end of the inductor L1. The other end of the inductor L1 is connected to the CS pin of the chip U1 and one end of the resistor R1. The other end of the resistor R1 is connected to one end of the capacitor C2, the BAT pin of the chip U1, and the positive electrode of the battery E1. The other end of the capacitor C2 is grounded. The negative electrode of the battery E1 is grounded. The GND pin of the chip U1 is grounded. The VSR pin of the chip U1 is connected to one end of the photoresistor RG. The other end of the photoresistor RG is grounded. The model of the chip U1 is YL3388.

[0007] As a further scheme of the utility model: The chip U1 internally includes:

[0008] A set current source module for setting a first current source through a reference voltage;

[0009] A mirror current source module for obtaining a second current source through mirroring based on the first current source and obtaining a voltage signal for supplying to an amplification module based on the resistance value of the photoresistor RG;

[0010] An amplification module for amplifying the voltage signal;

[0011] The set current source module is connected to the mirror current source module, and the mirror current source module is connected to the amplification module.

[0012] As a further solution of the present utility model: The set current source module includes an amplifier OP1, a MOS transistor MP1, a MOS transistor MN1, and a resistor R2. The non-inverting input terminal of the amplifier OP1 is connected to a reference voltage, and the inverting input terminal of the amplifier OP1 is connected to the S pole of the MOS transistor MN1 and one end of the resistor R2. The other end of the resistor R2 is grounded. The G pole of the MOS transistor MN1 is connected to the G pole of the amplifier OP1. The D pole of the MOS transistor MN1 is connected to the D pole of the MOS transistor MP1, the G pole of the MOS transistor MP1, and the mirror current source module. The S pole of the MOS transistor MP1 is connected to the voltage VIN.

[0013] As a further solution of the present utility model: The mirror current source module includes a MOS transistor MP2. The S pole of the MOS transistor MP2 is connected to the voltage VIN. The G pole of the MOS transistor MP2 is connected to the set current source module. The D pole of the MOS transistor MP2 is connected to one end of a photoresistor RG and the amplification module. The other end of the photoresistor RG is grounded.

[0014] As a further solution of the present utility model: The amplification module includes an amplifier EA. The non-inverting input terminal of the amplifier EA is connected to the mirror current source module. The inverting input terminal of the amplifier EA receives the processed signal V0. The output terminal of the amplifier EA outputs to the ramp compensation circuit inside the chip U1.

[0015] Compared with the prior art, the beneficial effects of the present utility model are as follows: The present utility model samples and feeds back the voltage on the photoresistor to obtain the sampling voltage under different outdoor lighting conditions. The stronger the light, the higher the voltage, thus realizing the "adaptive" function. Using the voltages sampled under different light intensities to participate in the loop control of the charging management system to achieve automatic adjustment of the charging current and also protect the battery. Description of the Drawings

[0016] Figure 1 It is a schematic diagram of a solar adaptive charging management circuit.

[0017] Figure 2 It is a circuit diagram of the set current source module, the mirror current source module, and the amplification module. Detailed Embodiment

[0018] Next, the technical solutions in the embodiments of the present utility model will be clearly and completely described in conjunction with the drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all the embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present utility model.

[0019] Please refer to Figure 1 Figure 1 , a solar adaptive charging management circuit, including diode D1, capacitor C1, MOS transistor MP3, inductor L1, resistor R1, capacitor C2, battery E1, photoresistor RG, and chip U1. The positive electrode of diode D1 is connected to voltage VIN and the VIN pin of chip U1. The negative electrode of diode D1 is connected to one end of capacitor C1 and the S pole of MOS transistor MP3. The other end of capacitor C1 is grounded. The G pole of MOS transistor MP3 is connected to the DRV pin of chip U1. The D pole of MOS transistor MP3 is connected to one end of inductor L1. The other end of inductor L1 is connected to the CS pin of chip U1 and one end of resistor R1. The other end of resistor R1 is connected to one end of capacitor C2, the BAT pin of chip U1, and the positive electrode of battery E1. The other end of capacitor C2 is grounded. The negative electrode of battery E1 is grounded. The GND pin of chip U1 is grounded. The VSR pin of chip U1 is connected to one end of photoresistor RG. The other end of photoresistor RG is grounded. The model of chip U1 is YL3388.

[0020] Voltage VIN is input, and a 4.2V battery full charge voltage is output. The chip U1 internally controls the battery charging process through trickle, constant current, and constant voltage methods. The VSR pin is the input terminal of the external photoresistor RG. When the outdoor light is stronger, the resistance value of the photoresistor RG will increase, and the voltage sampled inside the chip U1 will be higher. The conduction degree of the MOS transistor MP3 will be higher. At this time, the charging current can be set to the maximum value and reach the maximum. On the contrary, when the light is weaker, the resistance value of the photoresistor RG will decrease, the sampled voltage will be smaller, and the charging current will decrease until the charging current is 0.

[0021] So that the circuit can still reasonably control the normal output current (that is, the charging current of battery E1) when the light is weak, and the battery E1 can still receive a continuous charging process. If there is no control and the circuit is still set to charge with a large current in low light, then the input power supply (the power supply converted from solar energy) will be forcibly pulled down by a strong load, resulting in insufficient power supply, the charging management loop cannot work properly, and the battery cannot be charged. This state is a waste of light energy and is also likely to damage the circuit system.

[0022] In this embodiment: Please refer to Figure 2 , the inside of the chip U1 includes:

[0023] A set current source module, used to set a first current source through a reference voltage;

[0024] A mirror current source module, used to obtain a second current source through mirroring based on the first current source, and obtain a voltage signal based on the resistance value of the photoresistor RG and supply it to the amplification module;

[0025] An amplification module for amplifying a voltage signal;

[0026] The set current source module is connected to the mirror current source module, and the mirror current source module is connected to the amplification module.

[0027] In this embodiment: Please refer to Figure 2 , the set current source module includes an amplifier OP1, a MOS transistor MP1, a MOS transistor MN1, and a resistor R2. The non-inverting terminal of the amplifier OP1 is connected to a reference voltage, the inverting terminal of the amplifier OP1 is connected to the S pole of the MOS transistor MN1 and one end of the resistor R2, the other end of the resistor R2 is grounded, the G pole of the MOS transistor MN1 is connected to the G pole of the amplifier OP1, the D pole of the MOS transistor MN1 is connected to the D pole of the MOS transistor MP1, the G pole of the MOS transistor MP1, and the mirror current source module, and the S pole of the MOS transistor MP1 is connected to the voltage VIN.

[0028] By setting the reference voltage VREF, the conduction state of the MOS transistor MN1 is controlled, and the magnitude of the current I1 in the loop of the voltage VIN, the MOS transistor MP1, the MOS transistor MN1, and the resistor R2 is controlled. The current I1 does not change with temperature and power supply voltage changes and is very suitable for use as a reference current source.

[0029] In this embodiment: Please refer to Figure 2 , the mirror current source module includes a MOS transistor MP2. The S pole of the MOS transistor MP2 is connected to the voltage VIN, the G pole of the MOS transistor MP2 is connected to the set current source module, and the D pole of the MOS transistor MP2 is connected to one end of a photoresistor RG and the amplification module, and the other end of the photoresistor RG is grounded.

[0030] The current I1 obtains the required reasonable final reference current I2 through a mirror ratio of N:1. Based on different resistances of the photoresistor RG, different voltage signals VSR are formed and output to the amplification module.

[0031] In this embodiment: Please refer to Figure 2 , the amplification module includes an amplifier EA. The non-inverting terminal of the amplifier EA is connected to the mirror current source module, the inverting terminal of the amplifier EA receives the processed signal V0, and the output terminal of the amplifier EA outputs to the ramp compensation circuit inside the chip U1.

[0032] After the amplification module completes error amplification, a PWM waveform is generated after passing through the ramp compensation circuit. The frequency of this PWM waveform is to control the conduction of the MOS transistor MP3, thereby completing the adjustment of the charging current of the battery E1. The ramp compensation circuit is a common circuit and will not be elaborated here.

[0033] The utility model samples and feeds back the voltage on the photoresistor to obtain the sampled voltage under different outdoor lighting conditions. The stronger the light, the higher the voltage, thus realizing the "adaptive" function. The voltages under different light intensities sampled are used to participate in the loop control of the charging management system to automatically adjust the charging current and protect the battery at the same time.

[0034] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting.

[0035] In addition, it should be understood that although this specification is described according to the embodiments, not every embodiment only contains an independent technical solution. This narrative way of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A solar adaptive charging management circuit, characterized in that: The solar adaptive charging management circuit includes a diode D1, a capacitor C1, a MOS tube MP3, an inductor L1, a resistor R1, a capacitor C2, a battery E1, a photoresistor RG, and a chip U1. The positive electrode of the diode D1 is connected to the voltage VIN and the VIN pin of the chip U1, the negative electrode of the diode D1 is connected to one end of the capacitor C1 and the S pole of the MOS tube MP3, the other end of the capacitor C1 is grounded, the G pole of the MOS tube MP3 is connected to the DRV pin of the chip U1, the D pole of the MOS tube MP3 is connected to one end of the inductor L1, the other end of the inductor L1 is connected to the CS pin of the chip U1 and one end of the resistor R1, the other end of the resistor R1 is connected to one end of the capacitor C2, the BAT pin of the chip U1, and the positive electrode of the battery E1, the other end of the capacitor C2 is grounded, the negative electrode of the battery E1 is grounded, the GND pin of the chip U1 is grounded, the VSR pin of the chip U1 is connected to one end of the photoresistor RG, and the other end of the photoresistor RG is grounded. The model of the chip U1 is YL3388.

2. The solar adaptive charging management circuit according to claim 1, characterized in that: The chip U1 includes: A current source setting module, used for setting a first current source through a reference voltage; A mirror current source module, used to obtain a second current source through mirroring based on the first current source, and to obtain a voltage signal based on the resistance value of the photoresistor RG to supply to the amplifier module; An amplification module, used for amplifying the voltage signal; The current source module is set to be connected to the mirror current source module, and the mirror current source module is connected to the amplification module.

3. The solar adaptive charging management circuit according to claim 2, characterized in that: The setting current source module includes an amplifier OP1, a MOS tube MP1, a MOS tube MN1, and a resistor R2. The in-phase end of the amplifier OP1 is connected to the reference voltage, the inverting end of the amplifier OP1 is connected to the S pole of the MOS tube MN1 and one end of the resistor R2, the other end of the resistor R2 is grounded, the G pole of the MOS tube MN1 is connected to the G pole of the amplifier OP1, the D pole of the MOS tube MN1 is connected to the D pole of the MOS tube MP1, the G pole of the MOS tube MP1, and the mirror current source module, and the S pole of the MOS tube MP1 is connected to the voltage VIN.

4. The solar adaptive charging management circuit according to claim 2, characterized in that: The mirror current source module includes a MOS tube MP2, the S pole of the MOS tube MP2 is connected to the voltage VIN, the G pole of the MOS tube MP2 is connected to the setting current source module, the D pole of the MOS tube MP2 is connected to one end of the photoresistor RG and the amplification module, and the other end of the photoresistor RG is grounded.

5. The solar adaptive charging management circuit according to claim 2, characterized in that: The amplification module includes an amplifier EA, a non-inverting end of the amplifier EA is connected to the mirror current source module, an inverting end of the amplifier EA receives the processed signal V0, and an output end of the amplifier EA is output to a slope compensation circuit inside the chip U1.

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