Display device

Abstract

A display device includes: a substrate including a display area and a peripheral area surrounding the display area and including a first peripheral area extending along a first direction with a first length and a second peripheral area extending along a second direction intersecting the first direction with a second length longer than the first length; a gate line disposed in the display area on the substrate and extending in a first direction; a main data line disposed in the display area on the substrate and extending in a first direction; a sub-data line disposed in the display area on the substrate and extending in a second direction; a gate driver corresponding to the gate line and disposed in the second peripheral region on the substrate; and a data driver corresponding to the main data line and disposed in the second peripheral area on the substrate.

Description

Technical Field

[0001] The implementation of the present utility model generally relates to a display device. More specifically, the implementation of the present utility model relates to a display device that provides visual information. Background Art

[0002] With the development of information technology, the importance of display devices as a medium connecting users and information is emerging. Therefore, the use of display devices such as liquid crystal display devices, organic light-emitting display devices, and plasma display devices is increasing.

[0003] Meanwhile, for security or safety reasons, a display device may display an image with a wide viewing angle, or may control the viewing angle of the image displayed in the display device to improve reflection. Summary of the Utility Model

[0004] An embodiment provides a display device with improved display quality.

[0005] The display device according to an embodiment of the present utility model may include: a substrate including a display area and a peripheral area, surrounding the display area and including a first peripheral area extending along a first direction with a first length and a second peripheral area extending along a second direction intersecting the first direction with a second length longer than the first length; gate lines disposed on the substrate in the display area and extending along the first direction; main data lines disposed on the substrate in the display area and extending along the first direction; sub-data lines disposed on the substrate in the display area and extending along the second direction; a gate driver corresponding to the gate lines and disposed on the substrate in the second peripheral area; and a data driver corresponding to the main data lines and disposed on the substrate in the second peripheral area.

[0006] In an embodiment, the main data lines and the sub-data lines may correspond to each other one by one and may be electrically connected.

[0007] In an embodiment, the second length may be about three times or more of the first length.

[0008] In an embodiment, the display area may include a first display area and a second display area adjacent to each other.

[0009] In an embodiment, the display device may further include: a first pixel disposed on a substrate in a first display area and including a first circuit and a first light-emitting device electrically connected to the first circuit and controlled by a first light-emitting control signal; a second pixel disposed on the substrate in a second display area and including a second circuit and a second light-emitting device electrically connected to the second circuit and controlled by the first light-emitting control signal; and a light control pattern disposed on at least one of the first pixel and the second pixel and blocking at least one of a part of the light emitted from the first pixel and a part of the light emitted from the second pixel.

[0010] In an embodiment, the light control pattern may not be disposed on the upper part of the first pixel, but may be disposed on the upper part of the second pixel.

[0011] In an embodiment, the light control pattern may be disposed on both the upper part of the first pixel and the upper part of the second pixel.

[0012] In an embodiment, the second pixel may further include a third light-emitting device electrically connected to the second circuit and controlled by a second light-emitting control signal, and the second light-emitting device and the third light-emitting device emit light of the same color.

[0013] In an embodiment, the first pixel may further include a fourth light-emitting device electrically connected to the first circuit and controlled by the first light-emitting control signal, and the first light-emitting device and the fourth light-emitting element emit light of the same color.

[0014] In an embodiment, the gate lines may include: a first gate line disposed parallel to each other across the first display area to correspond to the entire first display area; and a second gate line disposed parallel to each other across the second display area to correspond to the entire second display area. The main data lines may include: a first main data line disposed parallel to each other across the first display area to correspond to the entire first display area; and a second main data line disposed parallel to each other across the second display area to correspond to the entire second display area. And the sub-data lines may include: a first sub-data line disposed parallel to each other across the first display area to correspond to the entire first display area; and a second sub-data line disposed parallel to each other across the second display area to correspond to the entire second display area.

[0015] In an embodiment, the first main data line and the first sub-data line may correspond to each other one by one and may be electrically connected, and the second main data line and the second sub-data line may correspond to each other one by one and may be electrically connected.

[0016] In an embodiment, the gate driver may include: a first gate driver corresponding to a first gate line and disposed in a second peripheral region; and a second gate driver corresponding to a second gate line and disposed in the second peripheral region.

[0017] In an embodiment, the length of the first display region in the second direction may be the same as the length of the second display region in the second direction.

[0018] In an embodiment, the length of the first display region in the second direction may be different from the length of the second display region in the second direction.

[0019] A display device according to another embodiment of the present invention may include: a substrate including a display region and a peripheral region, the peripheral region surrounding the display region and including a first peripheral region extending along a first direction with a first length and a second peripheral region extending along a second direction intersecting the first direction with a second length longer than the first length; data lines disposed in the display region on the substrate and extending along the first direction; main gate lines disposed in the display region on the substrate and extending along the second direction; sub-gate lines disposed in the display region on the substrate and extending along the first direction; a data driver corresponding to the data lines and disposed in the second peripheral region on the substrate; a main gate driver corresponding to the main gate lines and disposed in the first peripheral region on the substrate; and a sub-gate driver corresponding to the sub-gate lines and disposed in the second peripheral region on the substrate.

[0020] In an embodiment, the number of main gate lines and the number of sub-gate lines may be the same.

[0021] In an embodiment, the main gate lines and the sub-gate lines may correspond to each other one by one and may be electrically connected.

[0022] In an embodiment, the line connecting the center point of the sub-gate driver and the center point of the display region may be parallel to the first direction in a plane.

[0023] In an embodiment, the length of the sub-gate driver in the second direction may be the same as the length of the main gate driver in the first direction.

[0024] In an embodiment, the sub-gate driver may be arranged to be spaced apart from the data driver in the first direction in a plane, and the display region is between the sub-gate driver and the data driver.

[0025] Therefore, signal distortion can be reduced or prevented in a display device having a large length ratio between a long side and a short side. For example, distortion of a gate signal in the center of a display device having a large length ratio between a long side and a short side can be reduced or prevented. Accordingly, the display quality of the display device can be improved. In addition, module design can be performed for each display area, and thus the length of the long side can be designed to be longer. Accordingly, the ease of designing the display device can be improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings, which are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the present invention together with the description.

[0027] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0028] Figure 2 is a plan view showing a display device according to another embodiment of the present invention.

[0029] Figure 3 is a circuit diagram showing an example of a first pixel included in Figure 2 the display device.

[0030] Figure 4 is a circuit diagram showing an example of a second pixel included in Figure 2 the display device.

[0031] Figure 5 is a plan view showing an example of Figure 3 the first pixel.

[0032] Figure 6 is a plan view showing an example of Figure 4 the second pixel.

[0033] Figure 7 is a plan view showing another example of Figure 4 the second pixel.

[0034] Figure 8 is a plan view showing another example of Figure 3 the first pixel.

[0035] Figure 9 is a cross-sectional view taken along line I-I' of Figure 5 this.

[0036] Figure 10 is a cross-sectional view taken along line II-II' of Figure 6 this.

[0037] Figure 11 is a cross-sectional view taken alongFigure 7 Cross-sectional view taken along line III-III'.

[0038] Figure 12 is a circuit diagram showing another example of a first pixel included in Figure 2 a display device.

[0039] Figure 13 is a circuit diagram showing another example of a second pixel included in Figure 2 a display device.

[0040] Figure 14 is a plan view showing a display device according to another embodiment of the present invention. Detailed Description

[0041] Exemplary, non-limiting embodiments will be more clearly understood from the following detailed description in conjunction with the accompanying drawings.

[0042] In this specification, a plane may be defined by a first direction D1 and a second direction D2 intersecting the first direction D1. For example, the second direction D2 may be perpendicular to the first direction D1. Additionally, a third direction D3 may be the normal direction of the plane. That is, the third direction D3 may be perpendicular to the plane formed by the first direction D1 and the second direction D2.

[0043] Figure 1 is a plan view showing a display device according to an embodiment of the present invention.

[0044] Referring to Figure 1 , the display device DD may include a display area DA and a peripheral area SA. The display area DA may be surrounded by the peripheral area SA.

[0045] The display area DA may be an area where an image can be displayed by generating light or adjusting the transmittance of light provided from an external light source. The peripheral area SA may be an area where an image may not be displayed. However, the present invention is not limited thereto, and the peripheral area SA may display an image.

[0046] The peripheral area SA may include a first peripheral area SA1 and a second peripheral area SA2. The first peripheral area SA1 may be disposed on both sides of the display area DA along the second direction D2 in the plane. That is, the first peripheral area SA1 may be arranged to be spaced apart along the second direction D2, and the display area DA may be interposed between the first peripheral areas SA1. The first peripheral area SA1 may extend along the first direction D1 and have a first length L1. In Figure 1 it, the first peripheral area SA1 is shown as a rectangular shape, but the present invention is not limited thereto.

[0047] The second peripheral region SA2 can be disposed on both sides of the display region DA in a plane along a first direction D1. That is to say, the second peripheral region SA2 can be arranged to be spaced apart along the first direction D1, and the display region DA is interposed between the second peripheral regions SA2. The second peripheral region SA2 can extend along a second direction D2 and has a second length L2. In Figure 1 FIG. Figure 1 , the second peripheral region SA2 is shown as a rectangular shape, but the present invention is not limited thereto.

[0048] In an embodiment, the second length L2 can be longer than the first length L1. Specifically, the second length L2 can be about three times or more of the first length L1. That is to say, the display device DD can include a short side extending along the first direction D1 and a long side extending along the second direction D2.

[0049] The display device DD can include a gate driver GIC, a data driver DIC, gate lines GL, main data lines MDL, and sub-data lines SDL.

[0050] The gate driver GIC can be disposed in the second peripheral region SA2. For example, the gate driver GIC can be disposed on both sides of the display region DA. Specifically, the gate driver GIC can be arranged to be spaced apart along the first direction D1, and the display region DA is interposed between the gate drivers GIC. However, the present invention is not necessarily limited thereto, and the gate driver GIC can be disposed only on one side of the display region DA. The gate driver GIC can correspond to the gate lines GL and the gate driver GIC can sequentially apply gate signals to the gate lines GL. In Figure 1 FIG. Figure 1 , one gate driver GIC is shown disposed on each side of the display region DA, but the present invention is not necessarily limited thereto. In another example, the display device DD can have a plurality of gate drivers GIC.

[0051] The data driver DIC can be disposed in the second peripheral region SA2. For example, the data driver DIC can be disposed on one side of the display region DA. However, the present invention is not necessarily limited thereto, and the data driver DIC can be disposed on both sides of the display region DA. The data driver DIC can correspond to the main data lines MDL and can apply data signals to the main data lines MDL. Although Figure 1 FIG. Figure 1 shows a plurality of data drivers DIC, but the present invention is not necessarily limited thereto, and in another example, the display device DD can include one data driver DIC.

[0052] The gate line GL may be disposed in the display area DA. The gate line GL may correspond to the gate driver GIC and the gate line GL may extend along the first direction D1. The gate lines GL may be arranged to be spaced apart along the second direction D2. The gate line GL may transmit a gate signal to the pixel PX. Meanwhile, in Figure 1 for ease of explanation, six gate lines GL are shown as being arranged to span the display area DA. However, the present invention is not necessarily limited thereto, and the gate lines GL may vary according to embodiments. Additionally, in Figure 1 all the gate lines GL are shown as having the same length, but the present invention is not necessarily limited thereto, and the length of at least one of the plurality of gate lines GL may be different from the lengths of the remaining gate lines GL.

[0053] The main data line MDL may be disposed in the display area DA. The main data line MDL may correspond to the data driver DIC and the main data line MDL may extend along the first direction D1. The main data lines MDL may be arranged to be spaced apart along the second direction D2. The main data line MDL may transmit a data signal to the pixel PX. Meanwhile, in Figure 1 for ease of explanation, six main data lines MDL are shown as being arranged to span the display area DA, but the present invention is not necessarily limited thereto, and the number of the main data lines MDL may vary according to embodiments. Further, in Figure 1 all the main data lines MDL are shown as having the same length, but the present invention is not necessarily limited thereto, and the length of at least one of the plurality of main data lines MDL may be different from the lengths of the remaining main data lines MDL.

[0054] The sub-data line SDL may be disposed in the display area DA. The sub-data line SDL may correspond to the main data line MDL and the sub-data line SDL may extend along the second direction D2. That is, the main data line MDL and the sub-data line SDL may be orthogonal to each other. The sub-data lines SDL may be arranged to be spaced apart along the first direction D1. The sub-data line SDL may transmit the data signal applied from the main data line MDL to the pixel PX. Meanwhile, in Figure 1 for ease of explanation, six main data lines MDL are shown as being arranged to span the display area DA, but the present invention is not necessarily limited thereto, and the number of the main data lines MDL may vary according to embodiments. Additionally, in Figure 1 all the main data lines MDL are shown as having the same length, but the present invention is not necessarily limited thereto, and the length of at least one of the plurality of main data lines MDL is different from the lengths of the remaining main data lines MDL.

[0055] In an embodiment, the main data line MDL and the sub data line SDL may correspond to each other one by one and may be electrically connected. For example, the main data line MDL and the sub data line SDL may be provided in the same number in the display area DA, and the main data line MDL and the sub data line SDL may transmit data signals to the pixels PX corresponding to each other one by one.

[0056] The display device DD according to an embodiment of the present invention may include a gate driver GIC and a data driver DIC provided in the second peripheral area SA2. In addition, the display device DD may include gate lines GL, main data lines MDL, and sub data lines SDL provided in the display area DA such that the flow of the gate signal and the data signal applied to the pixel PX may intersect. Accordingly, signal distortion in a display device having a large length ratio between a long side and a short side may be reduced or prevented. For example, distortion of the gate signal in the center of a display device having a large length ratio between a long side and a short side may be reduced or prevented. Accordingly, the display quality of the display device DD may be improved.

[0057] Figure 2 is a plan view showing a display device according to another embodiment of the present invention. Different from Figure 1 Different, Figure 2 shows a display device DD' divided by a dividing line PL. Accordingly, it may include a configuration substantially the same as the configuration described in Figure 1 and repetitive descriptions may be omitted or simplified.

[0058] Reference Figure 2 , the display device DD' may include a display area DA' and a peripheral area SA. The display area DA' may be surrounded by the peripheral area SA.

[0059] The peripheral area SA may include a first peripheral area SA1 and a second peripheral area SA2. Since the description of the peripheral area SA is repetitive with the content described in reference Figure 1 description, detailed description thereof will be omitted.

[0060] The display area DA' may include a first display area DA1 and a second display area DA2. In an embodiment, the first display area DA1 and the second display area DA2 may be adjacent to each other along the second direction D2. In addition, in Figure 2 , the dividing line PL is shown as one, but there may be a plurality of dividing lines PL. That is, the display area DA' may include three or more divided areas divided by the dividing line PL.

[0061] In an embodiment, the length of the first display area DA1 in the second direction D2 may be the same as the length of the second display area DA2 in the second direction D2. In other words, the display area DA' may be equally divided into the first display area DA1 and the second display area DA2 by a dividing line PL.

[0062] In another embodiment, the length of the first display area DA1 in the second direction D2 may be different from the length of the second display area DA2 in the second direction D2. In other words, the display area DA' may be unevenly divided into the first display area DA1 and the second display area DA2 by a dividing line PL.

[0063] The display device DD' may include a gate driver GIC', a data driver DIC, gate lines GL', main data lines MDL', and sub-data lines SDL'. Since the description of the data driver DIC is repetitive with the reference Figure 1 description, the detailed description will be omitted.

[0064] In an embodiment, the gate driver GIC' may include a first gate driver GIC1 and a second gate driver GIC2. Specifically, the first gate driver GIC1 may be set to correspond to the first display area DA1, and the second gate driver GIC2 may be set to correspond to the second display area DA2.

[0065] For example, the first gate driver GIC1 may be disposed on both sides of the first display area DA1. Specifically, the first gate driver GIC1 may be set to be spaced apart along the first direction D1, and the first display area DA1 is between the first gate drivers GIC1. However, the present invention is not limited thereto, and the first gate driver GIC1 may be disposed only on one side of the first display area DA1. The first gate driver GIC1 may correspond to the first gate line GL1 and the first gate driver GIC1 may sequentially apply gate signals to the first gate line GL1.

[0066] The second gate driver GIC2 may be disposed on both sides of the second display area DA2. Specifically, the second gate driver GIC2 may be set to be spaced apart from each other along the first direction D1, and the second display area DA2 is between the second gate drivers GIC2. However, the present invention is not limited thereto, and the second gate driver GIC2 may be disposed only on one side of the second display area DA2. The second gate driver GIC2 may correspond to the second gate line GL2 and the second gate driver GIC2 may sequentially apply gate signals to the second gate line GL2.

[0067] The gate lines GL' may include a first gate line GL1 and a second gate line GL2.

[0068] The first gate line GL1 may be disposed in the first display area DA1. For example, the first gate lines GL1 may be disposed to extend across the first display area DA1 in parallel with each other to correspond to the entire first display area DA1. Specifically, the first gate lines GL1 may extend along a first direction D1 and may be spaced apart from each other along a second direction D2 and disposed in the first display area DA1. Meanwhile, in Figure 2 for ease of explanation, three first gate lines GL1 are shown as being disposed to extend across the first display area DA1. However, the present invention is not limited thereto, and the number of the first gate lines GL1 may vary according to embodiments. In addition, in Figure 2 all of the first gate lines GL1 are shown as having the same length, but the present invention is not limited thereto, and the length of at least one of the plurality of first gate lines GL1 may be different from the lengths of the remaining first gate lines GL1.

[0069] In an embodiment, the first gate line GL1 may correspond to the first gate driver GIC1. That is, the first gate driver GIC1 may apply a gate signal to the first gate line GL1.

[0070] In an embodiment, the first gate line GL1 may apply a gate signal to the first pixel PX1.

[0071] The second gate line GL2 may be disposed in the second display area DA2. For example, the second gate lines GL2 may be disposed to extend across the second display area DA2 in parallel with each other to correspond to the entire second display area DA2. Specifically, the second gate lines GL2 may extend along the first direction D1 and may be spaced apart from each other along the second direction D2 and disposed in the second display area DA2. Meanwhile, in Figure 2 for ease of explanation, three second gate lines GL2 are shown as being disposed to extend across the second display area DA2. The present invention is not limited thereto, and the number of the second gate lines GL2 may vary according to embodiments. Additionally, in Figure 2 all of the second gate lines GL2 are shown as having the same length, but the present invention is not limited thereto, and the length of at least one of the plurality of second gate lines GL2 is different from the lengths of the remaining second gate lines GL2.

[0072] In an embodiment, the second gate line GL2 may correspond to the second gate driver GIC2. That is, the second gate driver GIC2 may apply a gate signal to the second gate line GL2.

[0073] In an embodiment, the second gate line GL2 may apply a gate signal to the second pixel PX2.

[0074] The main data line MDL' may include a first main data line MDL1 and a second main data line MDL2.

[0075] The first main data line MDL1 may be disposed in the first display area DA1. For example, the first main data line MDL1 may be arranged to extend across the first display area DA1 in parallel with each other to correspond to the entire first display area DA1. Specifically, the first main data line MDL1 may extend along the first direction D1 and be spaced apart from each other along the second direction D2 and disposed in the first display area DA1. Meanwhile, in Figure 2 For ease of explanation, three first main data lines MDL1 are shown as being arranged to extend across the first display area DA1. However, the present invention is not limited thereto, and the number of the first main data lines MDL1 may vary according to embodiments. Additionally, in Figure 2 All of the first main data lines MDL1 are shown as having the same length. However, the present invention is not limited thereto, and the length of at least one of the plurality of first main data lines MDL1 may be different from the lengths of the remaining first main data lines MDL1.

[0076] The second main data line MDL2 may be disposed in the second display area DA2. For example, the second main data line MDL2 may be arranged to extend across the second display area DA2 in parallel with each other to correspond to the entire second display area DA2. Specifically, the second main data line MDL2 may extend along the first direction D1 and may be spaced apart from each other along the second direction D2 and disposed in the second display area DA2. Meanwhile, in Figure 2 For ease of explanation, three second main data lines MDL2 are shown as being arranged to extend across the second display area DA2. However, the present invention is not limited thereto, and the number of the second main data lines MDL2 may vary according to embodiments. Additionally, in Figure 2 All of the second main data lines MDL2 are shown as having the same length. However, the present invention is not limited thereto, and the length of at least one of the plurality of second main data lines MDL2 may be different from the lengths of the remaining second main data lines MDL2.

[0077] The sub-data line SDL' may include a first sub-data line SDL1 and a second sub-data line SDL2.

[0078] The first sub-data line SDL1 may be disposed in the first display area DA1. For example, the first sub-data line SDL1 may be arranged to extend across the first display area DA1 in parallel with each other to correspond to the entire first display area DA1. Specifically, the first sub-data line SDL1 may extend along the second direction D2 and be spaced apart from each other along the first direction D1 and disposed in the first display area DA1. Meanwhile, in Figure 2In order to facilitate explanation, three first sub-data lines SDL1 are shown as being arranged to straddle the first display area DA1, but the present invention is not limited thereto. The number of the first sub-data lines SDL1 may vary according to embodiments. Additionally, in Figure 2 all of the first sub-data lines SDL1 are shown as having the same length, but the present invention is not limited thereto, and the length of at least one of the plurality of first sub-data lines SDL1 may be different from the lengths of the remaining first sub-data lines SDL1.

[0079] In an embodiment, the first sub-data lines SDL1 may correspond to the first main data line MDL1 one by one and may be electrically connected to transmit data signals.

[0080] The second sub-data lines SDL2 may be arranged in the second display area DA2. For example, the second sub-data lines SDL2 may be arranged to straddle the second display area DA2 in parallel with each other to correspond to the entire second display area DA2. Specifically, the second sub-data lines SDL2 may extend along the second direction D2 and may be spaced apart from each other along the first direction D1 and arranged in the second display area DA2. Meanwhile, in Figure 2 in order to facilitate explanation, three second sub-data lines SDL2 are shown as being arranged to straddle the second display area DA2, but the present invention is not limited thereto. The number of the second sub-data lines SDL2 may vary according to embodiments. Additionally, in Figure 2 all of the second sub-data lines SDL2 are shown as having the same length, but the present invention is not limited thereto, and the length of at least one of the plurality of second sub-data lines SDL2 may be different from the lengths of the remaining second sub-data lines SDL2.

[0081] In an embodiment, the second sub-data lines SDL2 may correspond to the second main data line MDL2 one by one and may be electrically connected to transmit data signals.

[0082] Figure 3 is a circuit diagram showing an example of a first pixel included in the Figure 2 display device.

[0083] Figure 4 is a circuit diagram showing an example of a second pixel included in the Figure 2 display device.

[0084] Refer to Figure 3 and Figure 4, the first pixel PX1 may include a first circuit (or a first circuit portion) PC1, a first light-emitting device LED1, and a second light-emitting device LED2, and the second pixel PX2 may include a second circuit (or a second circuit portion) PC2, a third light-emitting device LED3, and a fourth light-emitting device LED4. The first circuit PC1 may supply a first driving current to the first light-emitting device LED1 and the second light-emitting device LED2, and the second circuit PC2 may supply a second driving current to the third light-emitting device LED3 and the fourth light-emitting device LED4. The first light-emitting device LED1 and the second light-emitting device LED2 may emit light of the same color based on the first driving current. Additionally, the third light-emitting device LED3 and the fourth light-emitting device LED4 may emit light of the same color based on the second driving current.

[0085] That is to say, the first pixel PX1 may be electrically connected to the first circuit PC1, and the second pixel PX2 may be electrically connected to the second circuit PC2.

[0086] Each of the first circuit PC1 and the second circuit PC2 may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, and a ninth transistor T9, a first capacitor C1, and a second capacitor C2.

[0087] The first transistor T1 may include a gate electrode, a first electrode, and a second electrode. The gate electrode of the first transistor T1 may be connected to the second node N2. The driving voltage ELVDD may be applied to the first electrode of the first transistor T1. The second electrode of the first transistor T1 may be connected to the fourth node N4.

[0088] The second transistor T2 may include a gate electrode, a first electrode, and a second electrode. The first gate signal GW may be applied to the gate electrode of the second transistor T2. The data voltage VDATA may be applied to the first electrode of the second transistor T2. The second electrode of the second transistor T2 may be connected to the first node N1.

[0089] The third transistor T3 may include a gate electrode, a first electrode, and a second electrode. The second gate signal GC may be applied to the gate electrode of the third transistor T3. The first electrode of the third transistor T3 may be connected to the third node N3. The second electrode of the third transistor T3 may be connected to the fourth node N4.

[0090] The fourth transistor T4 may include a gate electrode, a first electrode, and a second electrode. A third gate signal GI may be applied to the gate electrode of the fourth transistor T4. A first initialization voltage VINT may be applied to the first electrode of the fourth transistor T4. The second electrode of the fourth transistor T4 may be connected to the third node N3.

[0091] The fifth transistor T5 may include a gate electrode, a first electrode, and a second electrode. A second gate signal GC may be applied to the gate electrode of the fifth transistor T5. A reference voltage VREF may be applied to the first electrode of the fifth transistor T5. The second electrode of the fifth transistor T5 may be connected to the first node N1.

[0092] The sixth transistor T6 may include a gate electrode, a first electrode, and a second electrode. The first electrode of the sixth transistor T6 may be connected to the fifth node N5. The second electrode of the sixth transistor T6 may be connected to the sixth node N6. In an embodiment, a first emission control signal (or a first light emission control signal) EM1 may be applied to the gate electrode of the sixth transistor T6 in the first circuit portion PC1 and the gate electrode of the sixth transistor T6 in the second circuit portion PC2. That is, the same light emission control signal may be applied to the gate electrodes of the sixth transistor T6 in the first circuit portion PC1 and the second circuit portion PC2.

[0093] The seventh transistor T7 may include a gate electrode, a first electrode, and a second electrode. A fourth gate signal GB may be applied to the gate electrode of the seventh transistor T7. A second initialization voltage VAINT may be applied to the first electrode of the seventh transistor T7. The second electrode of the seventh transistor T7 may be connected to the sixth node N6.

[0094] The eighth transistor T8 may include a gate electrode, a first electrode, and a second electrode. The first electrode of the eighth transistor T8 may be connected to the fifth node N5. The second electrode of the eighth transistor T8 may be connected to the seventh node N7. In an embodiment, in the first circuit portion PC1, a first emission control signal EM1 may be applied to the gate electrode of the eighth transistor T8, and in the second circuit portion PC2, a second emission control signal (or a second light emission control signal) EM2 may be applied to the gate electrode of the eighth transistor T8. That is, the light emission control signal applied to the gate electrode of the eighth transistor T8 included in the first circuit portion PC1 and the light emission control signal applied to the gate electrode of the eighth transistor T8 included in the second circuit portion PC2 may be different.

[0095] The ninth transistor T9 may include a gate electrode, a first electrode, and a second electrode. A fourth gate signal GB may be applied to the gate electrode of the ninth transistor T9. A second initialization voltage VAINT may be applied to the first electrode of the ninth transistor T9. The second electrode of the ninth transistor T9 may be connected to the seventh node N7.

[0096] The first capacitor C1 may include a first electrode and a second electrode. A driving voltage ELVDD may be applied to the first electrode of the first capacitor C1. The second electrode of the first capacitor C1 may be connected to the first node N1. In an embodiment, the first capacitor C1 may be a storage capacitor.

[0097] The second capacitor C2 may include a first electrode and a second electrode. The first electrode of the second capacitor C2 may be connected to the first node N1. The second electrode of the second capacitor C2 may be connected to the second node N2. In an embodiment, the second capacitor C2 may be a holding capacitor.

[0098] Each of the first light-emitting device LED1 and the third light-emitting device LED3 may include a first electrode (e.g., an anode electrode) and a second electrode (e.g., a cathode electrode). The first electrode of each of the first light-emitting device LED1 and the third light-emitting device LED3 may be connected to the sixth node N6. A common voltage ELVSS may be applied to the second electrode of each of the first light-emitting device LED1 and the third light-emitting device LED3. In an embodiment, the first light-emitting device LED1 and the third light-emitting device LED3 may be controlled by a first light-emitting control signal EM1.

[0099] Each of the second light-emitting device LED2 and the fourth light-emitting device LED4 may include a first electrode (e.g., an anode electrode) and a second electrode (e.g., a cathode electrode). The first electrode of each of the second light-emitting device LED2 and the fourth light-emitting device LED4 may be connected to the seventh node N7. A common voltage ELVSS may be applied to the second electrode of each of the second light-emitting device LED2 and the fourth light-emitting device LED4. In an embodiment, the second light-emitting device LED2 may be controlled by a first emission control signal EM1, and the fourth light-emitting device LED4 may be controlled by a second emission control signal EM2.

[0100] For example, when the first emission control signal EM1 has an active level, the eighth transistor T8 of the first circuit PC1, the sixth transistor T6 of the first circuit PC1, and the sixth transistor T6 of the second circuit PC2 can be turned on. Additionally, the first transistor T1 can also be turned on by the data voltage VDATA. In this case, in the first circuit PC1, a first driving current can pass through the first transistor T1 to drive the first light-emitting device LED1 and the second light-emitting device LED2. Furthermore, in the second circuit PC2, a second driving current can pass through the first transistor T1 to drive the third light-emitting device LED3.

[0101] For example, when the second emission control signal EM2 has an active level, the eighth transistor T8 of the second circuit portion PC2 can be turned on. Additionally, the first transistor T1 can also be turned on by the data voltage VDATA. In this case, in the second circuit PC2, a second driving current can pass through the first transistor T1 to drive the fourth light-emitting device LED4.

[0102] For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, the eighth transistor T8, and the ninth transistor T9 can be a P-type thin film transistor. However, the embodiments of the present invention are not limited thereto.

[0103] However, in Figure 2 and Figure 3 each of the first pixel PX1 and the second pixel PX2 is shown as including 9 transistors, 2 capacitors, and 2 light-emitting devices, the embodiments of the present invention are not limited thereto.

[0104] Figure 5 is a plan view showing an example of the first pixel of Figure 3 . For example, Figure 5 is a plan view schematically showing an example of the arrangement of the light-emitting devices LED1 and LED2 of the first pixel PX1 of Figure 3 .

[0105] Referring to Figure 5 , the first pixel PX1 can include a first light-emitting device LED1 and a second light-emitting device LED2.

[0106] In an embodiment, the first light-emitting device LED1 and the second light-emitting device LED2 may emit light of the same color. For example, the first light-emitting device LED1 and the second light-emitting device LED2 may emit red light. As another example, the first light-emitting device LED1 and the second light-emitting device LED2 may emit green light. As still another example, the first light-emitting device LED1 and the second light-emitting device LED2 may emit blue light. However, the embodiments of the present utility model are not limited thereto, and the first light-emitting device LED1 and the second light-emitting device LED2 may emit light of a color other than red, green, and blue.

[0107] Figure 6 is a plan view showing an example of Figure 4 the second pixel.

[0108] Figure 7 is a plan view showing another example of Figure 4 the second pixel.

[0109] For example, Figure 6 and Figure 7 is a plan view schematically showing an example of the arrangement of the light-emitting devices LDE3 and LED4 of Figure 4 the second pixel PX2.

[0110] In an embodiment, the third light-emitting device LED3 and the fourth light-emitting device LED4 may emit light of the same color. For example, the third light-emitting device LED3 and the fourth light-emitting device LED4 may emit red light. As another example, the third light-emitting device LED3 and the fourth light-emitting device LED4 may emit green light. As still another example, the third light-emitting device LED3 and the fourth light-emitting device LED4 may emit blue light. However, the embodiments of the present utility model are not limited thereto, and the third light-emitting device LED3 and the fourth light-emitting device LED4 may emit light of a color other than red, green, and blue.

[0111] As Figures 5 to 7As shown, the first light-emitting device LED1, the second light-emitting device LED2, the third light-emitting device LED3, and the fourth light-emitting device LED4 can all emit light of the same color. For example, the first light-emitting device LED1, the second light-emitting device LED2, the third light-emitting device LED3, and the fourth light-emitting device LED4 can emit red light. As another example, the first light-emitting device LED1, the second light-emitting device LED2, the third light-emitting device LED3, and the fourth light-emitting device LED4 can emit green light. As still another example, the first light-emitting device LED1, the second light-emitting device LED2, the third light-emitting device LED3, and the fourth light-emitting device LED4 can emit blue light. However, the embodiments of the present invention are not limited thereto, and the first light-emitting device LED1, the second light-emitting device LED2, the third light-emitting device LED3, and the fourth light-emitting device LED4 can emit light of a color other than red, green, and blue.

[0112] The light control pattern LCP can be disposed on the second pixel PX2. Specifically, the light control pattern LCP can overlap with the third light-emitting device LED3 and / or the fourth light-emitting device LED4 of the second pixel PX2 in a plane.

[0113] That is to say, in the embodiment, the light control pattern LCP can overlap with one of the third light-emitting device LED3 and the fourth light-emitting device LED4 in a plane, and can be spaced apart from the other of the third light-emitting device LED3 and the fourth light-emitting device LED4 in a plane. For example, as Figure 6 shown, the light control pattern LCP can overlap with the fourth light-emitting device LED4 in a plane and can be spaced apart from the third light-emitting device LED3 in a plane.

[0114] In another embodiment, as Figure 7 shown, the light control pattern LCP can overlap with both the third light-emitting device LED3 and the fourth light-emitting device LED4 in a plane.

[0115] The light control pattern LCP can control the viewing angle by blocking a part of the light emitted from the third light-emitting device LED3 and / or the fourth light-emitting device LED4. In the embodiment, the light control pattern LCP can include an inorganic material. In the embodiment, the light control pattern LCP can include molybdenum tantalum oxide (MTO). For example, the light control pattern LCP can include MTO, MTO / Mo, MTO / Cu, MTO / Al, MTO / Mo / MTO, MTO / Cu / MTO, MTOAl / MTO, etc. These can be used alone or in combination with each other. However, the light control pattern LCP can be not limited to including MTO, and can include various materials having relatively low transmittance and reflectance and relatively high absorptance.

[0116] In another embodiment, the light control pattern LCP may include an organic material containing a light-blocking material such as black pigment, black dye, etc.

[0117] For example, when an image is displayed in a mode for controlling the viewing angle in the second direction D2 (or the first direction D1), the first light emission control signal EM1 (see Figure 3 ) has a disabled level, and the second light emission control signal EM2 (see Figure 4 ) may have an active level. In this case, the first light-emitting device LED1 and the second light-emitting device LED2 provided in the first display area DA1 may be turned off, and the third light-emitting device LED3 provided in the second display area DA2 may be turned off, and the fourth light-emitting device LED4 provided in the second display area DA2 may be turned on. Therefore, the light control pattern LCP may block a part of the light emitted from the fourth light-emitting device LED4 and traveling in the second direction D2. Therefore, the image may not be visible in the second direction D2 of the display device DD' (see Figure 2 ).

[0118] For example, when an image is displayed in a mode for not controlling the viewing angle, each of the first emission control signal EM1 and the second emission control signal EM2 may have an active level. In this case, the first light-emitting device LED1 and the second light-emitting device LED2 provided in the first display area DA1 and the third light-emitting device LED4 and the fourth light-emitting device LED4 provided in the second display area DA2 may all be turned on. Therefore, the image can be observed in the first direction D1 and the second direction D2 of the display device DD'.

[0119] In an embodiment, the display device according to an embodiment of the present invention may be applied to a vehicle display. The display device may display an image with a narrow viewing angle or a wide viewing angle. Therefore, the viewing angle of the driver (or passenger) can be controlled as needed.

[0120] Figure 8 is a plan view showing another example of the first pixel of Figure 3 .

[0121] Referring to Figure 8 , the light control pattern LCP may also be provided on the upper part of the first pixel PX1. Specifically, the light control pattern LCP may overlap with the first light-emitting device LED1 and / or the second light-emitting device LED2 of the first pixel PX1 in a plane.

[0122] That is, in an embodiment, the light control pattern LCP may overlap with one of the first light-emitting device LED1 and the second light-emitting device LED2 in a plane, and may be spaced apart from the other of the first light-emitting device LED1 and the second light-emitting device LED2 in a plane. For example, asFigure 8 As shown, the light control pattern LCP can overlap with the second light-emitting device LED2 on a plane and can be spaced apart from the first light-emitting device LED1 on the plane.

[0123] In Figure 8 In another embodiment not shown, the light control pattern LCP can overlap with both the first light-emitting device LED1 and the second light-emitting device LED2 on a plane.

[0124] That is to say, as Figures 5 to 8 shown, the light control pattern LCP can overlap with the first pixel PX1 and / or the second pixel PX2 on a plane.

[0125] Figure 9 is a cross-sectional view taken along Figure 5 line I-I' of

[0126] Referring to Figure 9 , the display device DD' according to an embodiment of the present invention may include a substrate SUB, a circuit element layer CEL, a pixel defining layer PDL, a first light-emitting device LED1, a second light-emitting device LED2, and a packaging layer ENC.

[0127] The substrate SUB may be an insulating substrate including a transparent material or an opaque material. For example, the substrate SUB may include glass. Optionally, the substrate SUB may include plastic. In this case, the display device DD' may be a flexible display device.

[0128] The circuit element layer CEL may be disposed on the substrate SUB. The circuit element layer CEL may include at least one transistor and at least one insulating layer. For example, the circuit element layer CEL may include Figure 3 the first circuit PC1 of

[0129] The first light-emitting device LED1 and the second light-emitting device LED2 may be disposed on the circuit element layer CEL.

[0130] The first light-emitting device LED1 may include a first pixel electrode PE1, a first light-emitting layer (or first emission layer) EL1, and a common electrode CE. Specifically, the first light-emitting layer EL1 may be located on the first pixel electrode PE1, and the common electrode CE may be located on the first light-emitting layer EL1.

[0131] The second light-emitting device LED2 may include a second pixel electrode PE2, a second light-emitting layer (or second emission layer) EL2, and a common electrode CE. Specifically, the second light-emitting layer EL2 may be located on the second pixel electrode PE2, and the common electrode CE may be located on the second light-emitting layer EL2.

[0132] Each of the first pixel electrode PE1 and the second pixel electrode PE2 may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other. The first pixel electrode PE1 and the second pixel electrode PE2 are formed by the same process and may include the same materials.

[0133] The pixel defining layer PDL may be disposed on the first pixel electrode PE1 and the second pixel electrode PE2. The pixel defining layer PDL may expose at least a part of each of the first pixel electrode PE1 and the second pixel electrode PE2. The pixel defining layer PDL may include an inorganic insulating material or an organic insulating material.

[0134] The first light emitting layer EL1 and the second light emitting layer EL2 may be respectively disposed on the first pixel electrode PE1 and the second pixel electrode PE2. The first emission layer EL1 and the second emission layer EL2 may emit light of the same color. For example, the first light emitting layer EL1 and the second light emitting layer EL2 may emit red light. Again for example, the first emission layer EL1 and the second emission layer EL2 may emit green light. Again for example, the first light emitting layer EL1 and the second light emitting layer EL2 may emit blue light. However, the embodiments of the present invention are not limited thereto, and the first light emitting layer EL1 and the second light emitting layer EL2 may emit light of a color other than red, green, and blue.

[0135] The common electrode CE may be disposed on the first emission layer EL1 and the second emission layer EL2. The common electrode CE may be disposed on the entire surface of the display area DA' (for example, see Figure 2 ). For example, the common electrode CE may include a metal, an alloy, a metal nitride, a conductive metal oxide, a transparent conductive material, etc. These may be used alone or in combination with each other.

[0136] The encapsulation layer ENC may be disposed on the common electrode CE. The encapsulation layer ENC may protect the first light emitting device LED1 and the second light emitting device LED2 from external moisture, heat, impact, etc. Although not shown, the encapsulation layer ENC may include at least one inorganic encapsulation layer and at least one organic encapsulation layer.

[0137] Figure 10 is a cross-sectional view taken along the Figure 6 line II-II'.

[0138] Figure 11 is a cross-sectional view taken along the Figure 7 line III-III'.

[0139] Except for the light control pattern LCP and the light transmissive layer LTL, the configurations described with reference to Figure 10 and Figure 11 may be the same as those described with reference toFigure 9 The described configurations are substantially the same. Therefore, repeated explanations can be omitted or simplified.

[0140] Reference Figure 10 and Figure 11 , the display device DD' may include a substrate SUB, a circuit element layer CEL, a third light-emitting device LED3, a fourth light-emitting device LED4, a pixel defining layer PDL, a packaging layer ENC, a light-transmitting layer LTL, and a light control pattern LCP.

[0141] The circuit element layer CEL may include at least one transistor and at least one insulating layer. For example, the circuit element layer CEL may further include Figure 4 the second circuit PC2.

[0142] The third light-emitting device LED3 and the fourth light-emitting device LED4 may be disposed on the circuit element layer CEL.

[0143] The third light-emitting device LED3 may include a third pixel electrode PE3, a third light-emitting layer (or third emission layer) EL3, and a common electrode CE. Specifically, the third light-emitting layer EL3 may be located on the third pixel electrode PE3, and the common electrode CE may be located on the third light-emitting layer EL3.

[0144] The fourth light-emitting device LED4 may include a fourth pixel electrode PE4, a fourth light-emitting layer EL4, and a common electrode CE. Specifically, the fourth light-emitting layer (or fourth emission layer) EL4 may be located on the fourth pixel electrode PE4, and the common electrode CE may be located on the fourth light-emitting layer EL4.

[0145] The pixel defining layer PDL may be disposed on the third pixel electrode PE3 and the fourth pixel electrode PE4. The pixel defining layer PDL may expose at least a part of each of the third pixel electrode PE3 and the fourth pixel electrode PE4.

[0146] The third light-emitting layer EL3 and the fourth light-emitting layer EL4 may be respectively disposed on the third pixel electrode PE3 and the fourth pixel electrode PE4. The third emission layer EL3 and the fourth emission layer EL4 may emit light of the same color. For example, the third light-emitting layer EL3 and the fourth light-emitting layer EL4 may emit the same red light. Optionally, the third light-emitting layer EL3 and the fourth light-emitting layer EL4 may emit green light or blue light. However, the present invention is not limited thereto, and the third light-emitting layer EL3 and the fourth light-emitting layer EL4 may emit light of a mixed color including red, green, and blue.

[0147] The common electrode CE may be disposed on the third light-emitting layer EL3 and the fourth light-emitting layer EL4. In addition, the packaging layer ENC may be disposed on the common electrode CE.

[0148] The light-transmitting layer LTL can be disposed on the encapsulation layer ENC. The light-transmitting layer LTL can fill the space between the light control patterns LCP. For example, the light-transmitting layer LTL can include an organic insulating material having a relatively high light transmittance. The light-transmitting layer LTL can have a substantially flat top surface.

[0149] The light control pattern LCP can be arranged to overlap with the third light-emitting device LED3 and / or the fourth light-emitting device LED4 in a plane. For example, as Figure 10 shown, the light control pattern LCP may not be disposed on the third light-emitting device LED3, but may be disposed on the fourth light-emitting device LED4. Again, for example, as Figure 11 shown, the light control pattern LCP can be disposed on both the third light-emitting device LED3 and the fourth light-emitting device LED4.

[0150] Figure 12 is a circuit diagram showing another example of the first pixel included in the Figure 2 display device.

[0151] Figure 13 is a circuit diagram showing another example of the second pixel included in the Figure 2 display device.

[0152] Except for omitting the Figure 3 eighth transistor T8, ninth transistor T9, and second light-emitting device LED2 shown in Figure 12 , the first pixel PX1' described with reference to Figure 3 can be substantially the same as the first pixel PX1 described with reference to

[0153] . Therefore, repeated explanations can be omitted or simplified. Figure 4 In addition, except for omitting the Figure 13 eighth transistor T8, ninth transistor T9, and fourth light-emitting device LED4 shown in Figure 4 , the second pixel PX2' described with reference to

[0154] can be substantially the same as the second pixel PX2 described with reference to Figure 12 . Therefore, repeated explanations can be omitted or simplified.

[0155] With reference to Figure 13, the second pixel PX2' may include a second circuit PC2' and a third light-emitting device LED3'. The second circuit PC2' may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7, a first capacitor C1, and a second capacitor C2. That is, in the embodiment, the second pixel PX2' may include only one light-emitting device.

[0156] Combined with Figure 2 , according to an embodiment of the present invention, the display device DD' may include a display area DA' divided into two or more regions. For example, the display device DD' may be divided into a first display area DA1 and a second display area DA2 to control the viewing angle. Therefore, the display device DD' may display an image with a narrow viewing angle or a wide viewing angle.

[0157] At this time, a plurality of light-emitting devices provided in one region of the display area DA' may be independently controlled by different light-emitting control signals. Therefore, even when an image is displayed with a narrow viewing angle that controls the viewing angle in a specific direction, the light-emitting efficiency of the display device DD' may not be reduced.

[0158] In addition, when the display device DD' is divided into the first display area DA1 and the second display area DA2, the display device DD' may include a first gate driver GIC1 provided in the second peripheral area SA2 corresponding to the first display area DA1, a second gate driver GIC2 provided in the second peripheral area SA2 corresponding to the second display area DA2, and a data driver DIC provided in the second peripheral area SA2. In addition, the display device DD' may include gate lines GL', main data lines MDL', and sub-data lines SDL' provided in the display area DA' such that gate signals and data signals applied to each of the first pixel PX1 and the second pixel PX2 may intersect. Therefore, signal distortion in a display device having a large length ratio between the long side and the short side may be reduced or prevented. For example, distortion of the gate signal in the center of a display device having a large length ratio between the long side and the short side may be reduced or prevented. Therefore, the display quality of the display device DD' may be improved.

[0159] Figure 14 is a plan view showing a display device according to another embodiment of the present invention. Hereinafter, among the components described with reference to Figure 14 Among the components described, a description of a part that is repeated with the components described with reference to Figure 1 may be omitted or simplified.

[0160] Reference Figure 14, the display device DD” may include a display area DA and a peripheral area SA. The display area DA may be surrounded by the peripheral area SA.

[0161] The peripheral area SA may include a first peripheral area SA1 and a second peripheral area SA2.

[0162] The display device DD” may include a main gate driver MGIC, a sub - gate driver SGIC, a data driver DIC, a main gate line MGL, a sub - gate line SGL, and a data line DL.

[0163] The main gate driver MGIC may be disposed on both sides of the display area DA. Specifically, the main gate drivers MGIC may be arranged to be spaced apart from each other along the second direction D2, and the display area DA is between the main gate drivers MGIC. However, the present utility model is not limited thereto, and the main gate driver MGIC may be disposed only on one side of the display area DA. The main gate driver MGIC may correspond to the main gate line MGL and may sequentially apply gate signals to the main gate line MGL.

[0164] The sub - gate driver SGIC may be disposed in the second peripheral area SA2. Specifically, the sub - gate driver SGIC may be disposed on one side of the display area DA. However, the present utility model is not limited thereto, and the sub - gate driver SGIC may be disposed on both sides of the display area DA. For example, the sub - gate drivers SGIC may be arranged to be spaced apart from each other along the first direction D1, and the display area DA is between the sub - gate drivers SGIC. The sub - gate driver SGIC may correspond to the sub - gate line SGL and may sequentially apply gate signals to the sub - gate line SGL.

[0165] The data driver DIC may be disposed in the second peripheral area SA2. Specifically, the data driver DIC may be disposed on one side of the display area DA. However, the present utility model is not limited thereto, and the data drivers DIC may be arranged to be spaced apart along the first direction D1, and the display area DA is between the data drivers DIC. The data driver DIC may correspond to the data line DL and apply data signals to the data line DL.

[0166] In an embodiment, an imaginary line connecting the center point of the sub - gate driver SGIC and the center point of the display area DA may be parallel to the first direction D1. That is to say, the sub - gate line SGL corresponding to the sub - gate driver SGIC may be disposed in the center of the display area DA.

[0167] In an embodiment, the length of the sub-gate driver SGIC in the second direction D2 may be the same as the length of the main gate driver MGIC in the first direction D1. Accordingly, the number of sub-gate lines SGL corresponding to the sub-gate driver SGIC and the number of main gate lines MGL corresponding to the main gate driver MGIC may be the same. However, the present invention is not necessarily limited thereto, and the number of main gate lines MGL and the number of sub-gate lines SGL may vary according to the embodiment.

[0168] The main gate lines MGL may be disposed in the display area DA. The main gate lines MGL may correspond to the main gate driver MGIC and may extend along the second direction D2. The main gate lines MGL may be disposed to be spaced apart along the first direction D1. The main gate lines MGL may transmit the main gate signal to the pixels PX. Meanwhile, in Figure 14 For ease of explanation, six main gate lines MGL are shown as being disposed to span the display area DA, but the present invention is not necessarily limited thereto, and the number of main gate lines MGL may vary according to the embodiment. In addition, in Figure 14 All of the main gate lines MGL are shown as having the same length, but the present invention is not necessarily limited thereto, and the length of at least one of the plurality of main gate lines MGL is different from the lengths of the remaining main gate lines MGL.

[0169] In an embodiment, the main gate lines MGL may include a metal having a low resistivity. For example, the main gate lines MGL may include aluminum-based metals such as aluminum (Al) and aluminum alloys, silver-based metals such as silver (Ag) and silver alloys, copper-based metals such as copper (Cu) and copper alloys, molybdenum-based metals such as molybdenum (Mo) and molybdenum alloys, chromium (Cr), titanium (Ti), and tantalum (Ta), etc. These may be used alone or in combination with each other.

[0170] The sub-gate lines SGL may be disposed in the display area DA. The sub-gate lines SGL may correspond to the sub-gate driver SGIC and may extend along the first direction D1. That is, the sub-gate lines SGL may be perpendicular to the main gate lines MGL. The sub-gate lines SGL may be disposed to be spaced apart along the second direction D2. The sub-gate lines SGL may transmit the sub-gate signal to the main gate lines MGL. Meanwhile, in Figure 14 For ease of explanation, six sub-gate lines SGL are shown as being disposed to span the display area DA. However, the present invention is not necessarily limited thereto, and the number of sub-gate lines SGL may vary according to the embodiment. Additionally, in Figure 14 All of the sub-gate lines SGL are shown as having the same length, but the present invention is not necessarily limited thereto, and the length of at least one of the plurality of sub-gate lines SGL is different from the lengths of the remaining sub-gate lines SGL.

[0171] In an embodiment, the main gate line MGL and the sub-gate line SGL can correspond to each other one by one and can be electrically connected.

[0172] The sub-gate driver SGIC can transmit an additional gate signal to the main gate line MGL through the sub-gate line SGL, thereby reducing signal distortion in the center of the display area DA. Therefore, signal distortion in a display device having a large length ratio between the long side and the short side can be reduced or prevented.

[0173] The data line DL can be disposed in the display area DA. The data line DL can correspond to the data driver DIC and the data line DL can extend along the first direction D1. The data lines DL can be arranged to be spaced apart along the second direction D2. The data line DL can apply a data signal to the pixel PX. Meanwhile, in Figure 14 For ease of explanation, six data lines DL are shown as being disposed across the display area DA. However, the present invention is not limited thereto, and the number of data lines DL can vary according to the embodiment. In addition, in Figure 14 All the data lines DL are shown as having the same length, but the present invention is not limited thereto, and the length of at least one of the plurality of data lines DL can be different from the lengths of the remaining data lines DL.

[0174] A display device according to various embodiments of the present invention can include a display area DA and a peripheral area SA surrounding the display area DA, and the peripheral area SA can include a first peripheral area SA1 having a first length L1 and a second peripheral area SA2 having a second length L2 longer than the first length L1.

[0175] In addition, the display device can include a gate driver and a data driver disposed in the second peripheral area SA2. Additionally, the display device can have an arrangement structure of signal lines (e.g., gate lines and data lines) in which the flow of the gate signal applied to the pixel PX and the flow of the data signal can intersect each other. Therefore, signal distortion in a display device having a large length ratio between the long side and the short side can be reduced or prevented. For example, distortion of the gate signal in the center of a display device having a large length ratio between the long side and the short side can be reduced or prevented. Therefore, the display quality of the display device can be improved.

[0176] In addition, each display area can be modularly designed, so the length of the long side can be designed to be longer. Therefore, the ease of designing the display device can be improved.

[0177] Although specific embodiments and implementations have been described herein, other embodiments and modifications will be apparent from this description. Accordingly, the present utility model is not limited to such embodiments, but rather to the broader scope of the appended claims and to various obvious modifications and equivalent arrangements that will be apparent to those of ordinary skill in the art.

Claims

1. A display device, characterized in that: The display device comprises: a substrate including a display area and a peripheral area surrounding the display area and including a first peripheral area extending along a first direction having a first length and a second peripheral area extending along a second direction intersecting the first direction having a second length longer than the first length; a gate line, disposed on the substrate in the display area and extending along the first direction; A main data line, disposed on the substrate in the display area and extending along the first direction; a sub-data line, disposed on the substrate in the display area and extending along the second direction; a gate driver corresponding to the gate line and disposed in the second peripheral area on the substrate; and A data driver corresponds to the main data line and is disposed in the second peripheral area on the substrate.

2. The display device according to claim 1, characterized in that The main data lines and the sub data lines correspond to each other one by one and are electrically connected.

3. The display device according to claim 1, characterized in that The display area includes a first display area and a second display area adjacent to each other, and Wherein, the display device further includes: a first pixel, disposed in the first display area on the substrate and comprising a first circuit and a first light emitting device electrically connected to the first circuit and controlled by a first light emitting control signal; a second pixel disposed in the second display area on the substrate and comprising a second circuit and a second light emitting device electrically connected to the second circuit and controlled by the first light emitting control signal; and A light-controlling pattern is disposed on at least one of the first pixel and the second pixel and blocks at least one of a portion of light emitted from the first pixel and a portion of light emitted from the second pixel.

4. The display device according to claim 3, characterized in that: The light-controlling pattern is not disposed on an upper portion of the first pixel but is disposed on an upper portion of the second pixel.

5. The display device according to claim 3, characterized in that: The light-controlling pattern is disposed on both an upper portion of the first pixel and an upper portion of the second pixel.

6. The display device according to claim 3, characterized in that: The second pixel further includes a third light emitting device, the third light emitting device being electrically connected to the second circuit and being controlled by a second light emitting control signal, and The second light emitting device and the third light emitting device emit light of the same color.

7. The display device according to claim 3, characterized in that: The gate line comprises: first gate lines are arranged to cross the first display area in parallel with each other to correspond to the entire first display area; and second gate lines are arranged to cross the second display area in parallel with each other to correspond to the entire second display area, The main data line includes: first main data lines are arranged to cross the first display area in parallel with each other to correspond to the entire first display area; and second main data lines are arranged to cross the second display area in parallel with each other to correspond to the entire second display area, and The sub-data line comprises: first sub-data lines are arranged to cross the first display area in parallel with each other to correspond to the entire first display area; and The second sub data lines are arranged to cross the second display area in parallel with each other to correspond to the entire second display area.

8. The display device according to claim 7, characterized in that: The first main data lines and the first sub data lines correspond to each other one by one and are electrically connected, and The second main data lines and the second sub data lines correspond to each other one by one and are electrically connected.

9. A display device, characterized in that: The display device comprises: a substrate including a display area and a peripheral area surrounding the display area and including a first peripheral area extending along a first direction with a first length and a second peripheral area extending along a second direction intersecting the first direction with a second length longer than the first length; A data line, disposed on the substrate in the display area and extending along the first direction; A main gate line, disposed on the substrate in the display area and extending along the second direction; A sub-gate line, disposed on the substrate in the display area and extending along the first direction; a data driver corresponding to the data line and disposed on the substrate in the second peripheral area; a main gate driver corresponding to the main gate line and disposed in the first peripheral region on the substrate; and A sub-gate driver corresponds to the sub-gate line and is disposed in the second peripheral area on the substrate.

10. The display device according to claim 9, characterized in that: The number of the main gate lines is the same as the number of the sub-gate lines.

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