Anti-peak surge optoelectronic isolator reliability test circuit

Abstract

The utility model relates to a reliability test circuit for an anti-peak surge optoelectronic isolator, and belongs to the technical field of optoelectronic device testing. The test circuit comprises a signal module, a signal amplification module, a control module, an output module, a load module, a display module, a power supply module VCC and a power supply module VDD. The output end of the signal module is connected with the input end of the signal amplification module, the output end of the signal amplification module is connected with the input end of the control module, the output end of the control module is optically connected with the input end of the output module, the output end of the output module is connected with the load module, and the power module VCC is connected with the power supply ends of the signal module and the signal amplification module. The power supply module VDD is connected with the power supply ends of the control module, the output module, the load module and the display module, and the display module is connected with the output module and the load module. The problem that in the prior art, an optoelectronic isolator reliability test cannot carry out an integrated overall test on an optoelectronic isolator is solved. The device is widely applied to the optoelectronic isolator reliability test technology.

Description

Technical Field

[0001] The utility model belongs to the technical field of optoelectronic device testing, and further relates to the technical field of optoelectronic isolator testing. Specifically, it relates to a reliability test circuit for an anti-spike surge optoelectronic isolator. Background Art

[0002] An anti-spike surge optoelectronic isolator is a photovoltaic isolation voltage control module. It mainly uses the function of optoelectronic isolation to control conduction and turn-off, has strong load capacity, and can directly drive the load to work. It can be directly used for spike voltage 600V / 10μs test and surge 80V / 50ms test.

[0003] For anti-spike surge optoelectronic isolators, the existing reliability test methods mainly conduct reliability tests on the optoelectronic isolator by dividing it into two parts, namely the front control end and the rear power working end. The disadvantages are as follows:

[0004] 1. The test efficiency of the two parts separately is relatively low.

[0005] 2. During the test, the front and rear ends cannot work in coordination. That is, when the front control end is tested, the rear power working end does not work, and when the rear power working end is working, the front control end does not work. It cannot fully reflect the actual working state of the device and cannot fully evaluate the reliability state of the device.

[0006] In view of this, the present utility model is specifically proposed. Summary of the Invention

[0007] The technical problem to be solved by the present utility model is to solve the problem that in the existing reliability test method of optoelectronic isolators, the optoelectronic isolator needs to be divided into a front control end and a rear power working end for separate reliability tests, and an integrated overall test of the optoelectronic isolator cannot be carried out.

[0008] The invention object of the present utility model is:

[0009] (1) To enable the front control end and the rear power end of the anti-spike surge optoelectronic isolator to work in coordination simultaneously to achieve the screening purpose of the whole product working simultaneously;

[0010] (2) To conduct a matching switch assessment on the anti-spike surge optoelectronic isolator, and take turns to turn on and off to complete the switch function to drive the load.

[0011] (3) Design an intuitive observation in the reliability test circuit to screen for faults in the anti-spike surge optoelectronic isolator and immediately eliminate it.

[0012] (4) To conduct an assessment on the constant current capacity of the control end of the anti-spike surge optoelectronic isolator.

[0013] The inventive concept of the present utility model is:

[0014] (1)Input signal design

[0015] The input signal is designed as a square wave signal, and the frequency of the square wave signal is selected according to the actual aging requirements of the switching function.

[0016] (2)Amplification of input signal

[0017] According to the number of device units under test screened by the reliability test, the minimum input drive current is determined. The input signal is first amplified in voltage and then in current to meet the current requirements when screening the set number of units simultaneously in the reliability test.

[0018] (3)Overall aging test method for the control end and the backend of the optoelectronic isolator

[0019] According to the signal provided by the signal module, it enters the front control end of the optoelectronic isolator to work. The front control end stabilizes the voltage and filters the constant current of the input signal and then sends the stabilized signal into the optoelectronic isolator. The optoelectronic isolator controls the backend switch to drive the load to work according to the signal. The signal amplification circuit and the optoelectronic isolator are powered by mutually isolated power supplies.

[0020] (4)Aging status display method

[0021] When the isolator is conducting, at this time, the current in the load circuit flows, the isolator is in a low-resistance state, and the working indicator light goes out; when the isolator is turned off, at this time, the current in the load circuit stops flowing, the isolator is in a high-resistance state, and the working indicator light is on; by simulating the on and off display of the indicator light in the load module, an expected observable effect is achieved.

[0022] For this reason, a reliability test circuit for an anti-spike surge optoelectronic isolator is provided, as Figure 1 shown.

[0023] It includes a signal module, a signal amplification module, a control module, an output module, a load module, a display module, a power supply module VCC, and a power supply module VDD.

[0024] The signal module outputs a square wave signal to the signal amplification module, the signal amplification module outputs a signal to the control module, the control module outputs an optical signal to the output module, the output module outputs a load signal to the load module, the power supply module VCC supplies power to the signal module and the signal amplification module, the power supply module VDD provides power for the control module, the output module, the load module, and the display module, and the display module is connected to the output module and the load module to display the reliability test status of the optoelectronic isolator.

[0025] The signal module is a square wave signal generator.

[0026] When the isolator is conducting, it is in a low-resistance state and the working indicator light is off; when the isolator is off, it is in a high-resistance state and the working indicator light is on. By simulating the on / off display of the indicator light in the analog load module, an expected observable effect is achieved.

[0027] Advantages of the present utility model:

[0028] (1) It effectively replaces the reliability test method of step-by-step aging screening of traditional anti-spike surge optoelectronic isolators, simultaneously realizes the coordination and unity of power aging screening and dynamic switch aging screening, and realizes the aging screening method of the switch timing of the isolator.

[0029] (2) The reliability test circuit has functions of high-voltage protection, normal working indication, and constant current of the working circuit current, which is convenient for real-time monitoring of the screening situation.

[0030] (3) The reliability test circuit combined in series and parallel is adopted. Considering heat dissipation, wiring, and various usage conditions, the push-pull type reliability test aging board is designed as a double-layer wiring board.

[0031] The technical solution of the present utility model can be widely applied to the reliability test technology of optoelectronic isolators. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 It is a schematic structural diagram of the principle block diagram of the reliability test of the optoelectronic isolator.

[0033] Figure 2 It is a schematic structural diagram of the reliability test circuit of the optoelectronic isolator.

[0034] Figure 3 It is a schematic diagram of the working state of the circuit when the control signal is at a low level.

[0035] Figure 4 It is a schematic diagram of the working state of the circuit when the control signal is at a high level.

[0036] Figure 5 It is a schematic structural diagram of the reliability test circuit of a batch of optoelectronic isolators.

[0037] In the figure: Q1 is a PNP triode, Q2 and Q3 are NMOS field effect transistors, R1, R2, R3, and R4 are resistors, CRD1, CRD2, CRD3, and CRD4 are constant current tubes, D1, D2, D3, and D4 are light-emitting diodes, D5, D6, and D9 are Schottky diodes, D7, D8, and D10 are zener diodes, and C1 is a capacitor. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0038] As Figures 1 - 5As shown, for the reliability test circuit of the anti-spike surge opto-isolator, taking the reliability test circuit of the unit opto-isolator as an example, the specific implementation is as follows:

[0039] The reliability test circuit (unit circuit) of the opto-isolator includes:

[0040] A square wave signal generator, a PNP transistor Q1, NMOS field effect transistors Q2 and Q3, resistors R1, R2, R3, and R4, a constant current diode CRD1, a light emitting diode D1, Schottky diodes D5, D6, and D9, zener diodes D7, D8, and D10, a capacitor C1, a control module, an output module, a load, a DC voltage source VCC, and a DC voltage source VDD.

[0041] The power supply terminal of the square wave signal generator is connected to the emitter of Q1 and the DC voltage source VCC. The output terminal of the square wave signal generator is connected to one end of R5, one end of R4, the gate of Q2, and the cathode of D8. The anode of D8 is connected to the positive electrode of D9 and one end of C1. The ground terminal of the square wave signal generator is connected to the ground terminal of the DC voltage source VCC, the negative electrode of D9, the other end of C1, the positive electrode of D7, and the source of Q3.

[0042] The base of Q1 is connected to the negative electrode of D6. The positive electrode of D6 is connected to the other end of R5. The collector of Q1 is connected to the anode of D4. The cathode of D4 is connected to the other end of R4, the drain of Q2, and one end of R3. The other end of R3 is connected to one end of R2 and the cathode of D5. The anode of D5 is connected to the other end of R2, the negative electrode of D7, and the gate of Q3.

[0043] The drain of Q3 is the signal output terminal. The drain of Q3 is connected to the input terminal of the opto-isolator control module. The power supply terminal of the opto-isolator control module is connected to the power supply terminal of the opto-isolator output module and the anode of CRD1. The cathode of CRD1 is connected to the anode of D1. The cathode of D1 is connected to the output terminal of the opto-isolator output module and one end of the load. The other end of the load is connected to the ground terminal of the DC voltage source VDD.

[0044] Q1, Q2, Q3, R1, R2, R3, R4, D5, D6, D9, D7, D8, D10, C1, and VCC form an input signal amplification circuit.

[0045] The control module and the output module form an opto-isolator.

[0046] The opto-isolator, CRD1, and D1 form an opto-isolator test circuit unit.

[0047] The working principle of the opto-isolator is as follows:

[0048] (1) When the PWM input is at a high level, the MOSFET driver conducts, setting the MOSFET gate voltage low. At this time, the MOSFET turns off, and no current flows through the signal terminal of the anti-spike surge opto-isolator. At this time, the opto-isolator is in a high-impedance off state.

[0049] (1) When the PWM input is at a low level, the MOSFET driver turns off, and the signal power supply supplies power to the MOSFET gate. At this time, the MOSFET turns on, and current flows through the signal terminal of the anti-spike surge opto-isolator. At this time, the opto-isolator is in a low-impedance on state.

[0050] As Figure 2 shown, the working principle of the reliability test circuit is as follows:

[0051] The signal generator generates high and low level signals to control the switches of the triode Q1 and the small-power MOSFET Q2, that is, when the triode Q1 turns on, the MOSFET Q2 turns off, and when the triode Q1 turns off, the MOSFET Q2 turns on. By controlling the charging and discharging of the gate of the high-power MOSFET Q3 to control the switch of Q2, the purpose of controlling the opto-isolator is achieved, meeting the aging requirements.

[0052] As Figure 3 shown, when the control signal is at a low level, the working state of the reliability test circuit is as follows:

[0053] When the signal generator outputs a low level, analyze the working states of Q1, Q2, Q3, and the opto-isolator in the circuit.

[0054] A. Working state of Q1

[0055] When the signal generator outputs a low level, for Q1, there is a voltage difference close to VCC between VCC and the output terminal of the signal generator (the breakdown voltage requirement of the D6 tube in the circuit design is slightly lower than VCC, usually 1V - 2V). At this time, the D6 tube is in a reverse breakdown state, and the current path of I IN1 is established. The direction of the I IN1 current is as Figure 2 shown, from VCC → the emitter of Q1 → the base of Q1 → D6 (reverse breakdown) → R5 → the signal generator → ground. At this time, the triode Q1 is in an on state.

[0056] B. Working state of Q2

[0057] When the signal generator outputs a low level, there is no voltage difference between the gate and source of Q2. Therefore, Q2 is in an off state.

[0058] C. Working state of Q3

[0059] When Q1 is on and Q2 is off, the current path of I IN2 is established. The I IN2The current passes through VCC → Q1 → D4 → R3 → R2 → the gate of Q2, I IN2 Charges the gate of Q3 to control Q3 to conduct. At this time, the MOSFET Q3 is in the on state.

[0060] D. Operating state of the opto-isolator

[0061] According to the above analysis of the operating state of Q3, Q3 is in the on state at this time. After Q3 is turned on, I O The current path is established, I O The current flows as Figure 2 , from VDD → the control module in the opto-isolator → the drain of Q3 → the source of Q3 → ground. At this time, the control module of the opto-isolator is turned on.

[0062] After the control module of the opto-isolator is turned on, it controls the output module to turn on. At this time, I OUT The path is established, I OUT The current flows from VDD → the output module in the opto-isolator → the load → ground. At this time, the control module in the opto-isolator is in a low-resistance state, and the voltage across it is relatively low, unable to drive the constant current tube and the light-emitting diode connected in parallel to work, resulting in the light-emitting diode not emitting light.

[0063] The circuit logic table is shown in Table 1:

[0064] Table 1 Circuit logic table for low-level signals

[0065] Signal generator Q1 Q2 Q3 Optical isolator (control module) Optical isolator (output module) Light - emitting diode Low level Turn on Turn off Turn on Turn on Turn on Do not emit light

[0066] As Figure 4 shown, when the control signal is at a high level, the operating state of the reliability test circuit is as follows:

[0067] When the signal generator outputs a high level, analyze the operating states of Q1, Q2, Q3, and the opto-isolator.

[0068] A. Operating state of Q1

[0069] When the signal generator outputs a high level, there is no voltage difference between VCC and the output terminal of the signal generator (the breakdown voltage requirement of the D6 tube in the circuit design is slightly lower than the voltage of VCC, usually 1V - 2V), D6 is in the reverse-off state, and there is no current flowing between the emitter and the base of Q1, controlling Q1 to be in the off state.

[0070] B. Operating state of Q2

[0071] When the signal generator outputs a high level, there is a voltage difference between the gate and the source of the MOSFET Q2, and Q2 is in the on state.

[0072] C. Operating state of Q3

[0073] When Q1 is turned on and Q2 is turned off, I O1 the current path is established, and I O1 the current flows as Figure 3 , from the gate of Q2 → D5 → R3 → Q3 → D9 → ground. Through I O1 the gate capacitance of Q2 is discharged, thereby changing the state of Q2 from the conducting state to the off state.

[0074] D. Operating state of the opto - isolator

[0075] According to the above analysis of the operating state of Q3, at this time Q3 is in the off state. After Q3 is turned off, I O the current channel is closed, resulting in the closing of the control module of the opto - isolator.

[0076] After the control module of the opto - isolator is closed, the control output module is closed, and I OUT the current flows from VDD → constant - current tube → light - emitting diode → load → ground. The light - emitting diode emits light by passing current.

[0077] The circuit logic table is shown in Table 2:

[0078] Table 2 Circuit logic table for high - level signal

[0079] Signal generator Q1 Q2 Q3 Optical isolator (control module) Optical isolator (output module) Light - emitting diode High level Turn off Turn on Turn off Turn off Turn off Emit light

[0080] In summary, the operating - state logic table of the reliability test circuit is shown in Table 3:

[0081] Table 3 Operating - state logic table

[0082] Signal generator Q1 Q2 Q3 Optical isolator (control module) Optical isolator (output module) Light - emitting diode Low level Turn on Turn off Turn on Turn on Turn on Do not emit light High level Turn off Turn on Turn off Turn off Turn off Emit light

[0083] As Figure 5 shown, by connecting multiple opto - isolator test - circuit units in series or parallel into the circuit, the purpose of batch reliability testing of opto - isolators can be achieved, improving production efficiency.

[0084] Finally, it should be noted that: the above embodiments are merely examples given for clear illustration. The present utility model includes but is not limited to the above embodiments, and it is not necessary and impossible to enumerate all implementation manners here. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. All implementation manners that meet the requirements of the present utility model fall within the protection scope of the present utility model.

Claims

1. A reliability test circuit for an anti-spike surge photoelectric isolator, characterized in that: Including signal module, signal amplification module, control module, output module, load module, display module, power module VCC, power module VDD; The output end of the signal module is connected to the input end of the signal amplifying module, the output end of the signal amplifying module is connected to the input end of the control module, the output end of the control module is optically connected to the input end of the output module, the output end of the output module is connected to the load module, the power module VCC is connected to the power supply ends of the signal module and the signal amplifying module, the power module VDD is connected to the power supply ends of the control module, the output module, the load module and the display module, and the display module is connected to the output module and the load module.

2. The reliability test circuit of an anti-spike surge photoelectric isolator according to claim 1, characterized in that: The signal amplification module includes Q1, Q2, Q3, R1, R2, R3, R4, D5, D6, D9, D7, D8, D10, C1, and VCC; The signal module is a square wave signal generator, the power supply end of the square wave signal generator is connected to the emitter of Q1 and the DC voltage source VCC, the output end of the square wave signal generator is connected to one end of R5, one end of R4, the gate of Q2, and the cathode of D8, the anode of D8 is connected to the positive electrode of D9 and one end of C1, and the ground end of the square wave signal generator is connected to the ground end of the DC voltage source VCC, the negative electrode of D9, the other end of C1, the positive electrode of D7, and the source of Q3; The base of Q1 is connected to the negative electrode of D6, the positive electrode of D6 is connected to the other end of R5, the collector of Q1 is connected to the anode of D4, the cathode of D4 is connected to the other end of R4, the drain of Q2, and one end of R3, the other end of R3 is connected to one end of R2 and the cathode of D5, and the anode of D5 is connected to the other end of R2, the negative electrode of D7, and the gate of Q3; The drain of Q3 is a signal output terminal.

3. The reliability test circuit of an anti-spike surge photoelectric isolator according to claim 2, characterized in that: The control module and the output module form a photoelectric isolator, and the photoelectric isolator, CRD1 and D1 form a photoelectric isolator test circuit unit; The power supply end of the photoelectric isolator control module is connected to the power supply end of the photoelectric isolator output module and the anode of CRD1, the cathode of CRD1 is connected to the anode of D1, and the cathode of D1 is connected to the output end of the photoelectric isolator output module.

4. The reliability test circuit of an anti-spike surge photoelectric isolator according to claim 3, characterized in that: Connect two or more photoelectric isolator test circuit units in series or in parallel into the reliability test circuit.

5. The reliability test circuit of an anti-spike surge photoelectric isolator according to claim 1, characterized in that: The test circuit comprises: Square wave signal generator, PNP transistor Q1, NMOS field effect transistors Q2, Q3, resistors R1, R2, R3, R4, constant current tube CRD1, light emitting diode D1, Schottky diodes D5, D6, D9, voltage regulator diodes D7, D8, D10, capacitor C1, control module, output module, load, DC voltage source VCC, DC voltage source VDD; The power supply end of the square wave signal generator is connected to the emitter of Q1 and the DC voltage source VCC, the power supply end output end of the square wave signal generator is connected to one end of R5, one end of R4, the gate of Q2, and the cathode of D8, the anode of D8 is connected to the positive electrode of D9 and one end of C1, and the ground end of the square wave signal generator is connected to the ground end of the DC voltage source VCC, the negative electrode of D9, the other end of C1, the positive electrode of D7, and the source of Q3; The base of Q1 is connected to the negative electrode of D6, the positive electrode of D6 is connected to the other end of R5, the collector of Q1 is connected to the anode of D4, the cathode of D4 is connected to the other end of R4, the drain of Q2, and one end of R3, the other end of R3 is connected to one end of R2 and the cathode of D5, and the anode of D5 is connected to the other end of R2, the negative electrode of D7, and the gate of Q3; The drain of Q3 is connected to the input end of the photoelectric isolator control module, the power end of the photoelectric isolator control module is connected to the power end of the photoelectric isolator output module and the anode of CRD1, the cathode of CRD1 is connected to the anode of D1, the cathode of D1 is connected to the output end of the photoelectric isolator output module and one end of the load, and the other end of the load is connected to the ground end of the DC voltage source VDD.

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