Sensor circuit

Abstract

The utility model provides a sensor circuit. The sensor circuit comprises a pixel array unit and a delay compensation unit, and the pixel array unit comprises N pixels and N first OR gates corresponding to the N pixels respectively; the delay compensation unit comprises N third delay units which are connected in series, a one-out-of-N multiplexer and a gating unit, and the output end of the gating unit is connected to the gating signal input end of the one-out-of-N multiplexer so as to be used for outputting gating signals to control the one-out-of-N multiplexer to gate the corresponding input end for output; each of the N first OR gates has a first delay, each of the N third delay units has a third delay, the third delay is the same as the first delay, and N is an integer greater than 1.

Description

Technical Field

[0001] The present disclosure relates to the field of three-dimensional depth sensing, and more particularly, to a sensor circuit, method, and system capable of performing delay compensation. Background Art

[0002] A direct time-of-flight (DToF) sensor is an active optical sensor that includes at least two main parts: a transmitting end Tx and a receiving end Rx. The transmitting end Tx emits short-pulse lasers, which irradiate the object to be measured, and part of the lasers are received by the receiving end Rx after reflection. Since there is a synchronization signal between Tx and Rx, the control circuit can record the time t for the laser to fly back and forth in the air. Given the speed of light C, the distance d of the object to be measured can be obtained as d = 1 / 2 * C * t. For a matrix DToF chip, the number of pixels is relatively large. To save the chip area and power consumption, generally, a time-to-digital converter (TDC) sharing technology can be adopted, that is, multiple pixels (e.g., SPAD pixels) can share a TDC time-divisionally, as Figure 1 shown. Taking pixel A and pixel B as examples, at the same distance from the object to be measured, the flight time of photons is the same, but due to the existence of transmission delay, the time (e.g., t1 and t2) for pixels at different positions on the array to reach the same or different TDCs may have deviations, resulting in deviations in the measured distance. Currently, generally, external calibration is used to reduce the deviation, but this solution may bring additional calibration costs and is sensitive to process, power supply, and temperature deviations. Even after calibration, there may still be a certain amount of error remaining. Therefore, a sensor circuit with strong robustness and capable of effectively performing delay compensation is needed. Summary of the Utility Model

[0003] Embodiments of the present disclosure provide a sensor circuit, characterized in that the sensor circuit includes a pixel array unit and a delay compensation unit. Among them, the pixel array unit includes N pixels and N first OR gates respectively corresponding to each of the N pixels. Among them, the output signal of each pixel in the N pixels is output to the first input end of the first OR gate corresponding to the pixel. The output ends of the first to the (N - 1)th first OR gates are respectively connected to the second input ends of the next first OR gate, and the output end of the Nth first OR gate is connected to the input end of the delay compensation unit; and the delay compensation unit includes N third delay units connected in series, a 1-of-N multiplexer, and a strobe unit. Among them, the output end of each of the N third delay units is also respectively connected to the N input ends of the 1-of-N multiplexer. The output end of the strobe unit is connected to the strobe signal input end of the 1-of-N multiplexer to output a strobe signal for controlling the 1-of-N multiplexer to select and output the corresponding input end. Among them, each of the N first OR gates has a first delay, each of the N third delay units has a third delay, and the third delay is the same as the first delay, where N is an integer greater than 1.

[0004] According to an embodiment of the present disclosure, the sensor circuit further includes a delay locked loop unit. Among them, the output end of the delay locked loop unit is connected to the bias input end of each of the N third delay units for outputting a bias signal to control the delay of each of the N third delay units.

[0005] According to an embodiment of the present disclosure, the delay locked loop unit includes N second OR gates, N second delay units connected in series, and a bias unit. Among them, the first clock signal is input to the first input end of the first second OR gate. The output ends of the first to the (N - 1)th second OR gates are respectively connected to the second input ends of the next second OR gate, and the output end of the Nth second OR gate is connected to the first input end of the bias unit; the second clock signal is input to the input end of the first second delay unit. The output ends of the first to the (N - 1)th second delay units are respectively connected to the input ends of the next second delay unit, and the output end of the Nth second delay unit is connected to the second input end of the bias unit; the bias unit detects the first input signal input through the first input end and the second input signal input through the second input end to generate a bias signal corresponding to the delay between the first input signal and the second input signal. Among them, the bias signal is output through the output end of the delay locked loop unit. Among them, the output end of the delay locked loop unit is also connected to the bias input end of each of the N second delay units for outputting the bias signal to control the delay of each of the N second delay units.

[0006] According to an embodiment of the present disclosure, the bias unit includes a delay detection unit, a voltage conversion unit, and a loop filter. Wherein, a first input end and a second input end of the delay detection unit are respectively a first input end and a second input end of the bias unit, and are configured to detect a delay between the first input signal and the second input signal and output a delay signal corresponding to the delay; an input end of the voltage conversion unit is connected to an output end of the delay detection unit, and is configured to convert the delay signal into a delay voltage signal corresponding to the delay signal; an input end of the loop filter is connected to an output end of the voltage conversion unit, and is configured to filter the delay voltage signal to output the bias signal.

[0007] According to an embodiment of the present disclosure, each of the N second OR gates has a fourth delay, and the fourth delay is the same as the first delay.

[0008] According to an embodiment of the present disclosure, the first clock signal and the second clock signal have the same frequency and phase.

[0009] According to an embodiment of the present disclosure, the delay detection unit is a phase detector, and the phase detector is configured to detect a phase difference between the first input signal and the second input signal, wherein the delay is determined based on the phase difference.

[0010] According to an embodiment of the present disclosure, the sensor circuit further includes a time-to-digital conversion unit, wherein an input end of the time-to-digital conversion unit is connected to an output end of the 1-of-N multiplexer, and the time-to-digital conversion unit is configured to measure a time difference associated with the signal based on the signal output from the output end of the 1-of-N multiplexer.

[0011] According to an embodiment of the present disclosure, the first input ends of the second to the Nth second OR gates among the N second OR gates are left open.

[0012] According to an embodiment of the present disclosure, when the i-th pixel is turned on, the strobe signal controls the 1-of-N multiplexer to select and output the i-th input end, where i is greater than or equal to 1 and less than or equal to N.

[0013] Embodiments of the present disclosure can provide a sensor circuit with strong robustness and capable of effectively compensating for delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] From the following description in conjunction with the accompanying drawings, the above and other aspects, features, and advantages of certain embodiments of the present disclosure will become more apparent, wherein:

[0015] Figure 1Shows a schematic diagram of the propagation delay occurring between different pixels in a pixel array according to an embodiment of the present disclosure;

[0016] Figure 2 Shows a schematic diagram of a sensor circuit capable of performing delay compensation according to an embodiment of the present disclosure;

[0017] Figure 3 Shows a schematic diagram of a sensor circuit capable of performing delay compensation according to an embodiment of the present disclosure; and

[0018] Figure 4 Shows a schematic diagram of the delay compensation of a pixel output signal through a sensor circuit according to an embodiment of the present disclosure. Detailed implementation

[0019] Before proceeding with the following detailed description, it may be advantageous to set forth the definitions of certain words and phrases used throughout this patent document. The terms "coupled", "connected" and their derivatives refer to any direct or indirect communication or connection between two or more elements, whether or not those elements are in physical contact with each other. The terms "transmit", "receive" and "communicate" and their derivatives cover both direct and indirect communication. The terms "comprise" and "include" and their derivatives mean including but not limited to. The term "or" is inclusive, meaning and / or. The phrases "associated with", "corresponding to" and their derivatives mean including, included within, interconnected, containing, contained within, connected or coupled to, communicating with, cooperating with, interwoven with, juxtaposed, adjacent to, bound or bound to, having, having an attribute, having a relationship or having a relationship with, etc. The term "controller" refers to any device, system or part thereof that controls at least one operation. Such a controller may be implemented in hardware, or in a combination of hardware and software and / or firmware. The functions associated with any particular controller may be centralized or distributed, whether local or remote. The phrase "at least one", when used in conjunction with a list of items, means that different combinations of one or more of the listed items may be used, and only one item from the list may be required. For example, "at least one of A, B, C" includes any one of the following combinations: A, B, C, A and B, A and C, B and C, A and B and C.

[0020] Definitions of other specific words and phrases are provided throughout this patent document. Those of ordinary skill in the art should understand that in many cases, if not most cases, such definitions apply to the prior and future use of the words and phrases so defined.

[0021] In this patent document, the application combinations of modules and the hierarchical divisions of sub-modules are only for illustration. Without departing from the scope of the present disclosure, the application combinations of modules and the hierarchical divisions of sub-modules can have different forms. Embodiments of the present disclosure can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that the present disclosure is thorough and complete, and will fully convey exemplary implementation manners to those skilled in the art. Embodiments of the present disclosure can be combined to form additional embodiments.

[0022] The present disclosure will be described in detail below with reference to exemplary embodiments of the present disclosure. However, the present disclosure is not limited to the embodiments described herein and can be implemented in many different forms. The described embodiments are only for making the present disclosure thorough and complete, and fully conveying the concept of the present disclosure to those skilled in the art. The features of the described embodiments can be combined with each other or replaced, unless explicitly excluded or should be excluded according to the context.

[0023] Figure 2 A schematic diagram of a sensor circuit 200 capable of performing delay compensation according to an embodiment of the present disclosure is shown.

[0024] As Figure 2 shown, the sensor circuit 200 according to an embodiment of the present disclosure may include a pixel array unit 210 and a delay compensation unit 220. In some embodiments, the pixel array unit 210 may include a plurality of pixels (e.g., SPAD pixels) and a plurality of first OR gates respectively corresponding to each of the plurality of pixels. For example, the pixel array unit 210 may include N pixels and N first OR gates respectively corresponding to each of the N pixels, where N may be an integer greater than 1. In some embodiments, the N pixels may share or multiplex the same TDC for time measurement. The output of each pixel may be connected in series through a corresponding OR gate. Hereinafter, an exemplary description will be given with N = 8 as an example. For example, the pixel array unit 210 may include 8 pixels Pixel_0, Pixel_1,..., Pixel_7 and 8 first OR gates OR0, OR1,..., OR7.

[0025] In some embodiments, the output signal of each of the 8 pixels may be output to the first input terminal of the first OR gate corresponding to the pixel. The output terminals of the 1st to 7th first OR gates may be respectively connected to the second input terminals of the next first OR gate, and the output terminal of the 8th first OR gate may be connected to the input terminal of the delay compensation unit 220.

[0026] For example, as Figure 2As shown, the output signals Pixel_0_out to Pixel_7_out of the eight pixels Pixel_0 to Pixel_7 can be respectively output to the first input terminals IN_1 of the first OR gates OR0 to OR7 corresponding to the pixels Pixel_0 to Pixel_7 respectively. The output terminal of the first OR gate OR0 can be connected to the second input terminal IN_2 of the second OR gate OR1, the output terminal of the second OR gate OR1 can be connected to the second input terminal IN_2 of the third OR gate OR2, and so on. And the output terminal of the eighth OR gate OR7 can be connected to the input terminal of the delay compensation unit 220 (for example, it can be the input terminal of the first third delay unit D0 included in the delay compensation unit 220 as described below).

[0027] In some embodiments, the delay compensation unit 220 may include eight third delay units D0 to D7, an 8-to-1 multiplexer MUX, and a gating unit 221. As Figure 2 shown, the eight third delay units D0 to D7 can be serially connected in sequence to form a delay chain 222 (which can be referred to as the third delay chain herein).

[0028] The 8-to-1 multiplexer MUX can be any device having eight input terminals, one output terminal, and one gating signal input terminal, and it can, under the control of the gating signal S1 input through the gating signal input terminal, select one of the eight input terminals and output it from the output terminal. Herein, the 8-to-1 multiplexer MUX can also be referred to as a delay selector.

[0029] As Figure 2 shown, the output terminals of each of the eight third delay units D0 to D7 can also be respectively connected to the eight input terminals of the 8-to-1 multiplexer MUX, and the output terminal of the gating unit 221 can be connected to the gating signal input terminal of the 8-to-1 multiplexer MUX to output a gating signal S1 to control the 8-to-1 multiplexer MUX to select the corresponding input terminal for output. For example, the output selection of the 8-to-1 multiplexer MUX can be determined based on the currently turned-on pixels.

[0030] In some embodiments, each of the eight first OR gates may have a first delay Delay1, each of the eight third delay units may have a third delay Delay3, and the third delay Delay3 may be the same as the first delay Delay1. In some embodiments, each of the third delay units may be a buffer, an inverter, or any other electronic device having a third delay Delay3. In some embodiments, each of the third delay units may also be an OR gate that is exactly the same as the first OR gate.

[0031] In some embodiments, the strobe unit 221 may output a strobe signal S1 based on the on-states of 8 pixels. For example, when the i-th pixel is on, the strobe unit 221 may output a strobe signal S1 that enables the N-to-1 multiplexer MUX to select the i-th input terminal for output, where i is greater than or equal to 1 and less than or equal to N.

[0032] Table 1 Corresponding relationship between turned-on pixels and outputs of the delay selector

[0033] Turn on pixel Output corresponding to delay selector Pixel_0 DLY0 Pixel_1 DLY1 Pixel_2 DLY2 Pixel_3 DLY3 Pixel_4 DLY4 Pixel_5 DLY5 Pixel_6 DLY6 Pixel_7 DLY7

[0034] Take Figure 2 as an example. When the pixel Pixel_0 is turned on, the pulse signal generated by pixel breakdown (e.g., the pixel Pixel_0 receives the returned photons) needs to pass through the delays of 8 first OR gates to be transmitted out of the pixel array unit 210, and the corresponding delay is: 8×Delay1. In this case, corresponding to Table 1, the DLY0 can be selected as the output of the 8-to-1 multiplexer MUX by the strobe signal S1 and passed to the subsequent processing unit (e.g., TDC). At this time, the pulse signal needs to pass through 1 third delay unit and 1 8-to-1 multiplexer MUX. Assuming that the delay of the pulse signal passing through 1 8-to-1 multiplexer MUX is a fixed delay MUX Delay, for the turn-on of the pixel Pixel_0, the total propagation delay of the pulse signal is T0, as shown in the following equation (1):

[0035] T0 = 8×Delay1 + Delay3 + MUX Delay (1)

[0036] When the pixel Pixel_3 is turned on, the pulse signal generated by pixel breakdown (e.g., the pixel Pixel_3 receives the returned photons) needs to pass through the delays of 5 first OR gates to be transmitted out of the pixel array unit 210, and the corresponding delay is: 5×Delay1. In this case, corresponding to Table 1, the DLY3 can be selected as the output of the 8-to-1 multiplexer MUX by the strobe signal S1 and passed to the subsequent processing unit (e.g., TDC). At this time, the pulse signal needs to pass through 4 third delay units and 1 8-to-1 multiplexer MUX. Assuming that the delay of the pulse signal passing through 1 8-to-1 multiplexer MUX is a fixed delay MUX Delay, for the turn-on of the pixel Pixel_3, the total propagation delay of the pulse signal is T3, as shown in the following equation (2):

[0037] T3 = 5×Delay1 + 4×Delay3 + MUX Delay (2)

[0038] And so on. When the third delay Delay3 of the selected third delay unit is the same as the first delay Delay1 of the first OR gate, the following equation (3) can be obtained:

[0039] T0 = T1 = … = T7(3)

[0040] That is, when all pixels are turned on, the total propagation delay of the pulse signal is the same. Thus, the performance of the DToF chip can be guaranteed without external calibration.

[0041] Figure 3 FIG. shows a schematic diagram of a sensor circuit 300 capable of delay compensation according to an embodiment of the present disclosure. Figure 3 The same parts as in Figure 2 will not be described again.

[0042] As Figure 3 shown, compared with the sensor circuit 200, the sensor circuit 300 according to an embodiment of the present disclosure may further include a delay locked loop unit 230. In some embodiments, the delay locked loop unit 230 may be a Delay lock loop (DLL) structure. In some embodiments, the output end of the delay locked loop unit 230 may be connected to the bias input end of each of the eight third delay units D0 to D7, for outputting a bias signal S2 to control the delay of each of the eight third delay units.

[0043] In some embodiments, the delay locked loop unit 230 may include eight second OR gates OR0' to OR7', eight second delay units D0' to D7' and a bias unit 310, the number of which is the same as that of the first OR gates.

[0044] The connection manner or circuit layout of the eight second OR gates OR0' to OR7' may be exactly the same as that of the eight first OR gates OR0 to OR7 in the pixel array unit 210 described above, so as to form a delay link 320 (which may be referred to as the first delay link herein). Each of the eight second OR gates OR0' to OR7' may have the same delay Delay1 as each of the eight first OR gates OR0 to OR7.

[0045] Similarly, the connection manner or circuit layout of the eight second delay units D0' to D7' may be exactly the same as that of the eight third delay units D0 to D7 in the pixel array unit 210 described above, so as to form a delay link 330 (which may be referred to as the second delay link herein).

[0046] In some embodiments, the first clock signal CLK1 may be input to the first input terminal IN_1 of the first second OR gate OR0', the output terminals of the first to seventh second OR gates OR0' to OR6' may be respectively connected to the second input terminal IN_2 of the next second OR gate, and the output terminal of the eighth second OR gate OR7' may be connected to the first input terminal IN_1 of the bias unit 310.

[0047] In some embodiments, the first input terminals IN_1 of the second to eighth second OR gates among the eight second OR gates may be left open or connected to any other suitable voltage signal. In some embodiments, the second input terminal IN_2 of the first second OR gate OR0' may be grounded or connected to any other suitable voltage signal. In some embodiments, the second input terminal IN_2 of the first first OR gate OR0 may be grounded or connected to any other suitable voltage signal.

[0048] In some embodiments, the second clock signal CLK2 may be input to the input terminal of the first second delay unit D0', the output terminals of the first to seventh second delay units D0' to D6' may be respectively connected to the input terminal of the next second delay unit, and the output terminal of the eighth second delay unit D7' may be connected to the second input terminal IN_2 of the bias unit 310.

[0049] In some embodiments, for facilitating the measurement of the delays of the delay link 320 and the delay link 330 (or the delays of the respective delay units in the links) by the delay lock loop unit 230, the first clock signal CLK1 and the second clock signal CLK2 may be signals having the same frequency and phase through specific constraints (e.g., the same signal generated and output via a specific signal generator).

[0050] The bias unit 310 may detect the first input signal input through the first input terminal IN_1 and the second input signal input through the second input terminal IN_2 to generate a bias signal S2 corresponding to the delay between the first input signal and the second input signal. The bias signal S2 may be output through the output terminal of the delay lock loop unit 230 (i.e., the output terminal of the bias unit 310).

[0051] In some embodiments, in addition to being connected to the bias input terminals of each of the eight third delay units D0 to D7, the output terminal of the delay lock loop unit 230 may also be connected to the bias input terminals of each of the eight second delay units D0' to D7' for outputting the bias signal S2 to control the delay of each of the eight second delay units.

[0052] Furthermore, as Figure 3As shown, the bias unit 310 may further include a delay detection unit 311, a voltage conversion unit 312, and a loop filter 313.

[0053] In some embodiments, the first input terminal and the second input terminal of the delay detection unit 311 may be the first input terminal IN_2 and the second input terminal IN_2 of the bias unit 310 respectively, and the delay detection unit 311 may be configured to detect the delay between the first input signal and the second input signal and output a delay signal corresponding to the delay. In some embodiments, the delay detection unit 311 may be a phase frequency detector, a phase detector, or any other device capable of detecting the phase difference and / or frequency difference of input signals.

[0054] For example, in the case where the delay detection unit 311 is a phase detector, the phase detector may be configured to detect the phase difference between the first input signal and the second input signal. Thereafter, the delay between the first input signal and the second input signal may be determined based on the phase difference.

[0055] The input terminal of the voltage conversion unit 312 may be connected to the output terminal of the delay detection unit 311, and may be configured to convert the delay signal output from the delay detection unit 311 into a delay voltage signal corresponding to the delay signal. In some embodiments, the voltage conversion unit 312 may be implemented by a charge pump or any other device capable of implementing the corresponding voltage conversion function.

[0056] The input terminal of the loop filter 313 may be connected to the output terminal of the voltage conversion unit 312, and may be configured to filter the delay voltage signal output from the voltage conversion unit 312 to output a bias signal S2.

[0057] Each of the eight second delay units D0' to D7' may have a second delay Delay2. As described above, in the embodiment as Figure 3 shown, the delay locked loop unit 230 may measure the delay between the delay link 320 and the delay link 330, so as to output a corresponding bias signal to continuously adjust the delay of the delay link 330 (and each second delay unit therein). When, after continuous adjustment, the delay locked loop unit 230 detects that the delay between the delay link 320 and the delay link 330 is 0, the output signal at this time may be output as the final bias signal S2. At this time, Delay2 = Delay1. The delay locked loop unit 230 according to the embodiments of the present disclosure may have improved characteristics such as resistance to process, power supply, and temperature deviation.

[0058] Since each of the second delay units D0' to D7' can be an identical delay unit to each of the third delay units D0 to D7, and the second delay units D0' to D7' and the third delay units D0 to D7 share the same bias voltage (e.g., bias signal S2), thus, through the adjustment of the delay locked loop unit 230, Delay3 = Delay2 = Delay1 can be obtained.

[0059] At this time, as described above, when all pixels are turned on, the total propagation delays that the pulse signal passes through are the same. Thereby, the performance of the DToF chip can be guaranteed without external calibration. In addition, since the delay locked loop unit 230 itself has characteristics such as resistance to process, power supply, and temperature deviations, a more robust sensor circuit capable of effectively compensating for delays can be provided.

[0060] In some embodiments, the sensor circuit 200 or 300 may further include a time-to-digital conversion unit (e.g., TDC) 314. The input end of the time-to-digital conversion unit 314 may be connected to the output end of the 1-of-8 multiplexer MUX, and the time-to-digital conversion unit 314 may be configured to measure the time difference associated with the signal based on the signal output from the output end of the 1-of-8 multiplexer MUX, so as to implement the distance measurement of the object to be measured.

[0061] Figure 4 A schematic diagram showing the delay compensation of the pixel output signal through the sensor circuit according to an embodiment of the present disclosure is shown.

[0062] Specifically, Figure 4 A schematic diagram showing the delay alignment of the output signals of pixel Pixel_0 and pixel Pixel_3 is shown. As Figure 4As shown, when pixel Pixel_0 is turned on, the output signal Pixel_0_out of pixel Pixel_0 can reach the TDC after passing through the delays of 8 first OR gates, 1 third delay unit, and 1 8-to-1 multiplexer MUX. That is, when pixel Pixel_0 is turned on, the delay of the input signal TDC_in0 of the TDC compared to the output signal Pixel_0_out of pixel Pixel_0 is T0 = 8×Delay1 + Delay3 + MUX Delay. When pixel Pixel_3 is turned on, the output signal Pixel_3_out of pixel Pixel_3 can reach the TDC after passing through the delays of 5 first OR gates, 4 third delay units, and 1 8-to-1 multiplexer MUX. That is, when pixel Pixel_3 is turned on, the delay of the input signal TDC_in3 of the TDC compared to the output signal Pixel_3_out of pixel Pixel_3 is T3 = 5×Delay1 + 4×Delay3 + MUX Delay. When the third delay Delay3 of the third delay unit is the same as the first delay Delay1 of the first OR gate, T0 = T3, that is, the delays of the output signals of different pixels reaching the TDC are the same.

[0063] It should be understood that the sensor circuits 200 or 300 described above are merely illustrative. The sensor circuits according to the embodiments of the present disclosure may further include one or more any other devices in addition to those included in the sensor circuits 200 or 300, or omit or replace any one or more devices in the sensor circuits 200 or 300, which are not limited herein. In addition, the embodiments of the present disclosure may also include any implementation method or operation method of the sensor circuits 200 or 300 described above, as well as any circuit system including the sensor circuits 200 or 300.

[0064] The whole or its components of the hardware computing device described in the present disclosure can be implemented by various suitable hardware means, including but not limited to FPGA, ASIC, SoC, discrete gate or transistor logic, discrete hardware components, or any combination thereof.

[0065] The block diagrams of the circuits, devices, apparatuses, equipment, and systems involved in the present disclosure are only exemplary examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these circuits, devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any way as long as the desired purpose can be achieved.

[0066] Although the present disclosure has been described with exemplary embodiments, various changes and modifications can be suggested to those skilled in the art. The present disclosure aims to cover such changes and modifications that fall within the scope of the appended claims.

[0067] None of the descriptions in this disclosure should be construed as implying that any particular element, step, or function is an essential element that must be included within the scope of the claims. The scope of the patent subject matter is defined only by the claims.

[0068] Exemplary embodiments in accordance with the present disclosure have been disclosed herein, and although specific terms are employed, they are used and interpreted in a general and descriptive sense only and not for purposes of limitation. In some instances, features, characteristics, and / or elements described in connection with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise specified. Accordingly, those skilled in the art will understand that various changes in form and detail may be made to the present disclosure without departing from the spirit and scope of the claims.

Claims

1. A sensor circuit, characterized in that: The sensor circuit includes a pixel array unit and a delay compensation unit, wherein: The pixel array unit includes N pixels and N first OR gates corresponding to each of the N pixels, wherein an output signal of each of the N pixels is output to a first input terminal of the first OR gate corresponding to the pixel, output terminals of the 1st to N-1th first OR gates are respectively connected to a second input terminal of a next first OR gate, and an output terminal of the Nth first OR gate is connected to an input terminal of the delay compensation unit; and The delay compensation unit comprises N third delay units connected in series, an N-to-1 multiplexer and a gating unit, wherein the output end of each of the N third delay units is also connected to the N input ends of the N-to-1 multiplexer respectively, and the output end of the gating unit is connected to the gating signal input end of the N-to-1 multiplexer for outputting a gating signal to control the N-to-1 multiplexer to gating the corresponding input end for output, Each of the N first OR gates has a first delay, each of the N third delay units has a third delay, and the third delay is the same as the first delay. Wherein, N is an integer greater than 1.

2. The sensor circuit according to claim 1, characterized in that: The sensor circuit further comprises a delay locked loop unit, wherein: The output terminal of the delay locked loop unit is connected to the bias input terminal of each of the N third delay units, and is used to output a bias signal to control the delay of each of the N third delay units.

3. The sensor circuit according to claim 2, characterized in that: The delay locked loop unit includes N second OR gates, N second delay units connected in series, and a bias unit, wherein: The first clock signal is input to the first input terminal of the 1st second OR gate, the output terminals of the 1st to N-1th second OR gates are respectively connected to the second input terminal of the next second OR gate, and the output terminal of the Nth second OR gate is connected to the first input terminal of the bias unit; The second clock signal is input to the input end of the first second delay unit, the output ends of the first to N-1 second delay units are respectively connected to the input end of the next second delay unit, and the output end of the Nth second delay unit is connected to the second input end of the bias unit; The bias unit detects a first input signal input through a first input terminal and a second input signal input through a second input terminal to generate a bias signal corresponding to a delay between the first input signal and the second input signal, wherein the bias signal is output through an output terminal of the delay locked loop unit, The output end of the delay locked loop unit is also connected to the bias input end of each of the N second delay units, for outputting the bias signal to control the delay of each of the N second delay units.

4. The sensor circuit according to claim 3, characterized in that: The bias unit includes a delay detection unit, a voltage conversion unit and a loop filter, wherein: The first input terminal and the second input terminal of the delay detection unit are respectively the first input terminal and the second input terminal of the bias unit, and are configured to detect a delay between the first input signal and the second input signal and output a delay signal corresponding to the delay; The input terminal of the voltage conversion unit is connected to the output terminal of the delay detection unit, and is configured to convert the delay signal into a delay voltage signal corresponding to the delay signal; An input terminal of the loop filter is connected to an output terminal of the voltage conversion unit, and is configured to filter the delayed voltage signal to output the bias signal.

5. The sensor circuit according to claim 3, characterized in that: Each of the N second OR gates has a fourth delay, and the fourth delay is the same as the first delay.

6. The sensor circuit according to claim 3, characterized in that: The first clock signal and the second clock signal have the same frequency and phase.

7. The sensor circuit according to claim 4, characterized in that: The delay detection unit is a phase detector configured to detect a phase difference between the first input signal and the second input signal, wherein the delay is determined based on the phase difference.

8. The sensor circuit according to claim 1, characterized in that: The sensor circuit further includes a time-to-digital conversion unit, wherein an input terminal of the time-to-digital conversion unit is connected to an output terminal of the N-to-1 multiplexer, and the time-to-digital conversion unit is configured to measure a time difference associated with the signal based on a signal output from the output terminal of the N-to-1 multiplexer.

9. The sensor circuit according to claim 3, characterized in that: The first input terminals of the 2nd to Nth second OR gates among the N second OR gates are set to empty.

10. The sensor circuit according to claim 1, characterized in that: When the i-th pixel is turned on, the selection signal controls the N-to-1 multiplexer to select the i-th input terminal for output, where i is greater than or equal to 1 and less than or equal to N.

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