Device structure including fan-out package

Abstract

A device structure including a fan-out package includes a mold compound die frame laterally surrounding at least one semiconductor die; and an organic interposer including a redistribution dielectric layer embedded with redistribution interconnect lines, and located on the first horizontal surface of the mold compound die frame. An alignment mark region including a locally recessed region is located within an opening in a second horizontal surface of the molding compound die frame. The local recessed region extends from the second horizontal surface toward the organic interposer.

Description

Technical Field

[0001] An embodiment of the present utility model relates to a device structure including a fan-out package. Background Art

[0002] It is desirable that the semiconductor die and the interposer vias structure can be precisely aligned to improve the yield and reliability of the package substrate. Summary of the Utility Model

[0003] An embodiment of the present utility model provides a device structure including a fan-out package. The fan-out package includes: a molded compound die frame that laterally surrounds at least one semiconductor die; and an organic interposer including a redistribution dielectric layer embedded with redistribution wiring interconnects and located on a first horizontal surface of the molded compound die frame. An alignment mark area including a local depression area is located within an opening in a second horizontal surface of the molded compound die frame.

[0004] An embodiment of the present utility model provides a device structure including: a fan-out package including a molded compound die frame, at least one semiconductor die laterally surrounded by the molded compound die frame, and an organic interposer including a redistribution dielectric layer embedded with redistribution wiring interconnects and located on a first horizontal surface of the molded compound die frame; and a package substrate, a bonding structure bonded to the organic interposer. An alignment mark area including a local depression area is located within an opening in a second horizontal surface of the molded compound die frame.

[0005] Based on the above, the present utility model relates to a device structure of a fan-out package. During pick-and-place operations, the alignment of at least one semiconductor die with an optional interposer via structure can be improved by using the alignment mark structure of the present utility model, and the process yield and reliability of the package substrate can be increased. Brief Description of the Drawings

[0006] Reading the following detailed description in conjunction with the drawings will best understand the various aspects of the present disclosure. It should be noted that, according to standard practices in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0007] Figure 1A is a top view of a first embodiment structure after forming an alignment mark structure in a first geometric arrangement form according to a first embodiment of the present disclosure.

[0008] Figure 1B is a top view of a first embodiment structure after forming an alignment mark structure in a second geometric arrangement form according to a first embodiment of the present disclosure.

[0009] Figure 1C isFigure 1A or Figure 1B A vertical cross - sectional view of the structure of the first embodiment. The alignment mark structure is only schematic, and the details of the alignment mark structure are not shown in Figure 1C it.

[0010] Figure 1D is Figure 1C A vertical cross - sectional view of a unit area with a first configuration of the structure of the first embodiment.

[0011] Figure 1E is Figure 1C A vertical cross - sectional view of a unit area with a second configuration of the structure of the first embodiment.

[0012] Figure 2 A vertical cross - sectional view of a unit area with a first configuration of the structure of the first embodiment after placing a semiconductor die and a through - interposer via (TIV) structure according to the first embodiment of the present disclosure.

[0013] Figure 3 A vertical cross - sectional view of a unit area with a first configuration of the structure of the first embodiment after forming a molded compound matrix according to the first embodiment of the present disclosure.

[0014] Figure 4 A vertical cross - sectional view of a unit area with a first configuration of the structure of the first embodiment after forming a redistribution structure according to the first embodiment of the present disclosure.

[0015] Figure 5 A vertical cross - sectional view of a unit area with a first configuration of the structure of the first embodiment after attaching a local interconnect die according to the first embodiment of the present disclosure.

[0016] Figure 6 A vertical cross - sectional view of a unit area with a first configuration of the structure of the first embodiment after partially attaching a solder material to a bonding structure according to the first embodiment of the present disclosure.

[0017] Figure 7 A vertical cross - sectional view of the structure of the first embodiment including a fan - out package according to the first embodiment of the present disclosure.

[0018] Figure 8 A vertical cross - sectional view of the structure of the first embodiment including an assembly composed of a fan - out package and a package substrate according to the first embodiment of the present disclosure.

[0019] Figure 9 A vertical cross - sectional view of the structure of the first embodiment after attaching an additional semiconductor die to the fan - out package according to the first embodiment of the present disclosure.

[0020] Figure 10is a vertical cross-sectional view of a first embodiment structure after a combination composed of a fan-out package, a package substrate, and an additional semiconductor die is attached to a printed circuit board according to a first embodiment of the present disclosure.

[0021] Figure 11 is a vertical cross-sectional view of a first alternative configuration of a first embodiment structure according to a first embodiment of the present disclosure.

[0022] Figure 12 is a vertical cross-sectional view of a second alternative configuration of a first embodiment structure according to a first embodiment of the present disclosure.

[0023] Figure 13 is a vertical cross-sectional view of a third alternative configuration of a first embodiment structure according to a first embodiment of the present disclosure.

[0024] Figure 14 is a vertical cross-sectional view of a second embodiment structure after a fan-out package is formed according to a second embodiment of the present disclosure.

[0025] Figure 15 is a vertical cross-sectional view of a second embodiment structure after a combination including a fan-out package, an additional semiconductor die, and a package substrate is formed according to a second embodiment of the present disclosure.

[0026] Figure 16 is a vertical cross-sectional view of a second embodiment structure after a cover structure is attached to the package substrate according to a second embodiment of the present disclosure.

[0027] Figure 17 is a vertical cross-sectional view of a second embodiment structure after a combination including a fan-out package, an additional semiconductor die, a package substrate, and a cover structure is attached to a printed circuit board according to a second embodiment of the present disclosure.

[0028] Figure 18 is a vertical cross-sectional view of an alternative configuration of a second embodiment structure according to a second embodiment of the present disclosure.

[0029] Figure 19 is a vertical cross-sectional view of a unit area of a third embodiment structure after an alignment mark structure and a die bonding film are formed according to a third embodiment of the present disclosure.

[0030] Figure 20 is a vertical cross-sectional view of a unit area of a third embodiment structure after a solder material portion is attached to a bonding structure according to a third embodiment of the present disclosure.

[0031] Figure 21 is a vertical cross-sectional view of a unit area of a third embodiment structure after a horizontal extension portion of the die bonding film is removed according to a third embodiment of the present disclosure.

[0032] Figure 22 is a vertical cross-sectional view of a third embodiment structure including a fan-out package according to the third embodiment of the present disclosure.

[0033] Figure 23 is a vertical cross-sectional view of a third embodiment structure according to the third embodiment of the present disclosure after attaching a fan-out package to a package substrate, attaching an additional semiconductor die to the package substrate, and attaching a combination formed by the fan-out package, the package substrate, and the additional semiconductor die to a printed circuit board.

[0034] Figure 24 is a vertical cross-sectional view of a first alternative configuration of a third embodiment structure according to the third embodiment of the present disclosure.

[0035] Figure 25 is a vertical cross-sectional view of a second alternative configuration of a third embodiment structure according to the third embodiment of the present disclosure.

[0036] Figure 26 is a vertical cross-sectional view of a third alternative configuration of a third embodiment structure according to the third embodiment of the present disclosure.

[0037] Figure 27 is a vertical cross-sectional view of a unit area of a fourth embodiment structure according to the fourth embodiment of the present disclosure after forming an alignment mark structure and a die bonding film.

[0038] Figure 28 is a vertical cross-sectional view of a unit area of a fourth embodiment structure according to the fourth embodiment of the present disclosure after attaching a solder material portion to a bonding structure.

[0039] Figure 29 is a vertical cross-sectional view of a fourth embodiment structure including a fan-out package according to the fourth embodiment of the present disclosure.

[0040] Figure 30 is a vertical cross-sectional view of a fourth embodiment structure according to the fourth embodiment of the present disclosure after removing the die bonding film and the alignment mark structure.

[0041] Figure 31 is a vertical cross-sectional view of a fourth embodiment structure according to the fourth embodiment of the present disclosure after attaching a fan-out package to a package substrate, attaching an additional semiconductor die to the package substrate, and attaching a combination formed by the fan-out package, the package substrate, and the additional semiconductor die to a printed circuit board.

[0042] Figure 32 is a vertical cross-sectional view of a first alternative configuration of a fourth embodiment structure according to the fourth embodiment of the present disclosure.

[0043] Figure 33A vertical cross-sectional view of a second alternative configuration of the fourth embodiment structure according to the fourth embodiment of the present disclosure.

[0044] Figure 34 A flowchart showing steps for forming a device structure according to an embodiment of the present disclosure. Detailed Description

[0045] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are set forth below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or above a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature, such that the first feature and the first feature may not be in direct contact.

[0046] In addition, for ease of description, spatially relative terms such as "beneath", "below", "lower", "above", "upper", and similar terms may be used herein to describe the relationship of one element or feature shown in the figures to another (other) element or feature. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or at other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly. Unless otherwise explicitly stated, each element having the same reference numeral is assumed to have the same material composition and a thickness within the same thickness range.

[0047] Various embodiments of the present disclosure use alignment mark structures formed on a carrier wafer to align semiconductor dies during a pick-and-placement operation. Some embodiments may additionally use a through-interposer via structure during the pick-and-placement operation, as appropriate. The alignment mark structures may include metallic structures or dielectric structures. A molded compound matrix may be formed around the semiconductor die and optionally the through-interposer via structure. In some embodiments, a die attach film may be provided between the alignment mark structures and the molded compound matrix. In some embodiments, the alignment mark structures may be removed after the carrier wafer is removed. A combination including the semiconductor die, optionally the through-interposer via structure, and the molded compound matrix forms a reconstructed wafer, which may be diced to provide a fan-out package. The fan-out package may be attached to a package substrate. In some embodiments, additional semiconductor dies and / or lid structures may be attached to the fan-out package or to the package substrate, as appropriate. During the pick-and-placement operation, alignment of at least one semiconductor die and the optional through-interposer via structure can be improved by using the alignment mark structures of the present disclosure, and the process yield and reliability of the package substrate can be increased. Various aspects of the present invention will now be described with reference to the accompanying drawings.

[0048] Referring to Figures 1A to 1C , a structure according to a first embodiment of the present disclosure is shown. Figure 1A FIG. is a top view of the first embodiment structure after the alignment mark structure 20 is formed in an embodiment where the alignment mark structure 20 is in a first geometric arrangement. Figure 1B FIG. is a top view of the first embodiment structure after the alignment mark structure 20 is formed in an embodiment where the alignment mark structure 20 is in a second geometric arrangement. Figure 1C FIG. is Figure 1A or Figure 1B a vertical cross-sectional view of the first embodiment structure of. The alignment mark structure is only schematic, and details of the alignment mark structure are not shown in Figure 1C . Thus, Figure 1C only the position of the alignment mark structure is shown, while Figure 1D and Figure 1E show the structural details of the alignment mark structure.

[0049] Figures 1A to 1CThe structure of the first embodiment shown includes a carrier wafer 310. The carrier wafer 310 may include a semiconductor wafer, an insulator layer, a conductive wafer, or a composite wafer, wherein the carrier wafer 310 provides sufficient mechanical strength for the structures to be formed thereon subsequently. In one embodiment, the carrier wafer 310 may include a transparent wafer, such as a glass wafer or a sapphire wafer. The thickness of the carrier wafer 310 may range from 500 microns to 2 millimeters, but smaller and larger thicknesses may also be used.

[0050] A light-to-heat conversion (LTHC) layer 311 may be formed on the top surface of the carrier wafer 310. The LTHC layer 311 contains materials that absorb light and convert it into heat. For example, suitable LTHC materials are commercially available. Generally, the LTHC layer 311 may be deposited by physical vapor deposition, chemical vapor deposition, or atomic layer deposition, and may have a thickness in the range of 10 nanometers to 1,000 nanometers, but smaller and larger thicknesses may also be used.

[0051] The area of the carrier wafer 310 may include a two-dimensional array composed of unit areas UA, and a two-dimensional array composed of fan-out packages will be formed in the unit areas UA subsequently. The two-dimensional array composed of unit areas UA may be arranged as a two-dimensional periodic array (e.g., a two-dimensional rectangular array), or may be arranged as a two-dimensional irregular array in which the unit areas UA repeat in a non-periodic manner. Although the drawings of the present disclosure show a two-dimensional periodic array composed of unit areas UA, embodiments in which the unit areas UA are arranged as a non-periodic two-dimensional array are also clearly contemplated herein.

[0052] According to aspects of the present disclosure, a set of at least one alignment mark structure 20 may be formed within each of the unit areas UA. For each of the unit areas UA, the relative positions of the set of at least one alignment mark structure 20 may be the same. The set of at least one alignment mark structure 20 for each unit area may Figure 1A include a plurality of alignment mark structures 20 as shown (i.e., in some or all corners of the UA), or may Figure 1BAs shown, it consists of a single alignment mark structure 20 (i.e., in a single corner of the UA). Generally, the total size of each alignment mark structure 20 (e.g., the maximum size along each repeating direction within a two-dimensional periodic array composed of unit areas UA) can be in the range of 20 micrometers to 300 micrometers, but smaller and larger total sizes can also be used for each alignment mark structure 20. The pattern of each alignment mark structure 20 can include any pattern that can be recognized as an orientable pattern (i.e., a non-circular pattern with azimuthal variation in the lateral range) by an optical system (e.g., a camera) loaded with a pattern recognition program. For example, the alignment mark structure 20 can have a cross-shaped pattern as shown in Figure 1A , an L-shaped pattern as shown in Figure 1B , or any other orientable pattern known in the art. The features within the pattern of the alignment mark structure 20 can have sizes that can be recognized by the optical system in a pick-and-place tool to be used subsequently. For example, depending on the optical resolution of the end-view optical system, the alignment mark structure 20 can have a minimum line width in the range of 2 micrometers to 50 micrometers. Generally, each alignment mark structure 20 can be formed in the peripheral region of the corresponding unit area UA such that the alignment mark structure 20 does not have any area overlap with the semiconductor die to be subsequently placed on the carrier wafer 310.

[0053] According to an aspect of the present disclosure, the alignment mark structure 20 of the present disclosure can be formed by depositing at least one material layer and patterning the at least one material layer, and the at least one material layer can include at least one metallic material layer or dielectric material layer. Figure 1D is Figure 1C A vertical cross-sectional view of a unit area with a first configuration of the first embodiment structure of Figure 1E is Figure 1C A vertical cross-sectional view of a unit area with a second configuration of the first embodiment structure of

[0054] Referring to Figure 1D, a first configuration of the first embodiment structure can be provided by depositing a layer stack composed of multiple metallic material layers (21, 23) and patterning the layer stack to form an alignment mark structure 20. The multiple metallic material layers (21, 23) can include a metallic adhesion promoter layer 21 and a metal layer 23. The metallic adhesion promoter layer 21 contains a metal that provides high adhesion. For example, the metallic adhesion promoter layer 21 can contain elemental metals (such as Ti, Ta, W, Co, TiCu alloy, etc.) and / or can be substantially composed of the elemental metals, and can have a thickness in the range of 5 nanometers to 100 nanometers, but smaller and larger thicknesses can also be used. The metal layer 23 contains a metal that can be deposited at a high deposition rate, for example, by electroplating. The metal layer 23 can contain copper and can have a thickness in the range of 0.5 micrometers to 20 micrometers (for example, 1 micrometer to 10 micrometers), but smaller and larger thicknesses can also be used.

[0055] Each of the multiple metallic material layers (21, 23) can be deposited as a blanket metallic material layer, that is, deposited as an unpatterned metallic material layer. A photoresist layer (not shown in the figure) can be applied on the multiple metallic material layers (21, 23) and can be patterned lithographically to form discrete photoresist material portions. An anisotropic etching process can be carried out to remove the portions of the multiple metallic material layers (21, 23) that are not shielded by the discrete photoresist material portions. The patterned portions of the multiple metallic material layers (21, 23) located under the discrete photoresist material portions constitute the alignment mark structure 20. The sidewalls of the alignment mark structure 20 can have a taper angle in the range of 0.1 degrees to 10 degrees (for example, 0.2 degrees to 5 degrees) relative to the vertical direction, but smaller and larger taper angles can also be used. In this embodiment, each of the alignment mark structures 20 can have a variable horizontal cross-sectional area that decreases with the vertical distance from the carrier wafer 310. The photoresist layer can then be removed, for example, by ashing. Each alignment mark structure 20 can include a layer stack composed of a metallic adhesion promoter layer 21 and a metal layer 23, and there is a horizontal interface between the metallic adhesion promoter layer 21 and the metal layer 23.

[0056] Refer to Figure 1E, a second configuration of the first embodiment structure can be provided by depositing a dielectric material layer and patterning the dielectric material layer to form an alignment mark structure 20. The dielectric material layer can include an organic material (e.g., a polymer material) or an inorganic material (e.g., silicon oxide, silicon nitride, silicon carbide, a dielectric metal oxide, or a layer stack composed of multiple inorganic dielectric material layers). The dielectric material layer can be formed, for example, by chemical vapor deposition or by spin coating. The thickness of the dielectric material layer can be in the range of 0.5 micrometers to 20 micrometers (e.g., 1 micrometer to 10 micrometers), but smaller and larger thicknesses can also be used.

[0057] The dielectric material layer can be deposited as a blanket metallic material layer, i.e., as an unpatterned metallic material layer. A photoresist layer (not shown in the figure) can be applied over the dielectric material layer and can be patterned lithographically to form discrete photoresist material portions. An anisotropic etching process can be performed to remove the portions of the dielectric material layer not shielded by the discrete photoresist material portions. The patterned portions of the dielectric material layer located under the discrete photoresist material portions constitute the alignment mark structure 20. In an alternative embodiment, a photosensitive dielectric material (e.g., a photosensitive polymer material) can be deposited, and the photosensitive dielectric material can be patterned by photolithographic exposure and development. In an illustrative example, polyimide can be used as the photosensitive polymer material. The remaining portion of the photosensitive dielectric material constitutes the alignment mark structure 20. In one embodiment, a curing process such as an annealing process can be performed after developing the photosensitive dielectric material. The sidewalls of the alignment mark structure 20 can have a taper angle α in the range of 1 degree to 20 degrees (e.g., 3 degrees to 10 degrees) relative to the vertical direction, but smaller and larger taper angles can also be used. In this embodiment, each of the alignment mark structures 20 can have a variable horizontal cross-sectional area that decreases with the vertical distance from the carrier wafer 310. The photoresist layer can then be removed, for example, by ashing. In embodiments where the alignment mark structure 20 consists essentially of at least one dielectric material, the alignment mark structure 20 is referred to as a dielectric alignment mark structure 24.

[0058] Generally, with reference to Figure 1D and Figure 1E the alignment mark structure 20 described can have any horizontal cross-sectional shape discussed with reference to Figures 1A to 1C

[0059] With reference to Figure 2 ​, a pick-and-place tool including at least one optical system and a pattern recognition program can be used to place the semiconductor die 700 on the top surface of the LTHC layer 311. According to an aspect of the present disclosure, a set of at least one alignment mark structure 20 located within each unit area UA serves as a reference structure for determining the placement position of each semiconductor die 700 placed within the corresponding unit area UA. In other words, each of the semiconductor dies 700 can be placed on the carrier wafer 310 using the corresponding alignment mark structure 20 within the same unit area UA as a reference position for positioning the corresponding semiconductor die 700. In one embodiment, a die attachment film (DAF) 710 can be bonded to the first side of each semiconductor die 700, while the second side of each semiconductor die 700 can be physically exposed. The second side of each semiconductor die 700 can include a corresponding array of bump structures, which is referred to herein as an array of on-die bump structures 788 (i.e., bump structures located on the semiconductor die). The on-die bump structures 788 can include C4 bonding pads, or can include micro-bump structures (which are also referred to as C2 bump structures). Each combination of the semiconductor die 700 and the DAF 710 can be disposed on the LTHC layer 311 such that the DAF 710 directly contacts the top surface of the LTHC layer 311. The thickness of each DAF 710 can be in the range of 1 micron to 20 microns (e.g., 2 microns to 6 microns), although smaller and larger thicknesses can also be used.

[0060] Optionally, a through-interposer via (TIV) structure 786 may be disposed on the top surface of the LTHC layer 311. The TIV structure 786 may be placed within each unit area using the same pick-and-place tool or a different pick-and-place tool. According to aspects of the present disclosure, a set of at least one alignment mark structure 20 located within each unit area UA serves as a reference structure for determining the placement location of each TIV structure 786 placed within the corresponding unit area UA. In other words, each of the TIV structures 786 may be placed on the carrier wafer 310 using the corresponding alignment mark structure 20 within the same unit area UA as a reference location for positioning the corresponding TIV structure 786. Optionally, an additional die attach film (not shown in the figures) may be used to assist in placing the TIV structure 786 on the LTHC layer 311. In such embodiments, the additional die attach film may be positioned between the TIV structure 786 and the LTHC layer 311. Generally, the TIV structure 786 includes at least one metallic material (e.g., copper or tungsten) and may have a cylindrical shape or a corresponding frustum shape. The lateral dimension of each TIV structure 786 may be in the range of 5 microns to 60 microns (e.g., 10 microns to 30 microns), although smaller and larger dimensions may also be used. The height of the TIV structure 786 may be approximately the same as the height of the semiconductor die 700. Generally, the top surface of the TIV structure 786 may be in the same horizontal plane as the top surface of the semiconductor die 700. The height (i.e., thickness) of each semiconductor die 700 may be in the range of 30 microns to 300 microns, although smaller and larger thicknesses may also be used.

[0061] Refer to Figure 3, a molding compound (MC) can be applied to the gap between the semiconductor die 700 and the TIV structure 786. The MC includes an epoxy-containing compound that can be hardened (i.e., cured) to provide a dielectric material portion having sufficient stiffness and mechanical strength. The MC can include epoxy resin, a hardener, silica (as a filler material), and other additives. Depending on the viscosity and flowability, the MC can be provided in liquid form or in solid form. Liquid MC generally provides better handling, good flowability, fewer voids, better filling, and fewer flow marks. Solid MC generally provides a smaller cure shrinkage, better stand-off, and less die drift. A high filler content (e.g., 85 wt%) in the MC can shorten the time in mold, reduce the mold shrinkage, and reduce the mold warpage. A uniform filler size distribution in the MC can reduce the flow marks and enhance the flowability.

[0062] The MC can be cured at a curing temperature to form an MC matrix, which is referred to herein as the molding compound (MC) matrix 796M. The MC matrix 796M laterally surrounds each of the semiconductor die 700 and the TIV structure 786. The MC matrix 796M can be a continuous material layer extending across the entire area of the reconstructed wafer overlying the carrier wafer 310. An excess portion of the MC matrix 796M can be removed from above the horizontal plane including the top surface of the semiconductor die 700 and the top surface of the TIV structure 786 by a planarization process, which can use chemical mechanical planarization (CMP). After the planarization process is performed, the top surface of the semiconductor die 700 and the top surface of the TIV structure 786 can be physically exposed. The top surface of the semiconductor die 700 and the top surface of the TIV structure 786 can be located in the horizontal plane including the top surface of the MC matrix 796M.

[0063] The MC substrate 796M includes a plurality of molded compound (MC) interposer frames located within respective unit areas UA. Each MC interposer frame corresponds to a portion of the MC substrate 796M located within the unit area UA (i.e., the area of a single interposer to be formed subsequently). In other words, each portion of the MC substrate 796M located within the respective unit area UA constitutes an MC interposer frame. The MC interposer frames are laterally adjacent to each other to provide an integrated structure, i.e., the MC substrate 796M. Each MC interposer frame laterally surrounds a respective set of at least one semiconductor die 700 and may laterally surround a respective array formed by the TIV structure 786.

[0064] Referring Figure 4 , a redistribution structure 60R may be formed on top of the MC substrate 796M. The redistribution structure 60R includes a redistribution dielectric layer 660, redistribution wiring interconnects 680 formed in the redistribution dielectric layer 660, and a bonding structure 688 electrically connected to the redistribution wiring interconnects 680 and having a physically exposed top surface. The redistribution dielectric layer 660 contains a respective dielectric polymer material such as, for example, polyimide (PI), benzocyclobutene (BCB), or polybenzobisoxazole (PBO). Each redistribution dielectric layer 660 may be formed by spin coating and drying the respective dielectric polymer material. The thickness of each redistribution dielectric layer 660 may be in the range of 2 micrometers to 40 micrometers (e.g., 4 micrometers to 20 micrometers). Each redistribution dielectric layer 660 may be patterned, for example, by applying a respective photoresist layer over each redistribution dielectric layer 660 and patterning the photoresist layer; and using an etching process such as, for example, an anisotropic etching process to transfer the pattern in the photoresist layer into the redistribution dielectric layer 660. The photoresist layer may then be removed, for example, by ashing.

[0065] Each of the redistribution wiring interconnects 680 can be formed by depositing a metallic seed layer by sputtering; applying a photoresist layer over the metallic seed layer and patterning the photoresist layer to form an opening pattern through the photoresist layer; electroplating a metallic fill material (such as copper, nickel, or a stack composed of copper and nickel); removing the photoresist layer (e.g., by ashing); and etching a portion of the metallic seed layer located between the electroplated metallic fill materials. The metallic seed layer can include, for example, a stack composed of a titanium barrier layer and a copper seed layer. The titanium barrier layer can have a thickness in the range of 60 nanometers to 300 nanometers, and the copper seed layer can have a thickness in the range of 100 nanometers to 600 nanometers. The metallic fill material for the redistribution wiring interconnects 680 can include copper, nickel, or copper and nickel. The thickness of the metallic fill material deposited for each redistribution wiring interconnect 680 can be in the range of 2 micrometers to 40 micrometers (e.g., 4 micrometers to 10 micrometers), but smaller or larger thicknesses can also be used. The total number of wiring levels in the redistribution structure 60R (i.e., the levels of the redistribution wiring interconnects 680) can be in the range of 1 to 10.

[0066] The bonding structure 688 can include a first type of bonding structure 688A that can be used to bond a solder material portion (e.g., a solder ball) and a second type of bonding structure 688B that can be used to subsequently bond a local interconnect die. In one embodiment, the first type of bonding structure 688A can include C4 bonding pads, and the second type of bonding structure 688B can include microbump structures. The bonding structure 688 can have a horizontal cross-sectional shape that is rectangular, rounded rectangular, or circular. Other horizontal cross-sectional shapes can also be within the scope contemplated by this disclosure.

[0067] Referring Figure 5 to, the local interconnect die 400 can be bonded to the second type of bonding structure 688B using the solder material portions 490 within each unit area UA. The local interconnect die 400 can include, for example, a local silicon interconnect (LSI) die that includes a silicon substrate and a metal interconnect structure embedded within an inorganic dielectric material layer. The local interconnect die 400 can provide an electrical path for signal transmission between semiconductor dies 700 within the same unit area UA. In one embodiment, the local interconnect die 400 can include an array of bump structures 488 that are bonded to the second type of bonding structure 688B through an array of solder material portions 490.

[0068] Referring Figure 6, an additional solder material portion 290 can be bonded to a first type of bonding structure 688A of the redistribution structure 60R. The additional solder material portion 290 can include solder balls having a height greater than the combination of each of the following: the local interconnect die 400, the array formed by the bump structure 488, and the array formed by the solder material portion 490. For example, the additional solder material portion 290 can have a diameter in the range of 30 micrometers to 100 micrometers (e.g., 40 micrometers to 70 micrometers), but smaller and larger diameters can also be used.

[0069] Referring to Figure 7 , ultraviolet radiation can pass through the carrier wafer 310 and irradiate the LTHC layer 311. When irradiated with ultraviolet radiation, the LTHC layer 311 generates heat and is decomposed. The carrier wafer 310 can be separated from the reconstructed wafer, which includes a two-dimensional array of assemblies composed of the following: at least one semiconductor die 700, a set of at least one alignment mark structure 20, a molded compound die frame, and an organic interposer (the organic interposer is a part of the redistribution structure 60R within the corresponding unit area UA), an optional local interconnect die 400, and an array formed by the solder material portion 290. A suitable cleaning process can be implemented to remove the residual material portion from the decomposed LTHC layer 311. Generally, the carrier wafer 310 is separated from an assembly including a molded compound matrix 796M, a semiconductor die 700, and an alignment mark structure 20. The reconstructed wafer is divided along a dividing channel, which can overlap with the boundary between adjacent pairs of unit areas. Each divided portion of the reconstructed wafer includes a fan-out package 800.

[0070] Multiple fan-out packages 800 can be formed by dividing the molded compound matrix 796M. Each fan-out package 800 includes at least one semiconductor die 700, a set of at least one alignment mark structure 20, and a molded compound die frame 796 that is a cut portion of the molded compound matrix 796M.

[0071] Generally speaking, embodiments of the present disclosure provide a device structure including a fan-out package 800. The fan-out package 800 includes: a molded compound die frame 796 that laterally surrounds at least one semiconductor die 700; and an organic interposer 600 including a redistribution dielectric layer 660 embedded with redistribution wiring interconnections 680 and located on a first horizontal surface 791 of the molded compound die frame 796. An alignment mark region AMR including a local recessed region is located within an opening in a second horizontal surface 792 of the molded compound die frame 796. The lateral extent of each alignment mark region AMR may be defined by the lateral extent of the local recessed region, which is defined by the sidewalls and recessed surfaces of the molded compound die frame 796 that laterally surround and contact the alignment mark structure 20. The local recessed region extends from the second horizontal surface 792 towards the organic interposer 600.

[0072] In one embodiment, in a plan view along a direction perpendicular to the first horizontal surface 791, the alignment mark region AMR does not have any area overlap with the at least one semiconductor die 700. The plan view described herein refers to a view along the vertical direction (e.g., a direction perpendicular to the first horizontal surface 791). In one embodiment, each alignment mark structure 20 may be located within a corresponding local recessed region. In one embodiment, each alignment mark structure 20 may have the same volume as the corresponding local recessed region. In this embodiment, the flat surface of the alignment mark structure 20 that is physically exposed may be located within the horizontal plane including the second horizontal surface 792 of the molded compound die frame 796.

[0073] In one embodiment, each alignment mark structure 20 may include a layer stack composed of multiple metallic material layers (21, 23), with at least one horizontal interface between the multiple metallic material layers (21, 23). In one embodiment, each alignment mark structure 20 may have a variable horizontal cross-sectional area that increases with the vertical distance from the horizontal plane including the first horizontal surface 791. In one embodiment, each alignment mark structure 20 may have a thickness smaller than the thickness of the molded compound die frame 796 and smaller than the thickness of the at least one semiconductor die 700 and the TIV structure 786.

[0074] In one embodiment, the horizontal surface of the alignment mark structure 20 (e.g., the horizontal top surface observed when inverted) is completely located within the horizontal plane including the second horizontal surface 792 of the molded compound die frame 796. In one embodiment, the sidewalls and bottom surface of the alignment mark structure 20 (observed when inverted) are in direct contact with the molded compound die frame 796.

[0075] Refer to Figure 8, the encapsulation substrate 200 can be bonded to the fan-out package 800. The encapsulation substrate 200 can be a cored packaging substrate including a core substrate 210, or can be a coreless packaging substrate without an encapsulation core. As another alternative, the encapsulation substrate 200 can include a system-on-integrated packaging substrate (SoIS), and the system-on-integrated packaging substrate (SoIS) includes a redistribution layer, a dielectric interlayer, and / or at least one embedded interposer (such as a silicon interposer). Such a system-on-integrated packaging substrate can include layer-to-layer interconnections using solder material portions, micro-bumps, underfill material portions (such as molded underfill material portions), and / or adhesive films. Although the present disclosure is described using a cored packaging substrate, it should be understood that the scope of the present disclosure is not limited by any specific type of substrate encapsulation. For example, an SoIS can be used instead of a cored packaging substrate. In an embodiment using an SoIS, the core substrate 210 can include a glass epoxy board, and the glass epoxy board includes an array formed by through-plate holes. An array formed by through-core via structures 214 containing a metallic material can be provided in the through-plate holes. Each through-core via structure 214 may or may not include a cylindrical hollow. Optionally, a dielectric pad (not shown in the figure) can be used to electrically isolate the through-core via structure 214 from the core substrate 210.

[0076] The encapsulation substrate 200 can include a surface laminar circuit (SLC) 240 on the board side and a surface laminar circuit (SLC) 260 on the chip side. The board-side SLC can include a board-side insulating layer 242 in which board-side wiring interconnections 244 are embedded. The chip-side SLC 260 can include a chip-side insulating layer 262 in which chip-side wiring interconnections 264 are embedded. The board-side insulating layer 242 and the chip-side insulating layer 262 can contain a photosensitive epoxy resin material that can be patterned by lithography and then cured. The board-side wiring interconnections 244 and the chip-side wiring interconnections 264 can contain copper that can be deposited by electroplating in the patterns in the board-side insulating layer 242 or the chip-side insulating layer 262.

[0077] In one embodiment, the chip-side surface laminated circuit 260 includes chip-side wiring internal connections 264 connected to an array formed by substrate bonding pads 268. The array formed by the substrate bonding pads 268 can be configured to enable bonding through C4 solder balls. The board-side surface laminated circuit 240 includes board-side wiring internal connections 244 connected to an array formed by board-side bonding pads 248. The array formed by the board-side bonding pads 248 is configured to enable bonding through solder joints having a size larger than that of the C4 solder balls. Although the present disclosure is described using an embodiment in which the package substrate 200 includes the chip-side surface laminated circuit 260 and the board-side surface laminated circuit 240, embodiments in which one of the chip-side surface laminated circuit 260 and the board-side surface laminated circuit 240 is omitted or replaced by an array formed by bonding structures (such as microbumps) are also explicitly contemplated herein. In an illustrative example, the chip-side surface laminated circuit 260 can be replaced by an array formed by microbumps or any other array formed by bonding structures.

[0078] The fan-out package 800 can be attached to the package substrate 200 using solder material portions 290, which are also referred to as package-substrate-bonding (FSB) solder material portions 290. Specifically, each of the FSB solder material portions 290 can be bonded to a corresponding one of the substrate bonding pads 268 and to a corresponding one of the bonding structures 688 located on the fan-out package 800. A reflow process can be performed to reflow the FSB solder material portions 290, such that each FSB solder material portion 290 can be bonded to a corresponding one of the substrate bonding pads 268 and to a corresponding one of the bonding structures 688.

[0079] An underfill material can be applied to the gap between the fan-out package 800 and the package substrate 200. The underfill material can include any underfill material known in the art. An underfill material portion can be formed around the FSB solder material portions 290 in the gap between the fan-out package 800 and the package substrate 200. This underfill material portion is referred to herein as the package-substrate underfill material portion 292 or the PS underfill material portion 292.

[0080] According to an aspect of the present disclosure, a device structure is provided. The device structure includes: a fan-out package 800, including a molded compound die frame 796, at least one semiconductor die 700 laterally surrounded by the molded compound die frame 796, and an organic interposer 600. The organic interposer 600 includes a redistribution dielectric layer 660 embedded with redistribution wiring interconnections 680 and is located on a first horizontal surface 791 of the molded compound die frame 796; and a package substrate 200, bonded to a bonding structure 688 of the organic interposer 600. An alignment mark region AMR including a local depression region is located within an opening in a second horizontal surface 792 of the molded compound die frame 796.

[0081] Referring Figure 9 , an additional semiconductor die 300 can be attached to the fan-out package 800. The additional semiconductor die 300 can be any type of semiconductor die known in the art. For example, the additional semiconductor die 300 can include a logic die, a memory die, or a system-on-integrated-chip (SoIC) die. The additional semiconductor die 300 can include an array formed by bonding structures 388, and the array formed by the bonding structures 388 can include an array formed by C4 pads or an array formed by micro-bumps. A solder material portion 390 can be used to provide a bond between the array formed by the bonding structures 388 in the additional semiconductor die 300 and the physically exposed top surface of the TIV structure 786. In one embodiment, the TIV structure 786 can laterally surround each semiconductor die 700 within the fan-out package 800. A bottom fill material portion 392 can be applied to the gap between the fan-out package 800 and the additional semiconductor die 300. A stiffener ring (not shown in the figure) or a cover structure (not shown in the figure) can be attached to the fan-out package 800 or the package substrate 200 as appropriate.

[0082] In one embodiment, the additional semiconductor die 300 is disposed above the fan-out package 800 and attached to the fan-out package 800. The fan-out package 800 includes a through-interposer-via (TIV) structure 786 that extends vertically through the molded compound die frame 796. In one embodiment, the additional semiconductor die 300 is bonded to the TIV structure 786 through an array formed by solder material portions 390. In one embodiment, the alignment mark region AMR has an area overlap with the additional semiconductor die 300 and does not have any area overlap with the at least one semiconductor die 700.

[0083] Referring Figure 10, a printed circuit board (PCB) 100 including a PCB substrate 110 and PCB bonding pads 188 can be provided. The PCB 100 includes a printed circuit system (not shown in the figure) at least on one side of the PCB substrate 110. An array composed of solder joints 190 can be formed to bond an array composed of board-side bonding pads 248 to an array composed of PCB bonding pads 188. By disposing an array composed of solder balls between the array composed of board-side bonding pads 248 and the array composed of PCB bonding pads 188, and by reflowing the array composed of solder balls, the solder joints 190 can be formed. An additional underfill material portion can be formed around the solder joints 190 by applying an underfill material and shaping the underfill material. The additional underfill material portion is referred to herein as the board-substrate underfill material portion 192 or the BS underfill material portion 192. The package substrate 200 is attached to the PCB 100 through the array composed of the solder joints 190.

[0084] Referring to Figure 11 , by omitting the application of an underfill material between the fan-out package 800 and the additional semiconductor die 300, a first alternative configuration of the first embodiment structure can be obtained from Figure 10 the first embodiment structure shown.

[0085] Referring to Figure 12 , by using the dielectric alignment mark structure 24 (as described in reference to Figure 1E ), a second alternative configuration of the first embodiment structure can be obtained from Figure 10 the first embodiment structure shown. In one embodiment, each alignment mark structure 20 includes a dielectric material portion (referred to as the dielectric alignment mark structure 24), and the dielectric material portion has a variable horizontal cross-sectional area that increases with the vertical distance from a horizontal plane including the first horizontal surface 791. Such a geometric feature is a unique structural feature resulting from using the dielectric alignment mark structure 24 in the above manner. The variable horizontal cross-sectional area decreases with the vertical distance downward from a horizontal plane including the second horizontal surface 792.

[0086] Referring to Figure 13 , by omitting the application of an underfill material between the fan-out package 800 and the additional semiconductor die 300, a third alternative configuration of the first embodiment structure can be obtained from Figure 12 the second alternative configuration of the first embodiment structure shown.

[0087] Referring to Figure 14, A second embodiment structure including a fan - out package 800 is shown according to a second embodiment of the present disclosure. By omitting the formation of the TIV structure 786, the second embodiment structure can be obtained from the first embodiment structure as shown in Figure 7 .

[0088] Referring to Figure 15 , a second embodiment structure after forming a combination including a fan - out package 800, an optional additional semiconductor die 300, and a package substrate 200 is shown. Generally, the second embodiment structure can be formed by performing the processing steps described in reference to Figure 8 with optional modifications in the positions of the bonding structures (268, 688) and the solder material portion 290. In an embodiment where an optional additional semiconductor die 300 is placed, an additional solder material portion 290 located between the substrate bonding pad 268 and the semiconductor bonding pad 388 can be used to bond the optional additional semiconductor die 300 to the package substrate 200. A package - substrate underfill material portion 292 can be applied around the solder material portion 290. In an embodiment where an additional semiconductor die 300 is used, the top surface of the additional semiconductor die can be at the same horizontal level as the top surface of the fan - out package 800, above the horizontal level, or below the horizontal level.

[0089] Referring to Figure 16 , a lid structure 230 can be bonded to the package substrate 200, for example, using an adhesive layer 231. In one embodiment, the lid structure 230 includes sidewalls and a horizontal cap portion. In one embodiment, the horizontal cap portion at least overlies and at least covers the entirety formed by the at least one semiconductor die 700 and the alignment mark region AMR. The horizontal cap portion of the lid structure 230 can cover or not cover the additional semiconductor die 300. The alignment mark structure 20 is located in a partial recessed area of the alignment mark region AMR.

[0090] Referring to Figure 17 , the processing steps described in reference to Figure 10 can be performed to bond a printed circuit board 100 to a combination including a fan - out package 800, an additional semiconductor die 300, a package substrate 200, and a lid structure 230.

[0091] Referring to Figure 18 , by using a dielectric alignment mark structure 24 (as described in reference to Figure 1E ) as the alignment mark structure 20, it can be obtained from Figure 17The structure of the first embodiment shown gives an alternative configuration of the second embodiment structure. In one embodiment, each alignment mark structure 20 includes a dielectric material portion 24 having a variable horizontal cross-sectional area that increases with the vertical distance from a horizontal plane including a first horizontal surface 791. The variable horizontal cross-sectional area decreases with the vertical distance downward from a horizontal plane including a second horizontal surface 792.

[0092] Referring Figure 19 , by forming the die attach film 710 over the entire area of the carrier wafer 310 and over each of the alignment mark structures 20, the Figures 1A to 1E third embodiment structure according to the third embodiment of the present disclosure can be obtained from the structure of the first embodiment shown. In this embodiment, the die attach film 710 can have the same area as the carrier wafer 310 and can have no openings therethrough. Generally, the die attach film 710 can be conformally formed over the alignment mark structures 20 and above the carrier wafer 310.

[0093] Referring Figure 20 , the processing steps set forth in Figures 2 to 6 can be implemented with modifications such that there is no die attach film on the semiconductor die 700. In other words, before performing the pick-and-place operation, the die attach film 710 is disposed on the top surface of the carrier wafer 310 rather than on the surface of the semiconductor die 700. Thus, each semiconductor die 700 is disposed over the die attach film 710.

[0094] Referring Figure 21 , ultraviolet radiation can pass through the carrier wafer 310 and irradiate the LTHC layer 311. When irradiated with ultraviolet radiation, the LTHC layer 311 generates heat and is decomposed. The carrier wafer 310 can be separated from a reconstructed wafer including a two-dimensional array of assemblies consisting of at least one semiconductor die 700, a set of at least one alignment mark structure 20, a die attach film 710, a molded compound die frame, and an organic interposer (the organic interposer being a part of the redistribution structure 60R within a corresponding unit area UA), an optional local interconnect die 400, and an array of solder material portions 290. A suitable cleaning process can be implemented to remove residual material portions from the decomposed LTHC layer 311. Generally, the carrier wafer 310 is separated from an assembly including a molded compound matrix 796M, semiconductor die 700, and alignment mark structures 20.

[0095] Subsequently, an isotropic etching process may be performed to remove the horizontal extension portion of the die attach film 710 below the horizontal plane including the second horizontal surface 792 of each molded compound die frame, where each molded compound die frame is part of the molded compound matrix 796M. For example, a wet etching process using an organic solvent may be used to remove the horizontal extension portion of the die attach film 710. Each remaining portion of the die attach film 710 located within the corresponding alignment mark region AMR is referred to herein as the die attach film 712, and the die attach film 712 has the same material composition and the same thickness as Figure 19 the die attach film 710 shown. In one embodiment, each die attach film 712 may laterally surround the corresponding alignment mark structure 20.

[0096] Referring to Figure 22 , the reconstructed wafer is diced along the dicing channels, which may overlap the boundaries between adjacent pairs of unit regions. Each diced portion of the reconstructed wafer includes a fan-out package 800. A plurality of fan-out packages 800 may be formed by dicing the molded compound matrix 796M. Each fan-out package 800 includes at least one semiconductor die 700, a set of at least one alignment mark structure 20, and a molded compound die frame 796 that is a cut portion of the molded compound matrix 796M.

[0097] Referring to Figure 23 , the processing steps described with reference to Figures 8 to 10 may be performed to attach the fan-out package 800 to the package substrate 200, attach additional semiconductor dies 300 to the package substrate 200, and attach the assembly composed of the fan-out package 800, the package substrate 200, and the additional semiconductor dies 300 to the printed circuit board 100.

[0098] The fan-out package 800 includes: a molded compound die frame 796 that laterally surrounds at least one semiconductor die 700; and an organic interposer 600 including a redistribution dielectric layer 660 in which redistribution wiring interconnections 680 are embedded, and located on the first horizontal surface 791 of the molded compound die frame 796. An alignment mark region AMR including a local recessed region is located within an opening in the second horizontal surface 792 of the molded compound die frame 796. The lateral extent of each alignment mark region AMR may be defined by the lateral extent of the local recessed region, which is defined by the sidewalls and the recessed surface of the molded compound die frame 796 that laterally surround and contact the alignment mark structure 20. The local recessed region extends from the second horizontal surface 792 toward the organic interposer 600.

[0099] In one embodiment, in a plan view along a direction perpendicular to the first horizontal surface 791, the alignment mark region AMR does not have any area overlap with the at least one semiconductor die 700. In one embodiment, each alignment mark structure 20 may be located within a respective local recess region. In one embodiment, each alignment mark structure 20 may have a volume smaller than that of the respective local recess region. In one embodiment, the flat surface (e.g., the top surface) of the alignment mark structure 20 that is physically exposed may be in the horizontal plane of the second horizontal surface 792 including the molded compound die frame 796.

[0100] In one embodiment, each alignment mark structure 20 may include a layer stack composed of multiple metallic material layers (21, 23), with at least one horizontal interface between the multiple metallic material layers (21, 23). In one embodiment, each alignment mark structure 20 may have a variable horizontal cross-sectional area that increases with the vertical distance from the horizontal plane including the first horizontal surface 791. In one embodiment, each alignment mark structure 20 may have a thickness smaller than the thickness of the molded compound die frame 796 and smaller than the thickness of the at least one semiconductor die 700 and the TIV structure 786.

[0101] In one embodiment, the horizontal surface of the alignment mark structure 20 (e.g., the horizontal top surface observed when inverted) is completely within the horizontal plane of the second horizontal surface 792 including the molded compound die frame 796. In one embodiment, the alignment mark structure 20 is spaced apart from the molded compound die frame 796 by a die attach film 712 including a polymer matrix layer 712P and an adhesive layer 712A.

[0102] A bottom fill material portion 392 may be formed in the gap between the fan-out package 800 and the additional semiconductor die 300. The upper portions of the horizontal top surface and the sidewalls of each alignment mark structure 20 may be in contact with the bottom fill material portion 392. The lower portions of the sidewalls of each alignment mark structure 20 may be in contact with the adhesive layer 712A of the die attach film 712.

[0103] Referring to Figure 24 , by omitting the formation of the bottom fill material portion 392, a first alternative configuration of the third embodiment structure can be obtained from the third embodiment structure shown in Figure 23 . In this embodiment, the upper portions of the horizontal top surface and the sidewalls of each alignment mark structure 20 may be physically exposed and thus may be in contact with the gaseous environment. The lower portions of the sidewalls of each alignment mark structure 20 may be in contact with the adhesive layer 712A of the die attach film 712.

[0104] Referring to Figure 25 , by using Figure 22The fan-out package 800 shown and by implementing the reference Figures 15 to 17 The processing steps described above can obtain a second alternative configuration of the third embodiment structure according to the third embodiment of the present disclosure. Optionally, an additional adhesive layer 233 can be used to bond the bottom surface of the horizontal cap portion of the lid structure 230 to the top surface of the alignment mark structure 20.

[0105] In one embodiment, the horizontal top surface of the alignment mark structure 20 can be located above the horizontal plane including the second horizontal surface 792 of the molded compound die frame 796. In one embodiment, the alignment mark structure 20 is spaced apart from the molded compound die frame 796 by a die attach film 712 including a polymer matrix layer 712P and an adhesive layer 712A. In one embodiment, the alignment mark structure 20 is located within a local recessed area; and the horizontal cap portion of the lid structure 230 can be bonded to the alignment mark structure 20 through the adhesive layer 233.

[0106] Reference Figure 26 , by not using an additional adhesive layer 233, a third alternative configuration of the third embodiment structure can be obtained from Figure 26 The second alternative configuration of the third embodiment structure shown. In this embodiment, the alignment mark structure 20 is partially located within a local recessed area; and the horizontal cap portion of the lid structure 230 can be in direct contact with the alignment mark structure 20.

[0107] Reference Figure 27 , by directly conformally bonding the die attach film 710 to the physically exposed surface of the LTHC layer 311 and directly conformally bonding it to the physically exposed surface of the dielectric alignment mark structure 24, a fourth embodiment structure according to the fourth embodiment of the present disclosure can be obtained from Figure 1E The first embodiment structure shown. The sidewall of the dielectric alignment mark structure 24 can have a taper angle α in the range of 1 degree to 20 degrees (e.g., 3 degrees to 10 degrees) relative to the vertical direction, but smaller and larger taper angles can also be used. In this embodiment, each of the dielectric alignment mark structures 24 can have a variable horizontal cross-sectional area that decreases with the vertical distance from the carrier wafer 310.

[0108] Reference Figure 28 , the reference described in Figures 2 to 6 can be implemented with modifications such that the die attach film 710 exists as a single continuous film. In other words, before performing the pick-and-place operation, the die attach film 710 is disposed on the top surface of the carrier wafer 310 instead of on the surface of the semiconductor die 700. Thus, each semiconductor die 700 is disposed on top of the die attach film 710.

[0109] Reference Figure 29, ultraviolet radiation can pass through the carrier wafer 310 and irradiate the LTHC layer 311. The carrier wafer 310 can be separated from the reconstructed wafer, and the reconstructed wafer includes a two-dimensional array of assemblies composed of: at least one semiconductor die 700, a set of at least one alignment mark structure 20, a die attach film 710, a molded compound die frame, and an organic interposer (the organic interposer is a part of the redistribution structure 60R within the corresponding unit area UA), an optional local interconnect die 400, and an array composed of solder material portions 290. A suitable cleaning process can be implemented to remove the residual material portions from the decomposable LTHC layer 311. Generally, the carrier wafer 310 is separated from an assembly including a molded compound matrix 796M, semiconductor die 700, and alignment mark structures 20.

[0110] Subsequently, at least one isotropic etching process can be implemented to selectively remove (i.e., without etching or with minimal etching of the molded compound matrix 796M) the dielectric alignment mark structures 24 and the die attach film 710 relative to the molded compound matrix 796M. For example, a wet etching process using an organic solvent can be used to remove the dielectric alignment mark structures 24 and the die attach film 710. Each alignment mark region AMR includes a void 27 that does not have any solid-phase material and is within the volume of the local recessed region.

[0111] Referring to Figure 30 , the reconstructed wafer is divided along a dividing channel, and the dividing channel can overlap with the boundary between adjacent pairs of unit areas. Each divided portion of the reconstructed wafer includes a fan-out package 800. Multiple fan-out packages 800 can be formed by dividing the molded compound matrix 796M. Each fan-out package 800 includes at least one semiconductor die 700, a set of at least one alignment mark structure 20, and a molded compound die frame 796 that is a cut portion of the molded compound matrix 796M.

[0112] Referring to Figure 31 , the processing steps described in Figures 8 to 10 can be implemented to attach the fan-out package 800 to the package substrate 200, attach an additional semiconductor die 300 to the package substrate 200, and attach the assembly composed of the fan-out package 800, the package substrate 200, and the additional semiconductor die 300 to the printed circuit board 100.

[0113] The fan-out package 800 includes: a molded compound die frame 796 that laterally surrounds at least one semiconductor die 700; and an organic interposer 600 that includes a redistribution dielectric layer 660 in which redistribution wiring interconnections 680 are embedded and that is located on a first horizontal surface 791 of the molded compound die frame 796. An alignment mark region AMR including a local recessed region is located within an opening in a second horizontal surface 792 of the molded compound die frame 796.

[0114] In one embodiment, the volume of the local recessed region may be the same as the volume of a bottom fill material protrusion 392P that is a region of a bottom fill material portion that fills a void 27 formed during a processing step. The lateral extent of each alignment mark region AMR may be defined by the lateral extent of the local recessed region that is defined by the volume of the bottom fill material protrusion 392P. The local recessed region extends from the second horizontal surface 792 toward the organic interposer 600. Figure 27 In one embodiment, in a plan view along a direction perpendicular to the first horizontal surface 791, the alignment mark region AMR does not have any area overlap with the at least one semiconductor die 700. In one embodiment, each bottom fill material protrusion 392P may be located within a corresponding local recessed region. In one embodiment, each bottom fill material protrusion 392P may have the same volume as the corresponding local recessed region.

[0115] In one embodiment, each bottom fill material protrusion 392P may have a variable horizontal cross-sectional area that increases with the vertical distance from a horizontal plane including the first horizontal surface 791. In one embodiment, each bottom fill material protrusion 392P may have a thickness that is less than the thickness of the molded compound die frame 796 and less than the thickness of the at least one semiconductor die 700 and the TIV structure 786. Each bottom fill material protrusion 392P may contact the sidewall and the recessed surface of the molded compound die frame 796.

[0116] In one embodiment, each bottom fill material protrusion 392P may have a thickness that is less than the thickness of the molded compound die frame 796 and less than the thickness of the at least one semiconductor die 700 and the TIV structure 786. Each bottom fill material protrusion 392P may contact the sidewall and the recessed surface of the molded compound die frame 796.

[0117] Referring to Figure 32 and by omitting the formation of the bottom fill material portion 392, a first alternative configuration of the fourth embodiment structure may be obtained from the fourth embodiment structure shown. Each alignment mark region AMR may include a local recessed region defined by a corresponding void 27 that does not have any solid-phase material. The sidewall and the recessed surface of the molded compound die frame 796 may be physically exposed to the void 27 within each alignment mark region AMR. Figure 29 Referring to

[0118] and by using Figure 33 and by using Figure 28The fan-out package 800 shown and by implementing the reference Figures 15 to 17 The processing steps described above can obtain a second alternative configuration of the structure of the fourth embodiment. In one embodiment, the alignment mark region AMR including the local depression region may include a void 27 that does not have any solid-phase material and extends vertically from the second horizontal surface 792 of the molded compound die frame 796 toward the first horizontal surface 791 of the molded compound die frame 796.

[0119] Reference Figure 34 , the flowchart shows the steps for forming a device structure according to an embodiment of the present disclosure.

[0120] Referring to step 3410 and Figures 1A to 1E 、 Figure 19 And Figure 25 , an alignment mark structure 20 can be formed on the carrier wafer 310.

[0121] Referring to step 3420 and Figure 2 、 Figure 20 And Figure 26 , the alignment mark structure 20 can be used as a reference position for positioning at least one semiconductor die 700, and at least one semiconductor die 700 (per unit area UA) can be placed on the carrier wafer 310.

[0122] Referring to step 3430 and Figure 3 、 Figure 20 And Figure 26 , a molded compound matrix 796M can be formed around at least one semiconductor die 700 and on the alignment mark structure 20.

[0123] Referring to step 3440 and Figures 4 to 18 And Figures 20 to 33 , the fan-out package 800 can be formed by dividing the molded compound matrix 796M. The fan-out package 800 includes at least one semiconductor die 700, an alignment mark structure 20, and a molded compound die frame 796 that is a cut portion of the molded compound matrix 796M.

[0124] Referring to all the accompanying drawings and according to various embodiments of the present disclosure, a device structure including a fan-out package 800 is provided. The fan-out package 800 includes: a molded compound die frame 796 that laterally surrounds at least one semiconductor die 700; and an organic interposer 600 including a redistribution dielectric layer 660 embedded with redistribution wiring interconnections 680 and located on a first horizontal surface 791 of the molded compound die frame 796, wherein an alignment mark region AMR including a local recessed region is located within an opening in a second horizontal surface 792 of the molded compound die frame 796, and the local recessed region extends from the second horizontal surface 792 toward the organic interposer 600.

[0125] In one embodiment, in a plan view along a direction perpendicular to the first horizontal surface 791, the alignment mark region AMR does not have any area overlap with the at least one semiconductor die 700. In one embodiment, an alignment mark structure 20 is located within the local recessed region.

[0126] In one embodiment, the alignment mark structure 20 includes a layer stack formed by a plurality of metallic material layers (21, 23), and at least one horizontal interface is included between the plurality of metallic material layers (21, 23). In one embodiment, the alignment mark structure 20 includes a dielectric material portion 24 having a variable horizontal cross-sectional area that increases with the vertical distance from a horizontal plane including the first horizontal surface 791.

[0127] In one embodiment, a horizontal surface of the alignment mark structure 20 is completely located within a horizontal plane including the second horizontal surface 792 of the molded compound die frame 796. In one embodiment, a horizontal surface of the alignment mark structure 20 is located above a horizontal plane including the second horizontal surface 792 of the molded compound die frame 796.

[0128] In one embodiment, sidewalls and a bottom surface of the alignment mark structure 20 are in direct contact with the molded compound die frame 796. In one embodiment, the alignment mark structure 20 is spaced apart from the molded compound die frame 796 by a die bonding film 712 including a polymer matrix layer 712P and an adhesive layer 712A.

[0129] According to an aspect of the present disclosure, a device structure is provided. The device structure includes: a fan-out package 800, including a molded compound die frame 796, at least one semiconductor die 700 laterally surrounded by the molded compound die frame 796, and an organic interposer 600. The organic interposer 600 includes a redistribution dielectric layer 660 embedded with redistribution wiring interconnections 680 and is located on a first horizontal surface 791 of the molded compound die frame 796; and a package substrate 200 bonded to a bonding structure 688 of the organic interposer 600, wherein an alignment mark region AMR including a local recessed region is located within an opening in a second horizontal surface 792 of the molded compound die frame 796.

[0130] In one embodiment, the device structure includes an additional semiconductor die 300 disposed over and adhered to the fan-out package 800. In one embodiment, the fan-out package 800 includes an interposer via (TIV) structure 786 extending vertically through the molded compound die frame 796; and the additional semiconductor die 300 is bonded to the TIV structure 786 through an array composed of solder material portions 390.

[0131] In one embodiment, the alignment mark region AMR has an area overlap with the additional semiconductor die 300 and has no area overlap with the at least one semiconductor die 700. In one embodiment, the device structure includes a lid structure 230, the lid structure 230 is adhered to the package substrate 200 and includes a horizontal cap portion, and the horizontal cap portion covers and covers the entirety composed of the at least one semiconductor die 700 and the alignment mark region AMR. In one embodiment, an alignment mark structure 20 is located within the local recessed region; and the horizontal cap portion is in direct contact with the alignment mark structure 20 or is adhered to the alignment mark structure 20 through an adhesive layer 233.

[0132] According to an aspect of the present disclosure, a method of forming a device structure includes: forming an alignment mark structure over a carrier wafer; placing the at least one semiconductor die over the carrier wafer using the alignment mark structure as a reference position for positioning the at least one semiconductor die; forming a molded compound matrix around the at least one semiconductor die and over the alignment mark structure; and forming a fan-out package by dividing the molded compound matrix, wherein the fan-out package includes the at least one semiconductor die, the alignment mark structure, and a molded compound die frame as a cut portion of the molded compound matrix.

[0133] In one embodiment, the alignment mark structure is formed by depositing a layer stack composed of a plurality of metallic material layers and patterning the layer stack composed of the plurality of metallic material layers. In one embodiment, the alignment mark structure is formed by depositing a dielectric material layer and patterning the dielectric material layer such that the sidewalls of the alignment mark structure have a taper angle in the range of 1 degree to 20 degrees with respect to the vertical direction. In one embodiment, a die attach film is further conformally formed over the alignment mark structure and over the carrier wafer, wherein the at least one semiconductor die is disposed over the die attach film. In one embodiment, it further includes: separating the carrier wafer from the assembly including the molded compound matrix, the at least one semiconductor die, and the alignment mark structure; and selectively removing the alignment mark structure relative to the material of the molded compound matrix.

[0134] Various embodiments of the present disclosure can be used to improve the positional accuracy and speed of pick-and-place operations for placing semiconductor die 700 and TIV structure 786 on carrier wafer 310. At least one alignment mark structure 20 located within the same unit area UA can be used to place each semiconductor die 700 and each TIV structure 786 within the unit area UA. Accordingly, the lateral displacement between each semiconductor die 700 and a reference point (i.e., the closest one among the at least one alignment mark structure 20) is less than the maximum lateral dimension of the unit area UA (e.g., the diagonal of a rectangular unit area UA). Similarly, the lateral displacement between each TIV structure 786 and a reference point (i.e., the closest one among the at least one alignment mark structure 20) is less than the maximum lateral dimension of the unit area UA. By using the alignment mark structure 20 of the present disclosure, the lateral displacement between the reference point and the components placed during the pick-and-place operation can be reduced, and the throughput and process yield of the pick-and-place operation can be improved.

[0135] The foregoing has outlined features of several embodiments in order that those skilled in the art may better understand the various aspects of the present disclosure. Each embodiment described using the term "comprises" inherently discloses additional embodiments in which, unless expressly disclosed otherwise herein, the term "consists essentially of" is used in place of or the term "consists of" is used in place of the term "comprises". Whenever two or more elements are listed as alternative elements in the same paragraph or different paragraphs, a Markush group including the list of the two or more elements is also implicitly disclosed. Whenever the auxiliary verb "can" is used in the present disclosure to describe the formation of an element or the performance of a processing step, embodiments in which such an element is not formed or such a processing step is not performed are also expressly contemplated, provided that the resulting device or apparatus can provide equivalent results. Thus, whenever the omission of the formation of an element or a processing step can provide the same result or an equivalent result, the auxiliary verb "can" applied to the formation of such an element or the performance of such a processing step should also be interpreted as "may" or be interpreted as "may" or "may not", and the equivalent results include slightly superior results and slightly inferior results. Those skilled in the art should understand that they can readily use the present disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent structures do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

Claims

1. A device structure comprising a fan-out package, characterized in that: The fan-out package comprises: a mold compound die frame laterally surrounding the at least one semiconductor die; and an organic interposer including a redistribution dielectric layer embedded with redistribution wiring interconnects and located on a first horizontal surface of the mold compound die frame, An alignment mark region including a localized recessed region is located within an opening in the second horizontal surface of the mold compound die frame.

2. The device structure according to claim 1, characterized in that: In a plan view along a direction perpendicular to the first horizontal surface, the alignment mark region does not have any area overlap with the at least one semiconductor die.

3. The device structure according to claim 1, characterized in that: The alignment mark structure is located in the local recessed area.

4. The device structure according to claim 3, characterized in that: The alignment mark structure includes a layer stack consisting of a plurality of metallic material layers including at least one horizontal interface between the plurality of metallic material layers.

5. The device structure according to claim 3, characterized in that: The alignment mark structure includes a dielectric material portion having a variable horizontal cross-sectional area that increases with vertical distance from a horizontal plane including the first horizontal surface.

6. The device structure according to claim 3, characterized in that: Sidewalls and a bottom surface of the alignment mark structure are in direct contact with the mold compound die frame.

7. The device structure according to claim 3, characterized in that: The alignment mark structure is spaced apart from the mold compound die frame by a die attach film including a polymer matrix layer and an adhesive layer.

8. A device structure, characterized in that: include: A fan-out package comprising a mold compound die frame, at least one semiconductor die laterally surrounded by the mold compound die frame, and an organic interposer including a redistribution dielectric layer embedded with redistribution wiring interconnects and located on a first horizontal surface of the mold compound die frame; as well as a packaging substrate, a bonding structure bonded to the organic interposer, An alignment mark region including a localized recessed region is located within an opening in the second horizontal surface of the mold compound die frame.

9. The device structure according to claim 8, characterized in that: Also included is a cover structure attached to the package substrate and including a horizontal cap portion overlying and covering the entirety of the at least one semiconductor die and the alignment mark region.

10. The device structure according to claim 9, characterized in that: An alignment mark structure is located within the local recessed area; and The horizontal cap portion is in direct contact with the alignment mark structure or is attached to the alignment mark structure through an adhesive layer.

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