Chip pin control circuit and electronic equipment
By designing the chip pin control circuit, switching the chip pin function mode is achieved using the switching switch, which solves the high temperature problem caused by the single driving chip function, and achieves both low power consumption and high-efficiency communication.
Patent Information
- Application Number
- CN202422384571.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-29
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-09-29
AI Technical Summary
In the prior art, the chip pin function of the driver chip is single, and the communication function is usually retained and the low current mode is abandoned, resulting in an increase in the temperature of the electronic device, affecting service life and system performance.
A chip pin control circuit is designed, through the first switching switch and the second switching switch, the control signal is received respectively to switch the functional mode of the chip pin, and the serial communication functional mode and the low-power functional mode are realized between different time periods.
The functional mode switching of chip pins between different time periods is realized, which not only meets serial communication control, but also reduces current input in low-power mode, avoids overheating of chips and electronic devices, extends service life and reduces system power consumption.
Smart Images
Figure CN223051657U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of electronic circuits, in particular to a chip pin control circuit and an electronic device. Background Technique
[0002] In the related art, a driver chip is an integrated circuit chip used to control and drive the operation of other electronic devices. In a driver chip, its chip pins may be dual-functional pins. For example, they can be used as communication function pins for transmitting communication signals and also as configuration pins for providing a low-current mode to the driver chip during other time periods.
[0003] In previous uses, for such special chip pins, generally only one of the dual functions is selected, and only one function of the chip pin is used, thereby reducing the design difficulty.
[0004] In the related art, the communication function of the chip pin is usually retained, while the low-current mode is discarded. However, it is found in use that if the holding current of the driver chip when it is in a static state does not decrease, the temperature of the electronic device connected thereto will be very high, resulting in serious overheating of the electronic device. On the one hand, the electronic device remaining at a high temperature all the time will affect its service life. On the other hand, maintaining a high current all the time will cause the power consumption of the entire electronic device to be relatively high. More importantly, the high temperature of the electronic device will affect the chips around it, raising the internal temperature of the entire system and ultimately affecting the performance of the surrounding devices.
[0005] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present utility model, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Utility Model
[0006] Aiming at the problems in the prior art, the purpose of the present utility model is to provide a chip pin control circuit and an electronic device, which overcome the technical problem of the single function of chip pins in the related art.
[0007] An embodiment of the present disclosure provides a chip pin control circuit, which includes: a first switching switch having a first control pin, a first input pin, and a first output pin. The first control pin is used to receive a first control signal and a second control signal. The first input pin is used to be coupled to a main control device, and the first output pin is coupled to a first chip pin;
[0008] The first switching switch is configured as:
[0009] When the first control pin receives the first control signal, it controls the connection between the first input pin and the first output pin, so that the first chip pin is configured in a serial communication function mode;
[0010] When the first control pin receives the second control signal, the second control signal is used to control the disconnection between the first input pin and the first output pin, so that the first chip pin is configured in the low-power function mode.
[0011] In some embodiments, the first switching switch further has a first pull-up pin, and the first pull-up pin is coupled to a first pull-up circuit;
[0012] The first switching switch is configured to: when the first control pin receives the second control signal, control the connection between the first input pin and the first pull-up pin.
[0013] In some embodiments, the chip pin control circuit further includes: a second switching switch and a third switching switch;
[0014] The second switching switch has a second control pin, a second input pin, and a second output pin. The second control pin is used to receive the first control signal and the second control signal. The second input pin is used to be coupled to the master device, and the second output pin is coupled to the second chip pin;
[0015] The second switching switch is configured to:
[0016] When the second control pin receives the first control signal, control the connection between the second input pin and the second output pin, so that the second chip pin is configured in the serial communication function mode;
[0017] When the second control pin receives the second control signal, control the disconnection between the second input pin and the second output pin, so that the second chip pin is configured in the low-power function mode;
[0018] The third switching switch is coupled between the first input pin and the second input pin and the master device, and the third switching switch is configured to be controlled to switch the coupling of the first input pin and the second input pin to the master device respectively.
[0019] In some embodiments, the second switching switch further has a second pull-up pin, and the second pull-up pin is coupled to a second pull-up circuit;
[0020] The second switching switch is configured to: when the second control pin receives the second control signal, control the connection between the second input pin and the second pull-up pin.
[0021] In some embodiments, the first control pin and the second control pin are connected.
[0022] In some embodiments, the third switching switch has a third control pin, a third input pin, a third output pin, and a fourth output pin;
[0023] The third control pin is used to receive a third control signal and a fourth control signal, the third input pin is used to connect to the main control device, the third output pin is coupled to the first input pin, and the fourth output pin is coupled to the second input pin;
[0024] The third switching switch is configured to:
[0025] When the third control pin receives the third control signal, control the connection between the third input pin and the third output pin, and when the first control pin receives the first control signal, control the connection between the first input pin and the first output pin, so that the first chip pin is configured in the serial communication function mode;
[0026] When the third control pin receives the fourth control signal, control the connection between the third input pin and the fourth output pin, and when the second control pin receives the first control signal, control the connection between the second input pin and the second output pin, so that the second chip pin is configured in the low-power function mode.
[0027] The embodiments of the present disclosure further provide an electronic device, which includes the chip pin control circuit of any of the above embodiments.
[0028] Optionally, the first chip pin is disposed on a motor drive chip.
[0029] The chip pin control circuit and the electronic device of the present utility model have the following advantages:
[0030] In the chip pin control circuit, the first switching switch is configured as follows: when the first control pin receives the first control signal, it controls the connection between the first input pin and the first output pin, so that the first chip pin is configured in the serial communication function mode; when the first control pin receives the second control signal, it controls the disconnection between the first input pin and the first output pin through the second control signal, so that the first chip pin is configured in the low power consumption function mode. The chip pin control circuit of this embodiment can enable the first chip pin to switch between the serial communication function mode and the low power consumption function mode at different time periods, which can not only realize the control of the driving chip based on serial communication, but also meet the low power consumption function mode without sacrificing one of the functions. In particular, in the low power consumption function mode, the current input from the first chip pin is pulled down, avoiding the temperature rise of the first driving chip and electronic devices where it is located, preventing the surrounding devices from being affected, increasing the service life of the corresponding electronic devices, and reducing the power consumption and temperature of the entire system. Moreover, the chip pin circuit design of this embodiment is simple and practical, with a low corresponding hardware cost. At the same time, in cooperation with programs such as the first control signal and the second control signal, it reduces the high complexity brought by pure hardware control. BRIEF DESCRIPTION OF THE DRAWINGS
[0031] Other features, objects, and advantages of the present utility model will become more apparent by reading the following detailed description of non-limiting embodiments with reference to the accompanying drawings.
[0032] Figure 1 One of the circuit structure diagrams showing the chip pin control circuit of the present disclosure embodiment.
[0033] Figure 2 Another circuit structure diagram showing the chip pin control circuit of the present disclosure embodiment.
[0034] Figure 3 Another circuit structure diagram showing the chip pin control circuit of the present disclosure embodiment.
[0035] Figure 4 Show Figure 3 The circuit diagram of the circuit structure diagram of the shown chip pin control circuit. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0036] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described can be combined in any suitable manner in one or more embodiments.
[0037] In addition, the drawings are only schematic illustrations of the present utility model and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus repeated descriptions thereof will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or implemented in one or more hardware modules or integrated circuits, or implemented in different networks and / or processor devices and / or microcontroller devices.
[0038] Figure 1 The circuit structure diagram of the chip pin control circuit provided by the embodiment of the present disclosure is shown as Figure 1 shown, and the chip pin control circuit includes: a first switching switch U1;
[0039] The first switching switch U1 has a first control pin 1a, a first input pin 1b, and a first output pin 1c. The first control pin 1a is used to receive a first control signal and a second control signal. The first input pin 1b is used to be coupled to a main control device, and the first output pin 1c is coupled to a first chip pin PDN_H;
[0040] The first switching switch U1 is configured as:
[0041] When the first control pin 1a receives the first control signal, it controls the connection between the first input pin 1b and the first output pin 1c, so that the first chip pin PDN_H is configured in a serial communication function mode;
[0042] When the first control pin 1a receives the second control signal, it controls the disconnection between the first input pin 1b and the first output pin 1c, so that the first chip pin PDN_H is configured in a low power consumption function mode.
[0043] The low power consumption function mode here refers to a relative mode. Compared with the connection between the first input pin 1b and the first output pin 1c, when the first input pin 1b and the first output pin 1c are disconnected, a relatively low current is output through the first output pin 1c, so that the current of the first driver chip connected to the first chip pin PDN_H is reduced to maintain low power consumption. Therefore, the "low" power consumption function mode here does not have a specific value.
[0044] The working principle of the above chip pin circuit of the embodiment of the present disclosure is:
[0045] The first input pin 1b is coupled to a main control device, the first output pin 1c is coupled to a first chip pin PDN_H, and the first chip pin PDN_H belongs to a first driver chip;
[0046] The first control signal and the second control signal are two different control signals. The first control signal controls the connection between the first input pin 1b and the first output pin 1c, and the second control signal controls the disconnection between the first input pin 1b and the first output pin 1c. The first input pin 1b is connected to the first output pin 1c, and a communication connection is established between the main control device and the first chip pin PDN_H, and data signals can be transmitted. The first input pin 1b is disconnected from the first output pin 1c, and the communication connection between the main control device and the first chip pin PDN_H is cut off. At this time, the first chip pin PDN_H receives a low current, and the first driver chip to which it is located maintains a low power consumption functional mode.
[0047] Therefore, the chip pin control circuit of the present embodiment can enable the first chip pin PDN_H to switch between the serial communication function mode and the low power consumption function mode at different time periods, which can realize the control of the driver chip based on the serial communication, and can also meet the low power consumption function mode without giving up one of the functions. In particular, in the low power consumption function mode, the current input from the first chip pin PDN_H is pulled down to avoid the temperature increase of the first driver chip and the electronic device where it is located, avoid the peripheral equipment from being affected, increase the service life of the corresponding electronic device, and reduce the power consumption temperature of the entire system. Moreover, the chip pin circuit design of the present embodiment is simple and practical, and the corresponding hardware cost is low. At the same time, it cooperates with the first control signal and the second control signal and other programs to reduce the high complexity brought by pure hardware control.
[0048] In one embodiment of the present disclosure, the first control signal pulls up the first control pin 1a to keep it at a high level, triggering the first input pin 1b to connect with the first output pin 1c. The second control signal pulls down the first control pin 1a to switch it to a low level, triggering the first input pin 1b to disconnect from the first output pin 1c.
[0049] like Figure 2 As shown, in an optional implementation, the first switch U1 further has a first pull-up pin 1d, and the first pull-up pin 1d is coupled to the first pull-up circuit SL1;
[0050] At this time, the first switch U1 is configured to control the first input pin 1b to be connected to the first pull-up pin 1d through the second control signal when the first control pin 1a receives the second control signal.
[0051] In this embodiment, when the first control pin 1 a receives the second control signal, the first input pin 1 b is disconnected from the first output pin 1 c and connected to the first pull-up pin 1 d .
[0052] Since the first input pin 1b is connected to the master device, to prevent the first input pin 1b from being floating and in an indeterminate state, the first pull-up circuit SL1 is used to keep the first input pin 1b in a determinate state, avoiding its floating and resulting in a high input impedance, being vulnerable to external noise interference, and causing the circuit to malfunction.
[0053] In this embodiment, the first switch U1 uses the SGM3157 switch chip. The SGM3157 is an analog switch based on the CMOS (full English text: Complementary Metal Oxide Semiconductor, Chinese: Complementary Metal Oxide Semiconductor) process, with good characteristics of low power consumption, low transmission delay, and low output impedance.
[0054] In an embodiment of the present disclosure, as Figure 3 shown, the chip pin control circuit further includes:
[0055] The second switch U2 and the third switch U3;
[0056] The second switch U2 has a second control pin 2a, a second input pin 2b, and a second output pin 2c. The second control pin 2a is used to receive the first control signal and the second control signal. The second input pin 2b is used to couple to the master device, and the second output pin 2c is coupled to the second chip pin PDN_V;
[0057] The second switch U2 is configured as:
[0058] When the second control pin 2a receives the first control signal, it controls the connection between the second input pin 2b and the second output pin 2c, so that the second chip pin PDN_V is configured in the serial communication function mode;
[0059] When the second control pin 2a receives the second control signal, it controls the disconnection between the second input pin 2b and the second output pin 2c, so that the second chip pin PDN_V is configured in the low power consumption function mode;
[0060] The third switch U3 is coupled between the first input pin 1b and the second input pin 2b and the master device. The third switch U3 is configured to be controlled to switch the coupling of the first input pin 1b and the second input pin 2b to the master device respectively.
[0061] The chip pin control circuit of this embodiment can achieve separate control of the dual-drive chip. Specifically, the third switch U3 is used to configure the dual-drive chip into the serial communication function mode respectively, so that the master device can control the first drive chip and the second drive chip respectively. At the same time, the first switch U1 and U2 can be switched to the low-power function mode simultaneously through the second control signal.
[0062] As Figure 3 shown, the first control pin 1a and the second control pin 2a are connected, so that both can receive the first control signal and the second control signal simultaneously, reducing unnecessary wiring.
[0063] In the embodiment of the present disclosure, as Figure 3 shown, the second switch U2 also has a second pull-up pin 2d, and the second pull-up pin 2d is coupled to the second pull-up circuit SL2;
[0064] The second switch U2 is configured to: when the second control pin 2a receives the second control signal, control the second input pin 2b to be connected to the second pull-up pin 2d.
[0065] In this embodiment, when the second control pin 2a receives the second control signal, the connection between the second input pin 2b and the second output pin 2c is switched off and the second input pin 2b is connected to the second pull-up pin 2d.
[0066] Since the second input pin 2b is connected to the master device, in order to avoid the second input pin 2b being floating and in an uncertain state, the second input pin 2b is kept in a definite state through the second pull-up circuit SL2, avoiding its floating and resulting in a high input impedance, being vulnerable to external noise interference, and causing the circuit to malfunction.
[0067] In this embodiment, the second switch U2 uses the SGM3157 switch chip. SGM3157 is an analog switch based on the CMOS (full English text: Complementary Metal Oxide Semiconductor, Chinese: Complementary Metal Oxide Semiconductor) process, and has good characteristics of low power consumption, low transmission delay and low output impedance.
[0068] As Figure 3 shown, the third switch U3 has a third control pin 3a, a third input pin 3b, a third output pin 3c and a fourth output pin 3d;
[0069] The third control pin 3a is used to receive a third control signal and a fourth control signal. The third input pin 3b is used to connect to a master device. The third output pin 3c is coupled to the first input pin 1b, and the fourth output pin 3d is coupled to the second input pin 2b;
[0070] The third switch U3 is configured as:
[0071] When the third control pin 3a receives the third control signal, it controls the third input pin 3b to be connected to the third output pin 3c, and when the first control pin 1a receives the first control signal, it controls the first input pin 1b to be connected to the first output pin 1c, so that the first chip pin PDN_H is configured in the serial communication function mode;
[0072] When the third control pin 3a receives the fourth control signal, it controls the third input pin 3b to be connected to the fourth output pin 3d, and when the second control pin 2a receives the first control signal, it controls the second input pin 2b to be connected to the second output pin 2c, so that the second chip pin PDN_V is configured in the low power consumption function mode.
[0073] In this embodiment, the third switch U3 has the same structure as the first switch U1 and the second switch U2. By cooperating with each other, the dual-function switching of the dual-drive chip is realized.
[0074] In one embodiment, both the first drive chip and the second drive chip are motor drive chips. In other embodiments, the first drive chip and the second drive chip may also be drive chips of other electronic devices, which are not limited herein.
[0075] Next, in conjunction with Figure 3 the specific circuit diagram corresponding to the chip pin control circuit shown, the specific implementation manner of the chip pin control circuit will be elaborated in detail.
[0076] As Figure 4 the circuit diagram of the chip pin control circuit shown, the first switch U1, the second switch U2, and the third switch U3 are all SGMSGM3157 switch chips. Taking the first switch U1 as an example, it has an S pin, a B1 pin, a B0 pin, and an A pin, where the S pin corresponds to Figure 1 the first control pin 1a in Figure 1 the A pin corresponds to Figure 1 the first input pin 1b in Figure 1 the first output pin 1c inFigure 2 The first pull-up circuit SL1 in
[0077] For the corresponding relationship between the corresponding pins of the second switching switch U2 and the third switching switch U3 and Figures 1 - 3 the corresponding pins in each circuit structure in , reference can be made to the content of the first switching switch U1, which is not limited here.
[0078] Continue as Figure 4 shown, the chip pin control circuit supports the master device to control two identical motor drive chips, where the first chip pin PDN_H corresponds to the first motor drive chip, and the second chip pin PDN_V corresponds to the second motor drive chip. Among them, PDN_H and PDN_V respectively correspond to the rotation directions around different axes in the same scenario. For example, H is the abbreviation of horizontal, and V is the abbreviation of vertical. The horizontal direction and the vertical direction are just a description, and they may not be the real "horizontal" or "vertical" in the specific scenario.
[0079] In the serial communication function mode, the S pins (corresponding to the signal PDN_CTL) of the first switching switch U1 and the second switching switch U2 are pulled high (corresponding to the first control signal above) through the control program. At this time, the A pin (corresponding to the signal UART_RX1) of the first switching switch U1 is connected to the B1 pin (corresponding to the signal UART_RXH), and the A pin (corresponding to the signal UART_RX2) of the second switching switch U2 is connected to the B1 pin (corresponding to the signal UART_RXV). At the same time, the S pin (corresponding to the signal UART_Driver_SEL) of the third switching switch U3 is pulled high (corresponding to the third control signal above) through the control software. At this time, the A pin (corresponding to the signal UART_RX) of the third switching switch U3 is connected to the B1 pin (corresponding to the signal UART_RX1), and the A pin (corresponding to the signal UART_RX1) of the first switching switch U1 is connected to the B1 pin (corresponding to the signal UART_RXH). The master device can then perform data communication with the first chip pin PDN_H of the first drive motor. If the master device needs to control the second motor drive chip, the signal UART_Driver_SEL is pulled low through the control software. At this time, the A pin (corresponding to the signal UART_RX) of the third switching switch U3 is connected to the B0 pin (corresponding to the signal UART_RX2), and the A pin (corresponding to the signal UART_RX2) of the second switching switch U2 is connected to the B1 pin (corresponding to the signal UART_RXV). The master device can then perform data communication with the second chip pin PDN_V.
[0080] If the control of the first motor and / or the second motor is completed and serial communication is no longer required, and the motor needs to maintain its current state, the functions of the first chip pin PDN_H and the second chip pin PDN_V are switched to the low-power function mode at this time. At this time, by controlling the software to switch the signal PDN_CTL to a low level (corresponding to the second control signal above), the A pin (signal UART_RX1) of the first switch U1 is connected to the B0 pin, and the A pin (corresponding to the signal UART_RX2) of the second switch U2 is connected to the B0 pin. The B0 pin is default in a pulled-high state, so the serial port of the master device can be modified to a pulled-high state. At the same time, the B1 pin (corresponding to the signal UART_RXH) of the first switch U1 and the B1 pin (corresponding to the signal UART_RXV) of the second switch U2 are no longer connected to the serial port of the master device. At this time, the first chip pin PDN_H corresponding to the first driving motor and the second chip pin PDN_V corresponding to the second driving motor are pulled low by the resistors R8 and R10, and both the first driving motor and the second driving motor enter the low-power function mode with reduced holding current.
[0081] In this way, the embodiment of the present disclosure realizes controlling the driving chips of the dual motors through the serial communication function mode in different time periods, and at the same time, when the low-power function mode with lower holding current is required, the chip pins of each driving chip can also be pulled low to implement the corresponding low-power function.
[0082] The embodiment of the present disclosure also provides an electronic device, which includes Figures 1 - 4 the chip pin control circuit of any one of the above embodiments.
[0083] In one embodiment, the electronic device may be a driving motor, and the chip pin control circuit is integrated in the driving motor. In another embodiment, the electronic device may also be a master device, and in this way, the chip pin control circuit is integrated in the master device.
[0084] In an application scenario, the electronic device is used in a video conferencing system and is connected between the master device and the driving motor for driving the image acquisition device to rotate. For example, in combination with the above content, the camera is configured with a first driving motor and a second driving motor. The first driving motor corresponds to the first chip pin PDN_H above, and the second driving motor corresponds to the second chip pin PDN_V above. In this way, the first driving motor is used to control the rotation of the camera relative to the horizontal plane, and the second driving motor is used to control the rotation of the camera relative to the vertical plane.
[0085] This is an example, and the electronic device of the present embodiment can also be applied in other application scenarios.
[0086] The above content is a further detailed description of the present utility model in combination with specific preferred embodiments. It cannot be determined that the specific implementation of the present utility model is only limited to these descriptions. For those of ordinary skill in the technical field to which the present utility model pertains, without departing from the concept of the present utility model, several simple deductions or substitutions can still be made, and all should be regarded as belonging to the protection scope of the present utility model.
Claims
1. A chip pin control circuit, characterized in that: include: A first switch having a first control pin, a first input pin and a first output pin, wherein the first control pin is used to receive a first control signal and a second control signal, the first input pin is used to couple to a main control device, and the first output pin is coupled to a first chip pin; The first switch is configured as follows: When the first control pin receives the first control signal, the first input pin is controlled to be connected to the first output pin, so that the first chip pin is configured as a serial port communication function mode; When the first control pin receives the second control signal, the first input pin is disconnected from the first output pin through the second control signal, so that the first chip pin is configured in a low power consumption function mode.
2. The chip pin control circuit according to claim 1, characterized in that: The first switch further has a first pull-up pin, and the first pull-up pin is coupled to a first pull-up circuit; The first switch is configured to control the first input pin to be connected to the first pull-up pin when the first control pin receives the second control signal.
3. The chip pin control circuit according to claim 1, characterized in that: The chip pin control circuit further includes: a second switch and a third switch; The second switch has a second control pin, a second input pin and a second output pin, the second control pin is used to receive the first control signal and the second control signal, the second input pin is used to couple to the main control device, and the second output pin is coupled to the second chip pin; The second switch is configured as follows: When the second control pin receives the first control signal, the second input pin is controlled to be connected to the second output pin, so that the second chip pin is configured as the serial port communication function mode; When the second control pin receives the second control signal, the second input pin is controlled to be disconnected from the second output pin, so that the second chip pin is configured to the low power consumption function mode; The third switch is coupled between the first input pin, the second input pin and the master device, and the third switch is configured to control and switch the first input pin and the second input pin to be coupled to the master device respectively.
4. The chip pin control circuit according to claim 3, characterized in that: The second switch further has a second pull-up pin, and the second pull-up pin is coupled to a second pull-up circuit; The second switch is configured to control the second input pin to be connected to the second pull-up pin when the second control pin receives the second control signal.
5. The chip pin control circuit according to claim 3, characterized in that: The first control pin is connected to the second control pin.
6. The chip pin control circuit according to claim 3, characterized in that: The third switch has a third control pin, a third input pin, a third output pin and a fourth output pin; The third control pin is used to receive a third control signal and a fourth control signal, the third input pin is used to connect to the main control device, the third output pin is coupled to the first input pin, and the fourth output pin is coupled to the second input pin; The third switch is configured as follows: When the third control pin receives the third control signal, the third input pin is controlled to be connected to the third output pin, and when the first control pin receives the first control signal, the first input pin is controlled to be connected to the first output pin, so that the first chip pin is configured as the serial port communication function mode; When the third control pin receives the fourth control signal, the third input pin is controlled to be connected to the fourth output pin, and when the second control pin receives the first control signal, the second input pin is controlled to be connected to the second output pin, so that the second chip pin is configured to the low power consumption functional mode.
7. An electronic device, characterized in that: A chip pin control circuit comprising any one of claims 1-6.
8. The electronic device according to claim 7, characterized in that: The first chip pin is arranged on the motor driving chip.