Clock synchronization device for I2S recording sound card

Abstract

The utility model discloses a clock synchronization device for an I2S recording sound card, which belongs to the field of AIOT equipment and comprises AIOT equipment, a sound card chip, a phase-locked loop clock frequency multiplier PLL and a computer. The AIOT equipment is in communication connection with the input end of the sound card chip, and the output end of the sound card chip is in communication connection with the computer; the AIOT equipment is in communication connection with a PLL (Phase Locked Loop) clock frequency multiplier; a system clock is arranged in the sound card chip; the phase-locked loop clock frequency multiplier PLL is in communication connection with a system clock in the sound card chip. According to the utility model, the phase-locked loop clock frequency multiplier PLL is introduced, and the BCLK signal of the AIOT equipment is subjected to frequency multiplication and then is used as the system clock of the sound card chip, so that clock synchronization of the AIOT equipment and the sound card chip is realized, the problems of audio data loss, distortion and the like caused by clock asynchronism in the audio data transmission process are effectively solved, and the audio data transmission efficiency is improved. And the transmission quality and reliability of the audio data are improved.

Description

Technical Field

[0001] The utility model relates to the field of AIOT devices, and specifically to a clock synchronization device for an I2S recording sound card. Background Art

[0002] By introducing artificial intelligence technology, AIOT devices can perform higher-level processing and analysis on the data generated by the Internet of Things. This not only improves the intelligence level of the devices but also enables more efficient and convenient services. AIOT devices can monitor and optimize various industrial and production processes in real time. The application of AIOT devices in fields such as retail and manufacturing has significantly improved operational efficiency. With the development of AIOT devices, the rise of edge computing and edge intelligence has further enhanced local data processing capabilities, contributing to the enhancement of data security and privacy protection. AIOT devices can be applied to multiple fields, such as intelligent manufacturing, smart home, and intelligent transportation. Their diverse application scenarios enable AIOT devices to play an important role in various fields.

[0003] When an AIOT device collects recorded audio, an I2S-to-UAC sound card is often used for recording. The rhythm of UAC data transmission usually transmits audio according to the crystal oscillator rhythm of the sound card. If the frequency deviation between the crystal oscillator and the I2S clock and the crystal oscillator is large, there will be a difference between the amount of data transmitted by UAC and the amount of data transmitted by I2S, resulting in a longer or shorter duration of the recorded audio and affecting the recording quality. Summary of the Utility Model

[0004] Regarding the above problems existing in the prior art, the purpose of the present utility model is to provide a clock synchronization device for an I2S recording sound card to solve the recording quality problem caused by the difference between the amount of data transmitted by UAC and the amount of data transmitted by I2S in an AIOT device.

[0005] To achieve the above purpose, the present utility model provides the following technical solutions:

[0006] A clock synchronization device for an I2S recording sound card includes an AIOT device, a sound card chip, a phase-locked loop clock multiplier PLL, and a computer; the input ends of the AIOT device and the sound card chip are communicatively connected, the output end of the sound card chip is communicatively connected to the computer; the AIOT device is communicatively connected to the phase-locked loop clock multiplier PLL; a system clock is provided inside the sound card chip; the phase-locked loop clock multiplier PLL is communicatively connected to the system clock inside the sound card chip.

[0007] As a further aspect of the present utility model: The signals communicatively transmitted between the AIOT device and the sound card chip are a data signal DATA, a frame time signal LRCLK, and a bit clock signal BCLK.

[0008] As a further solution of the present utility model: The sound card chip includes a main chip U1, a chip U2, a chip U3, and a chip U4. One end of the pin 48 of the main chip U1 is connected to one end of the inductor L1. The other end of the inductor L1 is simultaneously connected to the pin 46 of the main chip U1 and one end of the capacitor C19. The other end of the capacitor C19 is connected to the pin 47 of the main chip U1, and the pin 47 of the main chip U1 is grounded; both ends of the capacitor C19 are connected in parallel with the capacitor C20; one end of the pin 24 of the main chip U1 is connected to one end of the capacitor C24, and the other end of the capacitor C24 is grounded;

[0009] The pin 56 of the main chip U1 is connected to the pin 1 of the chip U2, the pin 55 of the main chip U1 is connected to the pin 2 of the chip U2, the pin 54 of the main chip U1 is connected to the pin 3 of the chip U2, the pin 60 of the main chip U1 is connected to the pin 5 of the chip U2, the pin 59 of the main chip U1 is connected to the pin 6 of the chip U2, the pin 58 of the main chip U1 is connected to the pin 7 of the chip U2, and the pin 4 of the chip U2 is grounded;

[0010] One end of the pin 15 of the main chip U1 is connected to one end of the resistor R15, and the other end of the resistor R15 is connected to the pin 2 of the chip U3; the pin 1 of the chip U3 is grounded;

[0011] One end of the pin 30 of the main chip U1 is connected to one end of the capacitor C11, and the other end of the capacitor C11 is connected to the connection terminal AGND; both the pin 28 and the pin 29 of the main chip U1 are connected to one end of the capacitor C12, and the other end of the capacitor C12 is simultaneously connected to the pin 27 of the main chip U1 and the connection terminal AGND; the pin 6 of the chip U4 is connected to the connection terminal AGND; one end of the pin 4 of the chip U4 is connected to one end of the capacitor C42, and the other end of the capacitor C42 is grounded; the pin 5 of the chip U4 is simultaneously connected to one end of the capacitor C49 and one end of the resistor R33; the other end of the resistor R33 is simultaneously connected to the pin 11 of the chip U4 and one end of the capacitor C50, and the other ends of the capacitor C49 and the capacitor C50 are both grounded; the pins 2 and 3 of the chip U4 are grounded.

[0012] As a further solution of the present utility model: The phase-locked loop clock multiplier PLL includes a power supply circuit, an output clock buffer circuit, a feedback circuit counting and frequency dividing logic circuit, a PLL circuit, a phase-locked loop feedback circuit, and an input clock configuration switch circuit; The power supply circuit includes a chip U5. The pin 1 of the chip U5 is grounded. The pins 2 and 4 of the chip U5 are both connected to the power supply 3V3. The pin 2 of the chip U5 is connected to one end of the capacitor C13, and the other end of the capacitor C13 is grounded; both ends of the capacitor C13 are connected in parallel with both ends of the capacitor C58; the pin 3 of the chip U5 is connected to the power supply VCC —For the 5V connection, pin 3 of chip U5 is connected to one end of capacitor C61 and one end of capacitor C62 at the same time. The other ends of capacitor C61 and capacitor C62 are both grounded.

[0013] As a further solution of the present utility model: The output clock buffer circuit includes chip U6. Pin 1 of chip U6 is connected to the power supply 3V3. Pin 1 of chip U6 is connected to one end of capacitor C56, and the other end of capacitor C56 is grounded; both ends of capacitor C56 and both ends of capacitor C59 are connected in parallel; Pin 3 of chip U6 is connected to one end of resistor R43, and the other end of resistor R43 is connected to pin 1 of chip U6; Pin 4 of chip U6 is grounded; Pin 5 of chip U6 is connected to one end of resistor R44, and the other end of resistor R44 is connected to pin 23 of the main chip U1 in the sound card chip;

[0014] The feedback circuit counting and frequency dividing logic circuit includes chip U7. Pin 14 of chip U7 is connected to the power supply 3V3. Pin 14 of chip U6 is connected to one end of capacitor C57, and the other end of capacitor C57 is grounded; both ends of capacitor C57 and both ends of capacitor C60 are connected in parallel;

[0015] The PLL circuit includes chip U8. Pin 4 of chip U8 is connected to pin 2 of chip U6 in the output clock buffer circuit; Pins 5 and 8 of chip U8 are both grounded; Pin 6 of chip U8 is connected to one end of capacitor C68, and the other end of capacitor C68 is connected to pin 7 of chip U8; Pin 14 of chip U8 is connected to one end of resistor R45, and the other end of resistor R45 is connected to pin 63 of the main chip U1 in the sound card chip; Pin 13 of chip U8 is connected to one end of resistor R46, and the other end of resistor R46 is connected to pin 9 of chip U8 and one end of capacitor C67 at the same time. The other end of capacitor C67 is connected in series with resistor R48, resistor R47, and pin 11 of chip U8 in sequence. Capacitor C69 is connected in parallel across resistor R48; The connection line between resistor R48 and resistor R47 is connected to the ground wire; Pin 16 of chip U8 is connected to the power supply 3V3. Pin 16 of chip U8 is connected to one end of capacitor C64, and the other end of capacitor C64 is grounded; both ends of capacitor C64 and both ends of capacitor C66 are connected in parallel;

[0016] The phase-locked loop feedback circuit includes chip U9. Pin 1 of chip U9 is connected to pin 4 of chip U8 in the PLL circuit; pin 2 and pin 12 of chip U9 are connected to pin 3 of chip U8; pin 4 of chip U9 is connected to pin 1, pin 4, and pin 12 of chip U7 in the feedback circuit counting and frequency dividing logic circuit; pin 5 of chip U9 is connected to pin 2 and pin 10 of chip U7; pin 6 and pin 13 of chip U9 are connected to pin 5 of chip U7; pin 7 of chip U9 is grounded; pin 10 of chip U9 is connected to pin 13 of chip U7; pin 11 of chip U9 is connected to pin 9 of chip U7; pin 14 of chip U9 is connected to the 3V3 power supply. Pin 14 of chip U9 is connected to one end of capacitor C63, and the other end of capacitor C63 is grounded; both ends of capacitor C63 and both ends of capacitor C65 are connected in parallel.

[0017] As a further solution of the present invention: The input clock configuration switch circuit includes switch SW2. Pin 1 of switch SW2 is connected to pin 3 of chip U7 in the feedback circuit counting and frequency dividing logic circuit; pin 2 of switch SW2 is connected to pin 6 of U7; pin 3 of switch SW2 is connected to pin 8 of U7; pin 4 of switch SW2 is connected to pin 11 of U7; pin 5, pin 6, pin 7, and pin 8 of switch SW2 are all connected to pin 3 of chip U8 in the PLL circuit.

[0018] As a further solution of the present invention: The output end of the sound card chip is communicatively connected to a computer through a UAC interface, and the sound card chip is an I2S sound card.

[0019] As a further solution of the present invention: The signal transmitted between the AIOT device and the phase-locked loop clock multiplier PLL is the bit clock signal BCLK.

[0020] As a further solution of the present invention: The clock frequency between the phase-locked loop clock multiplier PLL and the system clock is an integer multiple of the input BCLK signal frequency; the system clock of the sound card chip receives the clock signal generated by the phase-locked loop clock multiplier PLL and is synchronized with the clock signal of the AIOT device.

[0021] As a further solution of the present invention: The AIOT device is any one of a smart speaker, a smart home device, or an Internet of Things audio device.

[0022] Compared with the prior art, the beneficial effects of the present invention are:

[0023] By introducing a phase-locked loop clock multiplier PLL, the utility model multiplies the BCLK signal of the AIOT device and uses it as the system clock of the sound card chip, achieving clock synchronization between the AIOT device and the sound card chip, effectively solving problems such as audio data loss and distortion caused by clock asynchronization during the audio data transmission process, and improving the transmission quality and reliability of audio data. Description of the Drawings

[0024] Figure 1 It is a system framework diagram of a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0025] Figure 2 It is a connection diagram of the main chip U1 pins of the sound card chip in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0026] Figure 3 It is a connection diagram of the chip U2 pins of the sound card chip in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0027] Figure 4 It is a connection diagram of the chip U3 pins of the sound card chip in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0028] Figure 5 It is a connection diagram of the chip U4 pins of the sound card chip in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0029] Figure 6 It is a power supply circuit diagram of the phase-locked loop clock multiplier PLL in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0030] Figure 7 It is an output clock buffer circuit diagram of the phase-locked loop clock multiplier PLL in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0031] Figure 8 It is a feedback circuit counting and frequency dividing logic circuit in the phase-locked loop clock multiplier PLL in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0032] Figure 9 It is a PLL circuit diagram of the phase-locked loop clock multiplier PLL in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0033] Figure 10 It is a phase-locked loop feedback circuit diagram of the phase-locked loop clock multiplier PLL in a clock synchronization device for an I2S recording sound card disclosed in the embodiment.

[0034] Figure 11The circuit diagram of the input clock configuration switch in the phase-locked loop clock multiplier PLL of a clock synchronization device for an I2S recording sound card disclosed in the embodiment. Detailed implementation

[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention; obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative work shall fall within the protection scope of the present invention.

[0036] In the description of the present invention, it should be noted that unless otherwise clearly defined and limited, the terms "installed", "provided with", "connected", and "connected" should be understood in a broad sense; for example, it can be a fixed connection, a detachable connection, or an integral connection, it can be a mechanical connection, an electrical connection, a direct connection, or an indirect connection through an intermediate medium, and it can be the communication between two elements inside. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0037] Please refer to Figure 1 , a clock synchronization device for an I2S recording sound card, including an AIOT device, a sound card chip, a phase-locked loop clock multiplier PLL, and a computer;

[0038] The AIOT device is communicatively connected to the input end of the sound card chip through the data signal DATA, the frame time signal LRCLK, and the bit clock signal BCLK, and the output end of the sound card chip is communicatively connected to the computer through the UAC interface;

[0039] The AIOT device is communicatively connected to the phase-locked loop clock multiplier PLL through the bit clock signal BCLK;

[0040] The phase-locked loop clock multiplier PLL is communicatively connected to the system clock in the sound card chip;

[0041] The AIOT device transmits audio data to the sound card chip through the DATA signal, the LRCLK signal, and the BCLK signal; the sound card chip receives the audio data and converts it into the UAC format and transmits it to the computer. At the same time, the AIOT device transmits the BCLK signal to the phase-locked loop clock multiplier PLL. The phase-locked loop clock multiplier PLL generates a system clock signal synchronized with the clock of the AIOT device according to the received BCLK signal and transmits it to the sound card chip. The sound card chip uses the system clock signal synchronized with the clock of the AIOT device to process the audio data, thereby ensuring the synchronization of the audio data transmission.

[0042] AIOT devices are the sources of audio data, which can be smart speakers, smart home devices, etc. AIOT devices transmit audio data to the sound card chip through the I2S protocol. The I2S protocol uses three signals for data transmission:

[0043] DATA signal: Transmits audio data. LRCLK signal: Indicates the left and right channels. BCLK signal: Bit clock signal, used to synchronize data transmission.

[0044] The sound card chip is responsible for receiving the audio data transmitted by the AIOT device and converting it into UAC format for transmission to the computer. The sound card chip contains a system clock inside, which is used to control the processing of audio data.

[0045] The phase-locked loop clock multiplier PLL receives the BCLK signal of the AIOT device and generates a system clock signal synchronized with the clock of the AIOT device. The phase-locked loop clock multiplier PLL synchronizes the output clock with the input clock by adjusting its frequency and phase.

[0046] The computer receives the audio data transmitted by the sound card chip through the UAC interface and performs further processing or storage.

[0047] As Figures 2 - 5 shown, the sound card chip includes a main chip U1, a chip U2, a chip U3, and a chip U4. One end of pin 48 of the main chip U1 is connected to one end of an inductor L1. The other end of the inductor L1 is simultaneously connected to pin 46 of the main chip U1 and one end of a capacitor C19. The other end of the capacitor C19 is connected to pin 47 of the main chip U1, and pin 47 of the main chip U1 is grounded; both ends of the capacitor C19 are connected in parallel with a capacitor C20; one end of pin 24 of the main chip U1 is connected to one end of a capacitor C24, and the other end of the capacitor C24 is grounded;

[0048] Pin 56 of the main chip U1 is connected to pin 1 of the chip U2. Pin 55 of the main chip U1 is connected to pin 2 of the chip U2. Pin 54 of the main chip U1 is connected to pin 3 of the chip U2. Pin 60 of the main chip U1 is connected to pin 5 of the chip U2. Pin 59 of the main chip U1 is connected to pin 6 of the chip U2. Pin 58 of the main chip U1 is connected to pin 7 of the chip U2, and pin 4 of the chip U2 is grounded;

[0049] One end of pin 15 of the main chip U1 is connected to one end of a resistor R15, and the other end of the resistor R15 is connected to pin 2 of the chip U3; pin 1 of the chip U3 is grounded;

[0050] Pin 30 of the main chip U1 is connected to one end of the capacitor C11, and the other end of the capacitor C11 is connected to the terminal AGND; pins 28 and 29 of the main chip U1 are both connected to one end of the capacitor C12, and the other end of the capacitor C12 is simultaneously connected to pin 27 of the main chip U1 and the terminal AGND; pin 6 of the chip U4 is connected to the terminal AGND; pin 4 of the chip U4 is connected to one end of the capacitor C42, and the other end of the capacitor C42 is grounded; pin 5 of the chip U4 is simultaneously connected to one end of the capacitor C49 and one end of the resistor R33; the other end of the resistor R33 is simultaneously connected to pin 11 of the chip U4 and one end of the capacitor C50, and the other ends of the capacitor C49 and the capacitor C50 are both grounded; pins 2 and 3 of the chip U4 are grounded;

[0051] The model of the chip U2 is GD25Q64ESIG; the model of the chip U3 is SGM803-TXN3L / TR; the model of the chip U4 is LPA4722AQVF;

[0052] As Figures 6 - 11 shown, the phase-locked loop clock multiplier PLL includes a power supply circuit, an output clock buffer circuit, a feedback circuit counting and frequency dividing logic circuit, a PLL circuit, a phase-locked loop feedback circuit, and an input clock configuration switch circuit;

[0053] The power supply circuit includes the chip U5. Pin 1 of the chip U5 is grounded. Pins 2 and 4 of the chip U5 are both connected to the power supply 3V3. Pin 2 of the chip U5 is connected to one end of the capacitor C13, and the other end of the capacitor C13 is grounded; both ends of the capacitor C13 and both ends of the capacitor C58 are connected in parallel; pin 3 of the chip U5 is connected to the power supply VCC — 5V. Pin 3 of the chip U5 is simultaneously connected to one end of the capacitor C61 and one end of the capacitor C62, and the other ends of the capacitor C61 and the capacitor C62 are both grounded;

[0054] The output clock buffer circuit includes the chip U6. Pin 1 of the chip U6 is connected to the power supply 3V3. Pin 1 of the chip U6 is connected to one end of the capacitor C56, and the other end of the capacitor C56 is grounded; both ends of the capacitor C56 and both ends of the capacitor C59 are connected in parallel; pin 3 of the chip U6 is connected to one end of the resistor R43, and the other end of the resistor R43 is connected to pin 1 of the chip U6; pin 4 of the chip U6 is grounded; pin 5 of the chip U6 is connected to one end of the resistor R44, and the other end of the resistor R44 is connected to pin 23 of the main chip U1 in the sound card chip;

[0055] The feedback circuit counting and frequency dividing logic circuit includes the chip U7. Pin 14 of the chip U7 is connected to the power supply 3V3. Pin 14 of the chip U6 is connected to one end of the capacitor C57, and the other end of the capacitor C57 is grounded; both ends of the capacitor C57 and both ends of the capacitor C60 are connected in parallel;

[0056] The PLL circuit includes chip U8. Pin 4 of chip U8 is connected to pin 2 of chip U6 in the output clock buffer circuit; pins 5 and 8 of chip U8 are both grounded; pin 6 of chip U8 is connected to one end of capacitor C68, and the other end of capacitor C68 is connected to pin 7 of chip U8; pin 14 of chip U8 is connected to one end of resistor R45, and the other end of resistor R45 is connected to pin 63 of the main chip U1 in the sound card chip; pin 13 of chip U8 is connected to one end of resistor R46, and the other end of resistor R46 is simultaneously connected to pin 9 of chip U8 and one end of capacitor C67. The other end of capacitor C67 is connected in series with resistor R48, resistor R47, and pin 11 of chip U8 in sequence. Capacitor C69 is connected in parallel across resistor R48; the connection line between resistor R48 and resistor R47 is connected to the ground wire; pin 16 of chip U8 is connected to the 3V3 power supply. Pin 16 of chip U8 is connected to one end of capacitor C64, and the other end of capacitor C64 is grounded; both ends of capacitor C64 and both ends of capacitor C66 are connected in parallel;

[0057] The phase-locked loop feedback circuit includes chip U9. Pin 1 of chip U9 is connected to pin 4 of chip U8 in the PLL circuit; pins 2 and 12 of chip U9 are connected to pin 3 of chip U8; pin 4 of chip U9 is connected to pins 1, 4, and 12 of chip U7 in the feedback circuit counting and frequency-dividing logic circuit; pin 5 of chip U9 is connected to pins 2 and 10 of chip U7; pins 6 and 13 of chip U9 are connected to pin 5 of chip U7; pin 7 of chip U9 is grounded; pin 10 of chip U9 is connected to pin 13 of chip U7; pin 11 of chip U9 is connected to pin 9 of chip U7;

[0058] Pin 14 of chip U9 is connected to the 3V3 power supply. Pin 14 of chip U9 is connected to one end of capacitor C63, and the other end of capacitor C63 is grounded; both ends of capacitor C63 and both ends of capacitor C65 are connected in parallel;

[0059] The input clock configuration switch circuit includes switch SW2. Pin 1 of switch SW2 is connected to pin 3 of chip U7 in the feedback circuit counting and frequency-dividing logic circuit; pin 2 of switch SW2 is connected to pin 6 of U7; pin 3 of switch SW2 is connected to pin 8 of U7; pin 4 of switch SW2 is connected to pin 11 of U7; pins 5, 6, 7, and 8 of switch SW2 are all connected to pin 3 of chip U8 in the PLL circuit;

[0060] The phase-locked loop clock multiplier PLL is a key component in the present utility model. The following factors need to be considered in its design: The PLL needs to be able to handle the BCLK signal frequency range output by the AIOT device. The PLL needs to generate a frequency compatible with the system clock of the sound card chip. The output clock of the PLL needs to have low phase noise to ensure the quality of audio data. The PLL needs to quickly lock to the input clock to reduce synchronization delay. The phase-locked loop clock multiplier PLL includes a phase detector, a low-pass filter, and a voltage-controlled oscillator, which are used to achieve the frequency and phase synchronization of the input BCLK signal and the output system clock signal.

[0061] The output clock frequency of the phase-locked loop clock multiplier PLL is an integer multiple of the input BCLK signal frequency, and the phase is synchronized with the input BCLK signal.

[0062] The system clock of the sound card chip is usually provided by a crystal oscillator or an external clock source. In the present utility model, the system clock is generated by the PLL and synchronized with the BCLK signal of the AIOT device. This requires that the sound card chip can accept an external system clock input and perform clock distribution and synchronization internally. The sound card chip uses the system clock signal generated by the phase-locked loop clock multiplier PLL for audio data processing to ensure synchronization with the clock of the AIOT device.

[0063] The sound card chip communicates with the computer through the UAC interface. UAC is a standard protocol for audio data transmission in USB devices. The sound card chip needs to support the UAC protocol and convert the audio data into the UAC format for transmission to the computer.

[0064] The AIOT device communicates with the sound card chip through the I2S interface. I2S (Inter-IC Sound) is a serial bus standard for communication between digital audio devices. The AIOT device needs to support the I2S protocol and generate DATA, LRCLK, and BCLK signals. The AIOT device, the sound card chip, and the phase-locked loop clock multiplier PLL are integrated into the same hardware module to reduce signal transmission delay and noise interference.

[0065] When the AIOT device collects recorded audio, an I2S-to-UAC sound card is often used for recording. The rhythm of UAC data transmission is usually based on the crystal oscillator rhythm of the sound card for transmitting audio. If the frequency deviation between the crystal oscillator and the I2S clock and the crystal oscillator is large, there will be a difference in the amount of data transmitted by UAC and the amount of data transmitted by I2S, which will cause the recorded audio duration to become longer or shorter. In order to maintain the recording rhythm synchronization, the I2S clock needs to be synchronized to the sound card so that the I2S transmission rate is consistent with the UAC transmission rate.

[0066] The AIoT device collects audio through an I2S sound card. The clock after multiplying the BCLK in its I2S bus is used as the system clock input of the sound card. If the frequency deviation of the multiplied clock is consistent with that of the BCLK of I2S, the transmission rate of I2S data can be made consistent with the UAC transmission rate of the sound card, effectively avoiding the problems of the lengthening and shortening of the data collection duration of the I2S sound card.

[0067] The phase-locked loop clock multiplier PLL is a phase-locked loop clock multiplier. The PLL (phase-locked loop) multiplication can be realized through a VCO chip and a frequency division chip, and the clock frequency required by the sound card can be output by multiplication.

[0068] Clock synchronization mainly changes the asynchronous clocks of the I2S clock and the sound card clock into synchronous clocks to avoid the problem of mismatched data transmission rhythms.

[0069] Data is transmitted between the sound card and the computer according to the UAC program of the sound card. The computer stores the data transmitted via USB. Keeping the I2S transmission clock synchronized with the sound card can ensure that the amount of data stored in the computer is the same as the amount of data collected by the AIoT device.

[0070] The working principle of the present utility model is as follows: When the AIoT device collects recorded audio, an I2S-to-UAC sound card is often used for recording. The rhythm of UAC data transmission usually transmits audio according to the rhythm of the sound card crystal oscillator. If the frequency deviation between the crystal oscillator and the I2S clock and the crystal oscillator is relatively large, there will be a difference between the amount of data transmitted by UAC and the amount of data transmitted by I2S, which will cause the recorded audio duration to become longer or shorter. In order to keep the recording rhythm synchronized, the I2S clock needs to be synchronized to the sound card to make the I2S transmission rate consistent with the UAC transmission rate.

[0071] The present utility model introduces a phase-locked loop clock multiplier PLL, multiplies the BCLK signal of the AIoT device and uses it as the system clock of the sound card chip, realizes the clock synchronization between the AIoT device and the sound card chip, effectively solves problems such as audio data loss and distortion caused by clock asynchronization during the audio data transmission process, and improves the transmission quality and reliability of audio data.

[0072] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above-mentioned exemplary embodiments, and can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be included in the present utility model, and any reference signs in the claims should not be regarded as limiting the claimed rights.

[0073] In addition, it should be understood that although this specification is described in terms of embodiments, not every embodiment contains only an independent technical solution. This narrative manner of the specification is only for clarity. Those skilled in the art should regard the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A clock synchronization device for an I2S recording sound card, characterized in that: It includes an AIOT device, a sound card chip, a phase-locked loop clock multiplier PLL and a computer; the AIOT device is communicatively connected to the input end of the sound card chip, and the output end of the sound card chip is communicatively connected to the computer; the AIOT device is communicatively connected to the phase-locked loop clock multiplier PLL; a system clock is provided in the sound card chip; the phase-locked loop clock multiplier PLL is communicatively connected to the system clock in the sound card chip.

2. A clock synchronization device for an I2S recording sound card according to claim 1, characterized in that, The signals transmitted by the AIOT device and the sound card chip are data signal DATA, frame time signal LRCLK, and bit clock signal BCLK.

3. A clock synchronization device for an I2S recording sound card according to claim 1, characterized in that, The sound card chip includes a main chip U1, a chip U2, a chip U3 and a chip U4. The pin 48 of the main chip U1 is connected to one end of the inductor L1, and the other end of the inductor L1 is connected to the pin 46 of the main chip U1 and one end of the capacitor C19. The other end of the capacitor C19 is connected to the pin 47 of the main chip U1, and the pin 47 of the main chip U1 is grounded; both ends of the capacitor C19 are connected in parallel with the capacitor C20; the pin 24 of the main chip U1 is connected to one end of the capacitor C24, and the other end of the capacitor C24 is grounded; Pin 56 of the main chip U1 is connected to pin 1 of chip U2, pin 55 of the main chip U1 is connected to pin 2 of chip U2, pin 54 of the main chip U1 is connected to pin 3 of chip U2, pin 60 of the main chip U1 is connected to pin 5 of chip U2, pin 59 of the main chip U1 is connected to pin 6 of chip U2, pin 58 of the main chip U1 is connected to pin 7 of chip U2, and pin 4 of chip U2 is grounded; Pin 15 of the main chip U1 is connected to one end of the resistor R15, and the other end of the resistor R15 is connected to pin 2 of the chip U3; pin 1 of the chip U3 is grounded; Pin 30 of the main chip U1 is connected to one end of the capacitor C11, and the other end of the capacitor C11 is connected to the terminal AGND; pins 28 and 29 of the main chip U1 are connected to one end of the capacitor C12, and the other end of the capacitor C12 is also connected to pin 27 of the main chip U1 and the terminal AGND; pin 6 of the chip U4 is connected to the terminal AGND; pin 4 of the chip U4 is connected to one end of the capacitor C42, and the other end of the capacitor C42 is grounded; pin 5 of the chip U4 is simultaneously connected to one end of the capacitor C49 and one end of the resistor R33; the other end of the resistor R33 is simultaneously connected to pin 11 of the chip U4 and one end of the capacitor C50, and the other end of the capacitor C49 and the other end of the capacitor C50 are both grounded; pin 2 and pin 3 of the chip U4 are grounded.

4. A clock synchronization device for an I2S recording sound card according to claim 3, characterized in that, The phase-locked loop clock multiplier PLL includes a power supply circuit, an output clock buffer circuit, a feedback circuit counting frequency division logic circuit, a PLL circuit, a phase-locked loop feedback circuit and an input clock configuration switch circuit; the power supply circuit includes a chip U5, a pin 1 of the chip U5 is grounded, a pin 2 of the chip U5 and a pin 4 of the chip U5 are both connected to a power supply 3V3, a pin 2 of the chip U5 is connected to one end of a capacitor C13, and the other end of the capacitor C13 is grounded; both ends of the capacitor C13 and both ends of the capacitor C58 are connected in parallel; a pin 3 of the chip U5 is connected to a power supply VCC — 5V connection, pin 3 of chip U5 is connected to one end of capacitor C61 and one end of capacitor C62 at the same time, and the other end of capacitor C61 and the other end of capacitor C62 are grounded.

5. A clock synchronization device for an I2S recording sound card according to claim 4, characterized in that, The output clock buffer circuit includes a chip U6, wherein a pin 1 of the chip U6 is connected to a power supply 3V3, a pin 1 of the chip U6 is connected to one end of a capacitor C56, and the other end of the capacitor C56 is grounded; both ends of the capacitor C56 are connected in parallel with both ends of a capacitor C59; a pin 3 of the chip U6 is connected to one end of a resistor R43, and the other end of the resistor R43 is connected to a pin 1 of the chip U6; a pin 4 of the chip U6 is grounded; a pin 5 of the chip U6 is connected to one end of a resistor R44, and the other end of the resistor R44 is connected to a pin 23 of a main chip U1 in the sound card chip; The feedback circuit counting frequency division logic circuit includes a chip U7, a pin 14 of the chip U7 is connected to the power supply 3V3, a pin 14 of the chip U6 is connected to one end of a capacitor C57, and the other end of the capacitor C57 is grounded; both ends of the capacitor C57 and both ends of the capacitor C60 are connected in parallel; The PLL circuit includes a chip U8, wherein the pin 4 of the chip U8 is connected to the pin 2 of the chip U6 in the output clock buffer circuit; the pins 5 and 8 of the chip U8 are both grounded; the pin 6 of the chip U8 is connected to one end of the capacitor C68, and the other end of the capacitor C68 is connected to the pin 7 of the chip U8; the pin 14 of the chip U8 is connected to one end of the resistor R45, and the other end of the resistor R45 is connected to the pin 63 of the main chip U1 in the sound card chip; the pin 13 of the chip U8 is connected to one end of the resistor R46, and the The other end is connected to the pin 9 of the chip U8 and one end of the capacitor C67 at the same time. The other end of the capacitor C67 is connected in series with the resistor R48, the resistor R47, and the pin 11 of the chip U8 in sequence. The capacitor C69 is connected in parallel to both ends of the resistor R48. The connecting line between the resistor R48 and the resistor R47 is connected to the ground line. The pin 16 of the chip U8 is connected to the power supply 3V3. The pin 16 of the chip U8 is connected to one end of the capacitor C64, and the other end of the capacitor C64 is grounded. Both ends of the capacitor C64 are connected in parallel to both ends of the capacitor C66. The phase-locked loop feedback circuit includes chip U9, pin 1 of chip U9 is connected to pin 4 of chip U8 in the PLL circuit; pin 2 and pin 12 of chip U9 are connected to pin 3 of chip U8; pin 4 of chip U9 is connected to pin 1, pin 4 and pin 12 of chip U7 in the feedback circuit counting and frequency division logic circuit; pin 5 of chip U9 is connected to pin 2 and pin 10 of chip U7; pin 6 and pin 13 of chip U9 are connected to pin 5 of chip U7; pin 7 of chip U9 is grounded; pin 10 of chip U9 is connected to pin 13 of chip U7; pin 11 of chip U9 is connected to pin 9 of chip U7; pin 14 of chip U9 is connected to power supply 3V3, pin 14 of chip U9 is connected to one end of capacitor C63, and the other end of capacitor C63 is grounded; both ends of capacitor C63 and both ends of capacitor C65 are connected in parallel.

6. A clock synchronization device for an I2S recording sound card according to claim 5, characterized in that: The input clock configuration switch circuit includes a switch SW2, wherein pin 1 of the switch SW2 is connected to pin 3 of chip U7 in the feedback circuit counting and frequency division logic circuit; pin 2 of the switch SW2 is connected to pin 6 of U7; pin 3 of the switch SW2 is connected to pin 8 of U7; pin 4 of the switch SW2 is connected to pin 11 of U7; pin 5 of the switch SW2, pin 6 of the switch SW2, pin 7 of the switch SW2, and pin 8 of the switch SW2 are all connected to pin 3 of chip U8 in the PLL circuit.

7. A clock synchronization device for an I2S recording sound card according to claim 1, characterized in that: The output end of the sound card chip is connected to the computer through a UAC interface, and the sound card chip is an I2S sound card.

8. A clock synchronization device for an I2S recording sound card according to claim 7, characterized in that: The signal transmitted by the AIOT device and the phase-locked loop clock multiplier PLL is a bit clock signal BCLK.

9. A clock synchronization device for an I2S recording sound card according to claim 8, characterized in that: The clock frequency between the phase-locked loop clock multiplier PLL and the system clock is an integer multiple of the input BCLK signal frequency; the clock signal generated by the phase-locked loop clock multiplier PLL received in the system clock of the sound card chip is synchronized with the clock signal of the AIOT device.

10. A clock synchronization device for an I2S recording sound card according to claim 9, characterized in that: The AIOT device is any one of a smart speaker, a smart home device or an IoT audio device.

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