Device for reducing power

Abstract

The utility model provides a device and a system for reducing power. The apparatus may include a pull-up network and a pull-down network each coupled to an output of the apparatus. The pull-up network includes one or more pull-up branches coupled in parallel, each pull-up branch may have a pull-up capacitor and a pull-up module. The pull-down network may also include one or more pull-down branches coupled in parallel, each pull-down branch may have a pull-down capacitor and a pull-down module. The configuration of capacitors in the device may help improve power efficiency. In addition, the device can be applied to an artificial neural network based on a neuron model.

Description

Technical Field

[0001] The present disclosure relates to devices, systems, and methods for power reduction and their applications, particularly in artificial neural networks. Background Art

[0002] Power consumption in very large scale integration (VLSI) in modern integrated circuits (ICs) is very high, making many of their applications expensive or even infeasible.

[0003] Artificial neural networks are currently used in many artificial intelligence (AI) applications, such as natural language processing, computer vision, robotics, autonomous vehicles, etc. The implementation of many of these AI applications involves circuits such as VLSI ICs. Due to high computational complexity, executing such AI applications also consumes a large amount of power, making the power consumption problem worse.

[0004] Therefore, there is a need to improve the energy efficiency and reduce the power consumption of circuits (such as ICs), devices, and artificial neural network systems, including but not limited to. Summary of the Utility Model

[0005] In one aspect of the present disclosure, a device is provided that helps reduce power consumption and improve power efficiency. The device includes a pull-up network and a pull-down network, both of which are coupled to the output of the device. When the device is in operation, the pull-up network can be coupled between a first voltage and the output of the device, and the pull-down network can be coupled between a second voltage lower than the first voltage and the output of the device. The pull-up network can include one or more pull-up branches coupled in parallel, each pull-up branch having a pull-up capacitor with one end coupled to the output of the device. The pull-down network includes one or more pull-down branches coupled in parallel, each pull-down branch having a pull-down capacitor with one end coupled to the output of the device. Additionally, the pull-up branch can further include a pull-up module coupled in series with the pull-up capacitor in the same pull-up branch. Alternatively or additionally, the pull-down branch can further include a pull-down module coupled in series with the pull-down capacitor in the same pull-down branch.

[0006] The pull-up module can be a P-type module, which can include, for example, one or more P-type metal oxide semiconductor (PMOS) transistors. Meanwhile, the pull-down module can be an N-type module, which can include, for example, one or more N-type metal oxide semiconductor (NMOS) transistors.

[0007] In one aspect of the present disclosure, a device is provided that can be used as an enhanced inverter circuit. In one aspect of the present disclosure, a device is provided that can be used as an enhanced multi-input NAND logic circuit. In one aspect of the present disclosure, a device is provided that can be used as an enhanced multi-input NOR logic circuit.

[0008] In another aspect of the present disclosure, a device is provided that is a combination of a plurality of the above-mentioned devices. The plurality of the above-mentioned devices may be the same or different. In one example, different ones of the above-mentioned devices are connected in parallel with each other to form the combination. In another example, two identical ones of the above-mentioned devices are combined by using the input of one device as the output of the other device and the input of the other device as the output of the one device.

[0009] In yet another aspect of the present disclosure, the device is used in an artificial neural network. The output of the device is a function of the weighted sum of the logical inputs of each of the pull-up branches in the pull-up branch of the device and the weighted sum of the logical inputs of each of the pull-down branches in the pull-down branch of the device, and the output of the device is used as the output of at least one neuron in the artificial neural network. Since the pull-up network or the pull-down network can be replaced by pull-up capacitive elements or pull-down capacitive elements respectively, the output of the device can also be a function of the weighted sum of the logical inputs to each of the pull-up branches in the device, or a function of the weighted sum of the logical inputs to each of the pull-down branches in the device.

[0010] In yet another aspect of the present disclosure, a system is provided that includes the foregoing device and an activation function module. The activation function module receives the output signal of the device as its input and processes the received signal to generate an output that is used as the output of at least one neuron in the artificial neural network. In addition, the system may further include a separate pull-up capacitor coupled between a first voltage and the output of the device. Alternatively or additionally, the system may further include a separate pull-down capacitor coupled between the output of the device and a second voltage; and in yet another aspect of the present disclosure, a method is provided for improving power efficiency by the foregoing device or system.

[0011] In yet another aspect of the present disclosure, a method is provided for applying the foregoing device or system in an artificial neural network. From the following detailed description of the current embodiments in conjunction with the accompanying drawings, these and other features and advantages of the present disclosure will become apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Unless otherwise expressly indicated, the drawings cited herein are only intended to illustrate some embodiments of the present disclosure rather than all embodiments. The word "exemplary" is used herein to mean "serving as an example, instance, or illustration".

[0013] Figure 1 Schematic diagram showing an exemplary device according to various embodiments of the present disclosure.

[0014] Figure 2 Schematic diagram showing an exemplary device having a P-type module and an N-type module according to various embodiments of the present disclosure.

[0015] Figure 3A , Figure 3B , Figure 3C and Figure 3D respectively show exemplary circuit implementations of a device according to embodiments of the present disclosure.

[0016] Figure 4 Schematic diagram showing an exemplary circuit implementation of a device according to an embodiment of the present disclosure, the device being a combination of several devices according to embodiments of the present disclosure.

[0017] Figure 5A and Figure 5B respectively show a block diagram of a configurable capacitor and its corresponding exemplary circuit implementation.

[0018] Figure 6 Schematically shows an exemplary model of an artificial neural network to which exemplary embodiments of the present disclosure can be applied.

[0019] Figure 7 Shows a schematic diagram that illustrates an exemplary system for an artificial neural network according to various embodiments of the present disclosure.

[0020] Figure 8 Shows Figure 7 an exemplary implementation of the system in

[0021] Figure 9 Shows an exemplary flowchart of a method according to various embodiments of the present disclosure.

[0022] In the drawings, unless otherwise noted, the same reference numerals will be used for the same elements. Unless otherwise explicitly stated, the drawings referred to herein are only intended to illustrate some embodiments and not all embodiments. For elements that belong to the same category but may have individually varying attributes, reference numerals in the format "x-n" are used, where x indicates that all elements belong to the same category and are the same for all elements in that category, where n varies with each element, and x-n represents a specific element in that category in order to distinguish the elements from each other. Detailed Description

[0023] It will be readily understood that the components of the embodiments, generally described and illustrated in the accompanying drawings herein, may be arranged and designed in a wide variety of different configurations. Thus, the detailed description of the embodiments of the apparatus, system, and method of the present embodiments, as presented in the accompanying drawings below, is not intended to limit the scope of the embodiments of the present disclosure.

[0024] Throughout the specification, references to "embodiment", "exemplary embodiment", or "selected embodiment" mean that the particular features, structures, or characteristics described in connection with that embodiment are included in at least one embodiment. Thus, the phrases "in an exemplary embodiment", "in one embodiment", "in embodiments", "in exemplary embodiments", or "in an embodiment" appearing throughout this specification are not necessarily referring to the same embodiment. The illustrated embodiments will be better understood by reference to the accompanying drawings, in which like components are always denoted by the same reference numerals. The following description is intended only as an example and shows only certain selected embodiments of the apparatus, circuits, systems, methods, and processes consistent with the embodiments claimed herein.

[0025] The term "coupled" may refer to direct or indirect connection, wireless, wired, and all linkages suitable for the applications of the embodiments. The term "capacitor" may refer to any capacitor or any capacitive element, variations or derivatives thereof that do not depart from the scope of the present disclosure. The term "signal" may refer to a voltage signal, a current signal, an optical signal, a magnetic signal, a data signal, a control signal, a digital signal (interchangeable with a logic signal in this specification), an analog signal, or a radio frequency (RF) signal. The meanings of "a", "an", and "the" may include a single or multiple referents. The meaning of "in" may include "in" and "on". The term "transistor" may refer to any field effect transistor or variations thereof, including but not limited to metal oxide semiconductor (MOS) field effect transistors (FETs), complementary metal oxide semiconductor (CMOS) transistors, BiCMOS transistors, bipolar junction transistors, variations or derivatives thereof that do not depart from the scope of the present disclosure. The term "P-type module" may refer to PMOS transistors, P-type solar cells, P-type semiconductor diodes, P-type thermoelectric modules, P-type thin film transistors (TFTs), P-type light emitting diodes (LEDs), variations or derivatives thereof that do not depart from the scope of the present disclosure. The term "N-type module" may refer to NMOS transistors, N-type solar cells, N-type semiconductor diodes, N-type thermoelectric modules, N-type thin film transistors (TFTs), N-type light emitting diodes (LEDs), variations or derivatives thereof that do not depart from the scope of the present disclosure.

[0026] The term "configured to" can mean that a component, device, apparatus, element, system, module, network, branch, part, or variations thereof are arranged, designed, or adapted to perform a particular function or achieve a particular result. Unless otherwise specified, "first", "second", "third", etc. are not intended to imply that the defined objects should be in a given order in terms of priority, time, space, rank, etc.

[0027] Figure 1 FIG. shows a schematic diagram of an exemplary apparatus 100 in accordance with various embodiments of the present disclosure.

[0028] In Figure 1 FIG., apparatus 100 is shown to include two coupled parts: a pull-up network 110, and a pull-down network 120. For the pull-up network 110, when apparatus 100 is in operation, one end of the pull-up network 110 can be coupled to a high power supply voltage (e.g., VDD) 101, and the other end can be coupled to or serve as an output 107 of apparatus 100. The pull-up network 110 can include one or more pull-up branches (e.g., pull-up branches 1 to i, where i is an integer greater than or equal to 1) coupled in parallel between VDD 101 and output 107. For example, Figure 1 FIG. shows i pull-up branches. Each pull-up branch can have a pull-up capacitor 105 (i.e., capacitors 105-1, 105-2, …, 105-i for pull-up branches 1, 2, …, i, respectively, and having corresponding capacitance values C u1 , C u2 , …, C ui ), and one end of the pull-up capacitor 105 is coupled to the output 107. In addition, each capacitor 105 can be coupled in series with a pull-up module 103 (i.e., 103-1, 103-2, …, 103-i). For example, as Figure 1 FIG. shows, capacitor 105-1 is coupled between VDD and output 107 with pull-up module 103-1; capacitor 105-2 is coupled between VDD and output 107 with pull-up module 103-2; and capacitor 105-i is coupled between VDD and output 107 with pull-up module 103-i. When apparatus 100 is in operation, each pull-up module 103 can be provided with a pull-up input set, and each pull-up input set can include one or more inputs. For example, pull-up module 103-1 is provided with input set 121-1; pull-up module 103-2 is provided with input set 121-2; and pull-up module 103-i is provided with input set 121-i. Input sets 121-1, 121-2, …, 121-i can be coupled to or serve as inputs of apparatus 100, and input sets 121-1, 121-2, …, 121-i can be the same or different. For the latter case, it will be better understood from the example shown in Figure 4 FIG.

[0029] For the pull - down network 120, when the device 100 is in operation, one end of the pull - down network 120 can be coupled to a low power supply voltage (e.g., VSS) 102, and the other end can also be coupled to or serve as an output 107. The pull - down network 120 can include one or more capacitors 106 coupled in parallel between the output 107 and VSS 102. Each capacitor 106 can be coupled in series with a pull - down module 104. The pull - down network 120 can include one or more pull - down branches (e.g., pull - down branches 1 to j, where j is an integer greater than or equal to 1, and j can be the same as or different from i) coupled in parallel between the output 107 and VSS 102. For example, Figure 1 j pull - down branches are shown. Each pull - down branch can have a pull - down capacitor 106 (i.e., capacitors 106 - 1, 106 - 2, …, 106 - j respectively for pull - down branches 1, 2, …, j, and having corresponding capacitance values C d1 , C d2 , …, C dj ). One end of the pull - down capacitor 106 is coupled to the output 107. In addition, each capacitor 106 can be coupled in series with a pull - down module 104 (i.e., 104 - 1, 104 - 2, …, 104 - j). For example, as Figure 1 shown, capacitor 106 - 1 is coupled between the output 107 and VSS 102 with pull - down module 104 - 1; capacitor 106 - 2 is coupled between the output 107 and VSS 102 with pull - down module 104 - 2; and capacitor 106 - j is coupled between the output 107 and VSS 102 with pull - down module 104 - j. When the device 100 is in operation, each pull - down module 104 can be provided with a pull - down input set, and each pull - down input set can include one or more inputs. For example, pull - down module 104 - 1 is provided with input set 122 - 1; pull - down module 104 - 2 is provided with input set 122 - 2; and pull - down module 104 - j is provided with input set 122 - j. The input sets 122 - 1, 122 - 2, …, 122 - j can be coupled to or serve as inputs of the device 100, and can be the same or different. For the latter case, it will be better understood from the example shown in Figure 4 .

[0030] Although the total number of pull - up modules 103 is shown as being the same as the total number of capacitors 105 (i.e., i) in Figure 1 , it should be understood that the total number of pull - up modules 103 can be equal to or less than i. That is, one or more pull - up branches can include only capacitors and no pull - up modules. Similarly, in Figure 1In [the figure], the total number of pull-down modules 104 is shown as being the same as the total number of capacitors 106 (i.e., j), but it should be understood that the total number of pull-down modules 104 can be equal to or less than j. That is, one or more pull-down branches can include only capacitors and not pull-down modules. Moreover, the total number of pull-up modules 103 can be the same as (as Figure 1 shown) or different from (not shown) the total number of pull-down modules 104. In addition, the pull-up input set and the pull-down input set can be the same or different. For example, in a device implemented with CMOS transistors, the pull-up input set and the pull-down input set for the PMOS and NMOS transistor pairs used to construct the CMOS are the same.

[0031] In Figure 1 [the figure], the pull-up modules 103-1, 103-2, …, 103-i and / or the pull-down modules 104-1, 104-2, …, 104-j can be configured to perform the same or different functions. In addition, the device 100 can have both a pull-up module 103 (e.g., modules 103-1 to 103-i) and a pull-down module 104 (e.g., modules 104-1 to 104-j) simultaneously, or can have only a pull-up module 103 or a pull-down module 104. The pull-up network 110 is used to pull up the output 107 to a higher voltage in the direction towards the high power supply voltage VDD 101, while the pull-down network 120 is used to pull down the output 107 to a lower voltage in the direction towards the low power supply voltage VSS 102.

[0032] Here, U x is used to indicate the logical output (not shown) of the pull-up module 103-x, where x is an integer between 1 and i. For example, U1 indicates the logical output of module 103-1, and U i indicates the logical output of module 103-i. C ux is used to indicate the capacitance value of the capacitor 105-x, where x is an integer between 1 and i. For example, C u1 indicates the capacitance value of the capacitor 105-1, and C ui indicates the capacitance value of the capacitor 105-i. When the module 103-x is configured to provide an electrically conductive (ON) path between VDD 101 and the corresponding capacitor 105-x, that is, when the path between VDD 101 and the corresponding capacitor 105-x is electrically enabled by the module 103-x, the pull-up module 103-x can be configured to output a logical 1, i.e., U x = 1. When the pull-up module 103-x is configured to provide an electrically non-conductive (OFF) path between VDD 101 and the corresponding capacitor 105-x, the path between VDD 101 and the corresponding capacitor 105-x is electrically disabled by the module 103-x, i.e., U x = 0.

[0033] Here, D y indicates the logical output (not shown) of the pull-down module 104-y, where y is an integer between 1 and j. For example, D1 indicates the logical output of module 104-1, and D j indicates the logical output of module 104-j. C dy is used to indicate the capacitance value of the capacitor 106-y, where y is an integer between 1 and j. For example, C d1 indicates the capacitance value of the capacitor 106-1, and C dj indicates the capacitance value of the capacitor 106-j. When the module 104-y is configured to provide an electrically conductive path between VSS102 and the corresponding capacitor 106-y, that is, when the path between VSS102 and the corresponding capacitor 106-y is electrically enabled by the module 104-y, the pull-down module 104-y can be configured to output a logical 1, that is, D y = 1. When the pull-down module 104-y is configured to provide an electrically non-conductive path between VSS102 and the corresponding capacitor 106-y, the path between VSS102 and the corresponding capacitor 106-y can be electrically disabled by the module 104-y, that is, D y = 0.

[0034] Therefore, disregarding parasitic parameters, the total equivalent capacitance value C ute of the pull-up network 110 can be calculated according to Equation 1, and the total equivalent capacitance value C dte of the pull-down network 120 can be calculated according to Equation 2:

[0035]

[0036] where: i is the total number of pull-up capacitors used in the pull-up network 110. In this example, the total number of pull-up modules 103 is also equal to i, but the total number of pull-up modules 103 can be less than i. It should be noted that in the case where the pull-up branch only includes pull-up capacitors without pull-up modules, the pull-up branch is default enabled, that is, the U x of this pull-up branch is 1.

[0037]

[0038] where: j is the total number of pull-down capacitors used in the pull-down network 120. In this example, the total number of modules 104 is also equal to j, but the total number of modules 104 can be less than j. It should be noted that in the case where the pull-down branch only includes pull-down capacitors without pull-down modules, the pull-down branch is default enabled, that is, the D y of this pull-down branch is 1.

[0039] The capacitance value C uxWeighting the logical input of the pull-up branch x (where x is an integer and x ∈ [1, i]), when there is a pull-up module in the pull-up branch, the logical input of the pull-up branch is the logical output of the pull-up module 103 - x, and when there is no pull-up module in the pull-up branch, the logical input of the pull-up branch is logical 1. In other words, the capacitance value C of the capacitor 105 - x ux is the weighting of its logical output when the pull-up module 103 - x exists, or the weighting of logical 1 when there is no pull-up module 103 - x. The total equivalent capacitance value C of the pull-up network 110 ute is the weighted sum of the logical inputs to each pull-up branch among the parallel pull-up branches.

[0040] Alternatively or additionally, the capacitance value C of the capacitor 106 - y dy is used as the weighting of the logical input of the pull-down branch y (where y is an integer and y ∈ [1, j]). When there is a pull-down module in the pull-down branch, the logical input of the pull-down branch y is the logical output of the pull-down module 104 - y, and when there is no pull-down module in the pull-down branch, the logical input of the pull-down branch y is logical 1. In other words, the capacitance value C of the capacitor 106 - y dy is the weighting of its logical output when the pull-down module 104 - y exists, or the weighting of logical 1 when there is no pull-down module 104 - y. The total equivalent capacitance value C of the pull-down network 120 dte is the weighted sum of the logical inputs to each pull-down branch among the parallel pull-down branches.

[0041] All the pull-up capacitors in the pull-up network 110 as a whole (total equivalent capacitance value C ute ) can be considered to be electrically in series with all the pull-down capacitors in the pull-down network 120 as a whole (total equivalent capacitance value C dte ).

[0042] Ignoring parasitic parameters, the voltage at the output node 107 can be calculated according to Equation 3:

[0043]

[0044] From Equation 3, Figure 1 the voltage at the output node 107 in ute is determined by the total equivalent capacitance value (C ute ) of all the pull-up capacitors in the pull-up network 110 and the sum of the total equivalent capacitance value of all the pull-up capacitors in the pull-up network 110 and the total equivalent capacitance value of all the pull-down capacitors in the pull-down network 120 (C dteDetermination of the capacitance value ratio of (). It should be noted that controlling the precise capacitance value of a capacitor, especially for an integrated circuit (IC), is challenging, but controlling the capacitance value ratio is relatively easy. The logical output of the device can be derived from the voltage at output 107.

[0045] For a device implemented in a circuit (such as various ICs), after output 107, there may be an output stage ( Figure 1 not shown in), for example, an inverter or buffer used as the output stage. Depending on the application, other output stages can also be added to output 107. The output of the output stage can be configured as logic 1 or 0.

[0046] Figure 2 An exemplary device 200 with a P-type module and an N-type module according to various embodiments of the present disclosure is shown. Figure 2 Similar to Figure 1 , except that Figure 1 the pull-up modules 103-1, 103-2,..., 103-i in are respectively implemented by Figure 2 the P-type modules 203-1, 203-2,..., 203-i in, and Figure 1 the pull-down modules 104-1, 104-2,..., 104-j in are respectively implemented by Figure 2 the N-type modules 204-1, 204-2,..., 204-j in.

[0047] Correspondingly, Figure 1 VDD 101, the pull-up network 110, the pull-up capacitors 105-1, 105-2,..., 105-i, and the pull-up input sets 121-1, 121-2,..., 121-i in can be similarly applied respectively in Figure 2 as Figure 2 VDD 201, the pull-up network 210, the pull-up capacitors 205-1, 205-2,..., 205-i, and the pull-up input sets 221-1, 221-2,..., 221-i in. Alternatively or additionally, Figure 1 VSS102, the pull-down network 120, the pull-down capacitors 106-1, 106-2,..., 106-j, and the pull-down input sets 122-1, 122-2,..., 122-j in can be similarly applied respectively in Figure 2 as Figure 2 VSS202, the pull-down network 220, the pull-down capacitors 206-1, 206-2,..., 206-j, and the pull-down input sets 222-1, 222-2,..., 222-j in.

[0048] Moreover, the output of the pull-up network 210 and the output of the pull-down network 220 can be coupled to or used as the output 207 of device 200. For simplicity, it will not be repeated here. Figure 2and Figure 1 the same or similar parts between, but those skilled in the art will be able to apply the teachings of Figure 1 to the similar content related to Figure 2 in.

[0049] Figure 3A FIG. shows an exemplary device 310 according to an embodiment of the present disclosure. In Figure 3A , the device 310 may include a PMOS transistor 313 and an NMOS transistor 314, and the gates of both the PMOS transistor 313 and the NMOS transistor 314 are commonly connected to a common input 317 of the device 310. When the device 310 is in operation, the source of the PMOS transistor 313 may be coupled to a high power supply voltage (e.g., VDD) 311, and the source of the NMOS transistor 314 may be coupled to a low power supply voltage (e.g., VSS) 312. The drain of the PMOS transistor 313 is coupled to the output 318 of the device 310 via a pull-up capacitor 315, and the drain of the NMOS transistor 314 is coupled to the output 318 via a pull-down capacitor 316. It can be seen that Figure 3A the PMOS transistor 313 and the NMOS transistor 314 in Figure 2 can respectively act as a P-type module in at least one pull-up branch and an N-type module in at least one pull-down branch of the device 200 of

[0050] Generally, the leakage current flowing through the dielectric material of the capacitor is very small. As Figure 3A shown, when the improved CMOS inverter is in a static or stable state with no switching at the gate input 317, the pull-up capacitor 315 can reduce the leakage power from VDD 311 through the PMOS transistor 313 to the output 318; and the pull-down capacitor 316 can reduce the leakage power from the output 318 through the NMOS transistor 314 to VSS 312. When the improved CMOS inverter is in a dynamic state with switching at the gate input 317 (e.g., the gate input 317 switches from logic 1 to logic 0, or from logic 0 to logic 1), the PMOS transistor 313 and the NMOS transistor 314 are simultaneously turned on for a short time, which results in short-circuit power. This short-circuit power can be further reduced by the pull-up capacitor 315 and the pull-down capacitor 316. In this way, the static power of the transistor (pull-up module and / or pull-down module) and the short-circuit power of the branch (corresponding pull-up branch and pull-down branch) including the transistor (pull-up module and / or pull-down module) can be controllably reduced. Thus, the total power of the device 310 is reduced.

[0051] Due toFigure 3A The PMOS transistors 313 and NMOS transistors 314 in Figure 2 can respectively serve as the P-type modules of at least one pull-up branch and the N-type modules of at least one pull-down branch in the device 200 of Figure 1 or can respectively serve as the pull-up modules in at least one pull-up branch and the pull-down modules in at least one pull-down branch in the device 100 of Figure 3A Therefore, the above-described power reduction mechanism explained with reference to

[0052] Figure 3B FIG. shows an exemplary device 330 according to an embodiment of the present disclosure. In Figure 3B the device 330 may include two PMOS transistors 333, 334 and two NMOS transistors 335, 336. One input 339 of the device 330 is coupled to the gates of the PMOS transistor 333 and the NMOS transistor 336, and the other input 340 of the device 330 is coupled to the gates of the PMOS transistor 334 and the NMOS transistor 335. When the device 330 is in operation, the sources of the PMOS transistors 333, 334 may be coupled to a high power supply voltage (e.g., VDD) 331, and the drains of the PMOS transistors 333, 334 are coupled together with one end of the pull-up capacitor 337. The drain of the NMOS transistor 335 is coupled to one end of the pull-down capacitor 338, and the source of the NMOS transistor 335 is coupled to the drain of another NMOS transistor 336. When the device 330 is in operation, the source of the NMOS transistor 336 may be coupled to a low power supply voltage (e.g., VSS) 332. Here, the phrase "the device is in operation" may refer to the state where the device is powered, for example, coupled between a higher voltage and a lower voltage. The other ends of the pull-up capacitor 337 and the pull-down capacitor 338 are commonly coupled to the output 341 of the device 330. It can be seen that the PMOS transistors 333, 334 as a whole can serve as one pull-up module / P-type module in one pull-up branch in the device 100 of Figure 1 or in the device 200 of Figure 2 and the NMOS transistors 335, 336 as a whole can serve as one pull-up module / P-type module in one pull-up branch in the device 100 of Figure 1 or in the device 200 of Figure 2act as a pull-down module / N-type module in a corresponding one of the pull-down branches in the device 200. The pull-up input set for the pull-up module / P-type module and the pull-down input set for the pull-down module / N-type module both include two inputs 339 and 340. In addition, PMOS transistors 333, 334, NMOS transistors 335, 336 together with capacitors 337, 338 can form an improved CMOS structure, and this improved CMOS structure enables the device 330 to be used as an improved two-input NAND gate.

[0053] Figure 3C shows an exemplary device 350 according to an embodiment of the present disclosure. In Figure 3C the device 350 may include two PMOS transistors 353, 354 and two NMOS transistors 355, 356. An input terminal 359 of the device 350 is coupled to the gates of the PMOS transistor 353 and the NMOS transistor 355, and another input terminal 360 of the device 350 is coupled to the gates of the PMOS transistor 354 and the NMOS transistor 356. When the device is in operation, the source of the PMOS transistor 353 can be coupled to a high power supply voltage (e.g., VDD) 351. The drain of the PMOS transistor 353 is coupled to the source of another PMOS transistor 354, and the drain of another PMOS transistor 354 is then coupled to one end of the pull-up capacitor 357. The drains of the two NMOS transistors 355, 356 are both coupled to one end of the pull-down capacitor 358. When the device is in operation, the sources of the NMOS transistors 355, 356 can be coupled to a low power supply voltage (e.g., VSS) 352. The other end of the pull-up capacitor 357 and the other end of the pull-down capacitor 358 are coupled together to the output 361 of the device 350. Similar to Figure 3A , the static power and short-circuit power of the device 350 can be controllably reduced by the pull-up capacitor 357 and the pull-down capacitor 358 as shown in Figure 3C .

[0054] It can be seen that the PMOS transistors 353, 354 as a whole can act as a pull-up module / P-type module in at least one of the pull-up branches of the device 100 in Figure 1 or the device 200 in Figure 2 , and the NMOS transistors 355, 356 as a whole can be in Figure 1 the device 100 or Figure 2act as a pull - down module / N - type module in at least one of the pull - down branches in the device 200. The pull - up input set for the pull - up module / P - type module and the pull - down input set for the pull - down module / N - type module both include two inputs 359 and 360. In addition, PMOS transistors 353, 354, NMOS transistors 355, 356 together with capacitors 357, 358 can form an improved CMOS structure, which enables the device 350 to be used as an improved two - input NOR (NOT - OR) gate.

[0055] Although two inputs are shown in Figure 3B and 3C , those skilled in the art will understand that the number of inputs is not limited to two, but can be any number suitable for a particular application of the device. Similar to the device 310 in Figure 3A , the static power and short - circuit power of the devices 330, 350 can be controllably reduced by the corresponding pull - up capacitors and pull - down capacitors. Therefore, compared with the traditional NAND and NOR gates implemented by MOSFETs, the device 330 (which can be used as an improved two - input NAND gate) and the device 350 (which can be used as an improved two - input NOR gate) can achieve the corresponding logic functions with improved power efficiency.

[0056] Figure 3D FIG. shows an exemplary device 370 according to an embodiment of the present disclosure. In Figure 3D , the device 370 may include two PMOS transistors 373, 374 and two NMOS transistors 375, 376. The gate of PMOS transistor 373 and the gate of NMOS transistor 375 can be coupled to node 382 of the device 370, and the gates of the other PMOS transistor 374 and NMOS transistor 376 can be coupled together to another node 381 of the device 370. When the device 370 is in operation, the sources of PMOS transistors 373, 374 can be coupled to a high supply voltage (e.g., VDD) 371. The drain of PMOS transistor 373 is coupled to one end of the pull - up capacitor 377, and the drain of the other PMOS transistor 374 is coupled to one end of the other pull - up capacitor 378. The other ends of the pull - up capacitor 377 and the pull - up capacitor 378 are respectively connected to nodes 381, 382. The drains of NMOS transistors 375 and 376 are respectively coupled to one end of the pull - down capacitor 379 and one end of the other pull - down capacitor 380, and the other ends of the pull - down capacitor 379 and the other pull - down capacitor 380 are then respectively coupled to node 381 and node 382. When the device 370 is in operation, the sources of NMOS transistors 375 and 376 can be coupled to a low supply voltage (e.g., VSS) 372.

[0057] It can be seen that the PMOS transistor 373, NMOS transistor 375, pull-up capacitor 377, and pull-down capacitor 379 can respectively correspond to the PMOS transistor 313, NMOS transistor 314, pull-up capacitor 315, and pull-down capacitor 316 in a device 310. Similarly, the PMOS transistor 374, NMOS transistor 376, pull-up capacitor 378, and pull-down capacitor 380 can respectively correspond to the PMOS transistor 313, NMOS transistor 314, pull-up capacitor 315, and pull-down capacitor 316 in another device 310. Therefore, the device 370 can be considered as a combination of two devices 310, where the input of one device 310 serves as the output of the other device 310, and vice versa. The device 370 can be used in latches, flip-flops, memories, etc. Similar to Figure 3A , the static power and short-circuit power of the device 370 can be controllably reduced by the pull-up capacitors 377, 378 and pull-down capacitors 379, 380 as shown in Figure 3D . Thereby, the power efficiency of the devices in the present disclosure is improved. It should be noted that the logic functions used in a circuit (such as an IC) can be formed by any one or any combination of the devices in Figures 3A to 3D and their variants that do not depart from the spirit and scope of the present disclosure. Therefore, the devices according to the embodiments of the present disclosure can be applied to various scenarios, including but not limited to circuits, ICs, VLSI ICs, chips, semiconductor devices, etc.

[0058] Figure 4 FIG. 400 shows a device 400 according to an embodiment of the present disclosure. Similar to the devices 100 and 200, the device 400 may include a pull-up network 410 and a pull-down network 420 coupled between a high power supply voltage (such as VDD) 401 and a low power supply voltage (such as VSS) 402. The device 400 may also include one or more branches coupled in parallel between VDD 401 and VSS 402. Each branch may include a pull-up branch and / or a pull-down branch. In addition, each branch can be implemented by any one of the devices 310, 330, 350 and their variants. For example, as shown in Figure 4 , there are multiple branches, where the first branch 430 is implemented in the form of an improved CMOS inverter 310 with a similar input 421 as shown in Figure 3A , the second branch 440 is implemented in the form of an improved dual-input NAND gate 330 with similar inputs 423 and 424 as shown in Figure 3B , and the last branch 490 is in the form of Figure 3CAn implementation in the form of an improved dual-input NOR gate 350 with similar inputs 427, 428 is shown (the branch between 440 and 490 is not shown). All branches may have a common output 407, which is also the output of device 400. When device 400 is in operation, each of the pull-up capacitors 405-1, 405-2, …, 405-i can be used to reduce the leakage power from VDD 401 through the corresponding PMOS transistor coupled thereto to output 407. Alternatively or additionally, each of the pull-down capacitors 406-1, 406-2, …, 406-j can be used to reduce the leakage power from output 407 through the corresponding NMOS transistor coupled thereto to VSS 402. In Figure 4 , i is equal to j. Additionally, similar to Figure 3A , 3B and 3C, the short-circuit power of device 400 is also reduced. Thus, the power of device 400 is controllably reduced.

[0059] It should be noted that Figures 1 to 4 , all the capacitors in 7 and 8 and the capacitors in other devices according to the present disclosure may have constant or variable capacitance values. Figure 5A and 5B respectively show an exemplary configurable capacitor with a variable capacitance value and its exemplary circuit implementation. Other implementations of variable capacitance capacitors are also applicable to any capacitor in the present disclosure.

[0060] It should be understood that although some embodiments of the devices in the present disclosure are implemented with electronic circuits such as Figures 3A - 3D to Figure 4 , this is for illustration only and not for limitation. The devices according to the embodiments of the present disclosure or at least a part thereof can be implemented in other ways without departing from the principles and scope of the present disclosure, including but not limited to acoustic devices, optical devices, magnetic devices, wireless devices, etc.

[0061] Figure 5A Shows an example of a configurable capacitor 511, which can be applied to Figures 1 to 4 , Figure 7 and Figure 8Any pull-up capacitor within the pull-up network in. The capacitor 511 has two ends 531 and 532, and the capacitance value of the capacitor 511 can be configured to change according to requirements. The capacitor 511 can be implemented as shown in the virtual block 510, including one or more branches coupled in parallel between the two ends 531 and 532. For each branch, a PMOS transistor among the PMOS transistors 512-1, 512-2,..., 512-k and a pull-up capacitor among the capacitors 513-1, 513-2,..., 513-g are serially electrically coupled between the ends 531 and 532. Here, the total number g of the capacitors 513 is an integer equal to or greater than 1, and g is not less than the total number k of the PMOS transistors 512. However, in order to make the capacitance value of the capacitor 511 variable, g is preferably greater than 1. When the branch between the ends 531 and 532 only includes a pull-up capacitor, both ends of the capacitor are directly coupled to 531 and 532. Control logic (not shown) can be used to control the on / off of each of the PMOS transistors 512-1 to 512-k. By configuring the on / off (on / off) of each PMOS transistor and thus configuring the branch where the PMOS transistor exists to be turned on / off, the total capacitance value of the block 510 (i.e., the capacitor 511) is variable. Figure 5B is an example showing a configurable capacitor 521, which can be applied to Figures 1 to 4 , Figure 7 and Figure 8 any pull-down capacitor within the pull-down network of. The capacitor 521 has two ends 541 and 542, and the capacitance value of the capacitor 521 can be configured to change according to requirements. The capacitor 521 can be implemented as shown in the virtual block 520, which includes one or more branches coupled in parallel between the two ends 541 and 542. For each branch, a pull-down capacitor among the capacitors 523-1, 523-2,..., 523-h and an NMOS transistor among the NMOS transistors 522-1, 522-2,..., 522-q are serially electrically coupled between the ends 541 and 542. Here, the total number h of the capacitors 523 is an integer equal to or greater than 1, and h is not less than the total number q of the NMOS transistors 522. However, in order to make the capacitance value of the capacitor 521 variable, h is preferably an integer greater than 1. When the branch between the ends 541 and 542 only includes the pull-down capacitor 523, both ends of the capacitor are directly coupled to 541 and 542. Control logic (not shown) can be used to control the on / off of each of the NMOS transistors 522-1 to 522-q. By configuring the on / off (on / off) of each NMOS transistor and thus configuring the branch where the NMOS transistor exists to be turned on / off, the total capacitance value of the block 520 (i.e., the capacitor 521) is variable.

[0062] The pull-up capacitor and / or pull-down capacitor in the device according to the present disclosure can contribute to power reduction of the device. In addition, the capacitance value of the pull-up capacitor or pull-down capacitor can be configured to be greater than the capacitance value of the parasitic capacitor to such an extent that the capacitance value of the parasitic capacitor can be ignored in Equations 1 to 3 and Equations 5 to 8. Therefore, any capacitor in the pull-up network and / or pull-down network of the device can be configured with an appropriate capacitance value as needed, greatly improving the flexibility of the device.

[0063] Figure 6 An exemplary model 600 (e.g., a neuron) used in an artificial neural network is schematically shown. The model 600 determines its output y according to Equation 4,

[0064]

[0065] where: x i is the i-th input of the model, w i is the weight corresponding to x i , b is the bias, f is the function, n indicates the total number of inputs or the total number of weights, and n is an integer greater than 0 and preferably greater than 1.

[0066] Referring to Figure 6 , x1, x2 to x n are the inputs of the model 600, and the weights w1, w2 to w n correspond to x1, x2 to x n respectively. The sum of the bias b and x i *w i is used as the input of the function f to obtain the output y of the model 600. For example, the function can be an S (sigmoid) function, a rectified linear unit (ReLU) function, a logistic function, or other functions suitable for the application of the model.

[0067] An artificial neural network can include multiple neurons as Figure 6 shown, where each neuron can be constructed, for example, with a series of multiply-accumulate (MAC) blocks followed by a non-linear function. The series of MAC blocks and the non-linear function can be implemented in a circuit such as an IC. However, such a circuit will consume a large amount of power and chip area, resulting in high cost or even infeasibility in implementation. By applying the device and / or method according to the present disclosure to such an artificial neural network, this problem can be alleviated or solved.

[0068] It can be seen that the logical output U x of the pull-up module and the capacitance value C ux of the pull-up capacitor in the device according to the present disclosure (e.g., device 100, 200, etc.) can respectively correspond to the input x i and the weight wi 。In some examples, such as Figures 1 to 4 in the device explicitly shown in, the bias b can be considered to be 0. In some examples, the bias b can be provided by other separate elements, including but not limited to a capacitor coupled in parallel with the pull-up network of the device. Additionally, Equation 3 for calculating the voltage at the output of the device according to the present disclosure can correspond to at least a portion of the function f in Equation 4. The logical output y of Equation 4 can be derived from the output voltage of the device in a known manner.

[0069] Alternatively or additionally, the logical output D of the pull-down module in the device according to the present disclosure y and the capacitance value C of the pull-down capacitor dy can respectively correspond to the input x i and the weighting w i in Equation 4. For Figures 1 to 4 the device explicitly shown in, the bias b can be considered to be 0. In some examples, the bias b can be provided by other separate elements, including but not limited to a capacitor coupled in parallel with the pull-down network of the device. And, Equation 3 for calculating the voltage at the output of the device according to the present disclosure can correspond to at least a portion of the function f in Equation 4. Thus, a device according to various embodiments of the present disclosure, e.g., any one or any combination of devices 100, 200, 310, 330, 350, 400 or any variant thereof that does not depart from the principles of the present disclosure, can be used to construct at least a portion of a neuron model 600, up to and including an artificial neural network of multiple such neurons.

[0070] Figure 7 An exemplary system 700 according to various embodiments of the present disclosure is shown.

[0071] A system 700 mainly intended for an artificial neural network can include a device 750 according to an embodiment of the present disclosure and an activation function module 730. The activation function module 730 is configured to receive signals from the output node 709 of the device 750, process the signals, and output the processed signals as the output 731 of the activation function module 730, and the output 731 is also coupled to or used as the output of the system 700.

[0072] In Figure 7 , the pull-up modules 703-1, 703-2, …, 703-i can respectively correspond to Figure 1 the pull-up modules 103-1, 103-2, …, 103-i in; the pull-up capacitors 705-1, 705-2, …, 705-i can respectively correspond to Figure 1 the pull-up capacitors 105-1, 105-2, …, 105-i in. Additionally, the pull-down modules 704-1, 704-2, …, 704-j respectively correspond toFigure 1 the pull-down modules 104-1, 104-2, …, 104-j therein; and the pull-down capacitors 706-1, 706-2, …, 706-j can respectively correspond to Figure 1 the pull-down capacitors 106-1, 106-2, …, 106-j in Figure 1 . For the sake of simplicity, the same or similar content as in Figures 1 to 6 will not be repeated here, but those skilled in the art will be able to understand the details in the device 750 in view of the teachings of

[0073] When the system 700 is in operation, it may further include a separate pull-up capacitor 707 (with a capacitance value of C bu ) and / or a separate pull-down capacitor 708 (with a capacitance value of C bd ), where one end of the separate pull-up capacitor 707 is coupled to the high power supply voltage (e.g., VDD) 701 and the other end is coupled to the output 709 of the device 750, and one end of the separate pull-down capacitor 708 is coupled to the output 709 and the other end is coupled to the low power supply voltage (e.g., VSS) 702. In this case, the separate pull-up capacitor 707, together with the pull-up module 703, the pull-up capacitor 705 in the device 750, and the connections therebetween, form the pull-up network 710 of the system 700. Alternatively or additionally, the separate pull-down capacitor 708, together with the pull-down module 704, the pull-down capacitor 706 in the device 750, and the connections therebetween, form the pull-down network 720 of the system 700.

[0074] Although the device 750 is shown in the form of the device 100 shown in Figure 1 , it should be understood that the device 750 can be in the form of any one or any combination of devices or any variants thereof that do not depart from the principles of the present disclosure. In addition, although in Figure 7 , the separate pull-up capacitor 707 and the separate pull-down capacitor 708 are illustrated as being separated from the device 750, each of them can be a part of the device 750 or integrated into the device 750. For example, the separate pull-up capacitor 707 can be implemented by a pull-up capacitor in a pull-up branch without a pull-up module, and / or the separate pull-down capacitor 708 can be implemented by a pull-down capacitor in a pull-down branch without a pull-down module.

[0075] Similar to Figure 1 , here, C ux indicates the capacitance value of the capacitor 705-x, and U xIndicates the logical output of the pull-up module 703-x connected in series with the capacitor 705-x in the same pull-up branch, where x is an integer between 1 and i. When the module 703-x is configured to provide an electrically conductive path between VDD 701 and the corresponding capacitor 705-x, that is, when the path between VDD 701 and the corresponding capacitor 705-x is electrically enabled by the module 703-x, the pull-up module 703-x can be configured to output a logical 1, i.e., U x = 1. When the pull-up module 703-x is configured to provide an electrically non-conductive path between VDD 701 and the corresponding capacitor 705-x, the path between VDD 701 and the corresponding capacitor 705-x is electrically disabled by the module 703-x, i.e., U x = 0.

[0076] In addition, C dy is used to indicate the capacitance value of the capacitor 706-y, and D y is used to indicate the logical output of the pull-down module 704-y connected in series with the capacitor 706-y in the same pull-down branch, where y is an integer between 1 and j. When the module 704-y is configured to provide an electrically conductive path between VSS 702 and the corresponding capacitor 706-y, that is, when the path between VSS 702 and the corresponding capacitor 706-y is electrically enabled by the module 704-y, the pull-down module 704-y can be configured to output a logical 1, i.e., D y = 1. When the pull-down module 704-y is configured to provide an electrically non-conductive path between VSS 702 and the corresponding capacitor 706-y, the path between VSS 702 and the corresponding capacitor 706-y can be electrically disabled by the module 704-y, i.e., D y = 0.

[0077] Similarly, the pull-up capacitor can be used to reduce the leakage power from VDD 701 through the pull-up module in the same pull-up branch to the output 709 of the device 750; and the pull-down capacitor can be used to reduce the leakage power from the output 709 through the pull-down module in the same pull-down branch to VSS 702. In addition, the short-circuit power of the device 750 is also reduced by the pull-up capacitor and the pull-down capacitor as described above.

[0078] Disregarding parasitic parameters, the total equivalent capacitance value C ut of the pull-up network 710 of the system 700 can be calculated by Equation 5, which differs from Equation 1 by the additional term C bu , and this additional term C bu is the capacitance value of the individual pull-up capacitor 707, i.e., the total equivalent capacitance value C utis equal to the sum of the total equivalent capacitance value of the pull-up network of device 750 and the capacitance value of the individual pull-up capacitor 707.

[0079]

[0080] Similarly, without considering parasitic parameters, the total equivalent capacitance value C of the pull-down network 720 of system 700 dt can be calculated by Equation 6, which differs from Equation 2 in the additional term C bd , and the additional term C bd is the capacitance value of the individual pull-down capacitor 708, that is, the total equivalent capacitance value C of the pull-down network 720 of system 700 dt is equal to the sum of the total equivalent capacitance value of the pull-down network of device 750 and the capacitance value of the individual pull-down capacitor 708.

[0081]

[0082] It should be noted that each pull-up module 703-x can receive a pull-up input set 721-x and generate a logic output U x , for example, 1 or 0, to connect or disconnect the pull-up branch including the corresponding pull-up capacitor 705-x from the pull-up network. And each pull-down module 704-y can receive a pull-down input set 722-y and generate a logic output D y , for example 1 or 0, for connecting or disconnecting the pull-down branch including the corresponding pull-down capacitor 706-y from the pull-down network. It can be seen that the logic output U of the pull-up module 703-x x and the capacitance value C of the pull-up capacitor 705-x ux can respectively correspond to the input x i and the weighting w i in Equation 4. In addition, the capacitance value C of the individual pull-up capacitor 707 bu can correspond to the bias b in Equation 4. Alternatively or additionally, the logic output D of the pull-down module 704-y y , the capacitance value C of the pull-down capacitor 706-y dy and the capacitance value C of the individual pull-down capacitor 708 bd can also respectively correspond to the input x i , the weighting w i and the bias b in Equation 4.

[0083] Figure 7 The voltage at node 709 in ut is determined by the capacitance value ratio of C ut and C dt and C. Similar to Equation 3, without considering parasitic parameters, the output voltage at node 709 can be calculated according to Equation 7:

[0084]

[0085] Among them, C is calculated according to Equation 5 ut , and C is calculated according to Equation 6 dt .

[0086] As can be understood from the above, Equation 7 for calculating the voltage at the output 709 of the computing device 750 can correspond to at least a part of the function f in Equation 4. That is to say, even if the activation function module 730 is not activated, the device 750 can be configured to act as or be applied to the neuron model 600 up to an artificial neural network including multiple such neurons. However, in order to make the device 750 more flexible and applicable to more applications, especially artificial neural networks, the device 750 is followed by an activation function module 730 to form the system 700. The activation function module 730 can be configured to further compose Equation 7 (or Equation 3 when the bias is 0) to form a composition function z to be used as the function f in Equation 4, so as to expand the application of the system 700. That is to say, the function z implemented by the activation function module 730 can take the signal (e.g., voltage signal) at the output 709 of the device 750 as its input, and use z(V 输出 ) as the function f in Equation 4 to generate the output 731 of the system 700. This allows the device 750 or the system 700 to perform complex operations that are difficult to achieve separately by a single function such as Equation 3 or Equation 7, thereby making it applicable to different applications and scenarios. The activation function module 730 can be implemented by hardware, software, firmware, or any combination thereof. Since the activation function module 730 is separated from the device, the area of the device can be reduced, and the flexibility of the device can be increased.

[0087] In addition, each of the capacitors 705-1 to 705-i, 706-1 to 706-j, 707, and 708 can be a configurable capacitor with a variable capacitance value (e.g., a configurable capacitor as shown in Figure 5A or Figure 5B ) or a capacitor with a constant capacitance value. Therefore, in Equation 7, the corresponding weights w i and the bias b can be implemented by configurable capacitors, which enables the weights and / or the bias to be adjusted / updated during the operation of the neural network, further enhancing the flexibility of the device and / or system according to the present disclosure.

[0088] The voltage at the output node 709 can be adjusted by C ut and / or C dt . For example, when C ut increases, the voltage at the output node 709 will rise, while when C dtWhen increasing, the voltage at the output node 709 will decrease. By introducing two sets of weighted sums, namely, C calculated as in Equation 5 ut and C calculated as in Equation 6 dt , the computing throughput can be increased. Equation 5 or 6 augments Equation 1 or 2 with a bias respectively, which enhances the flexibility of the device and the system. Therefore, the neural network system 700 can increase the throughput of the computation for processing the input data and the weighted data, which further reduces the power consumption and the hardware complexity, thus allowing the feasibility of the hardware implementation for some applications.

[0089] Figure 8 shows Figure 7 an exemplary system 800 of the system in Figure 8 . In Figure 7 , the pull-up network 810 of the system 800 only includes one pull-up branch with one pull-up capacitor 805 (the number of pull-up capacitors in the pull-up network of the device 850 is equal to 1, i.e., i = 1). That is, there is neither a separate pull-up capacitor as indicated by 707 in Figure 7 , nor a pull-up module connected to the pull-up capacitor 805 in the same pull-up branch (the number of pull-up modules in the pull-up network of the device 850 is equal to 0). For the pull-down network 820, it is similar to the pull-down network 720 in Figure 7 . For example, the pull-down capacitors 806-1 to 806-j, the pull-down modules 804-1 to 804-j, the inputs 822-1 to 822-j, and the separate pull-down capacitor 808 can respectively correspond to the pull-down capacitors 706-1 to 706-j, the pull-down modules 704-1 to 704-j, the inputs 722-1 to 722-j, and the separate pull-down capacitor 708 in Figure 8 . Therefore, for simplicity, the details related to the same or similar content in Figure 7 are not repeated here.

[0090] Referring back to Equations 5, 6, and 7, the output voltage at the node 809 of the device 850 can be calculated according to Equation 8:

[0091]

[0092] where C u is the capacitance value of the pull-up capacitor 805 of the device 850, and C dt is the total equivalent capacitance value of all the pull-down capacitors in the pull-down network 820 of the system 800, which can be calculated similarly by Equation 6.

[0093] As can be understood from the above, equation 8 for calculating the voltage at the output 809 of the device 850 may correspond to at least a portion of the function f in equation 4. Thus, the device 850 may be configured to act as or be applied to a neuron model 600, up to an artificial neural network involving a plurality of such neurons. However, in order to make the device 850 more flexible and applicable to more applications, especially in artificial neural networks, the device 850 may be followed by an activation function module 830. The activation function module 830 may be configured to further compound equation 8 to form a composite function z, which is used as the function f in equation 4, thereby expanding the application of the system 800.

[0094] Compared to the general system 700, the system 800 is simplified by introducing only one set of weighted sums, which helps to reduce the complexity and area of ​​the device, and further reduces the power consumption for some applications. The system 800 can be used for applications that only require one set of weighted sums (with or without bias). Although Figure 8 The system 800 in FIG. 1 is shown as having one pull-up branch in the pull-up network of the system, but it should be understood that the system 800 can be replaced by a system having Figure 7 The pull-up network shown, however, only includes a pull-down network of one pull-down branch without a pull-down module, and / or a separate pull-down capacitor connected in parallel.

[0095] Figure 9 An exemplary flow chart of method 900 according to various embodiments of the present disclosure is shown.

[0096] In step 910, the device receives one or more inputs. The device may be any one or any combination of devices 100, 200, 310, 330, 350, 400, 750, 850, or any variations thereof without departing from the principles of the present disclosure.

[0097] In step 920, a pull-up capacitor is used to reduce the power of a pull-up branch in the device where the pull-up capacitor is located; and / or a pull-down capacitor is used to reduce the power of a pull-down branch in the device where the pull-down capacitor is located. Figures 1 to 8 For the reasons explained, the power efficiency of the device can be improved.

[0098] Optionally, in step 930, the capacitance value of each pull-up capacitor is used as a weight of the logic output generated by the corresponding pull-up module connected in series with the pull-up capacitor, or as a weight of logic 1 when there is no pull-up module; and / or the capacitance value of each pull-down capacitor is used as a weight of the logic output generated by the corresponding pull-down module connected in series with the pull-down capacitor, or as a weight of logic 1 when there is no pull-down module.

[0099] Optionally, in step 940, the device is applied to a neural network system, and the logical output of the device is used as the output of the neural network system. The logical output of the device is derived from the output voltage of the device. Optionally, in step 950, the device is applied to a neural network system, and an activation function implemented by an activation function module is further applied to the output voltage of the device to generate an output as the neural network system. The neural network system may include a device and an activation function module according to the present disclosure, and the activation function module may further implement a synthesis function on the voltage output of the device. For example, the neural network system may be implemented by system 700, 800, or any variant thereof that does not depart from the spirit and scope of the present disclosure.

[0100] According to the present disclosure, the following examples are provided.

[0101] Example 1. A device includes: a pull-up network and a pull-down network, both the pull-up network and the pull-down network are coupled to the output of the device. When the device is in operation, the pull-up network is coupled between a first voltage and the output. The pull-up network includes one or more pull-up branches coupled in parallel, and each pull-up branch has a pull-up capacitor with one end coupled to the output. The pull-down network is coupled between a second voltage lower than the first voltage and the output. The pull-down network includes one or more pull-down branches coupled in parallel, and each pull-down branch has a pull-down capacitor with one end coupled to the output. Wherein each pull-up branch and / or each pull-down branch is configured to receive one or more inputs to the device when the device is in operation.

[0102] Example 2. The device according to Example 1, wherein at least one pull-up branch further includes a pull-up module coupled in series with the other end of the pull-up capacitor in the corresponding pull-up branch, and / or at least one pull-down branch further includes a pull-down module coupled in series with the other end of the pull-down capacitor in the corresponding pull-down branch.

[0103] Example 3. The device according to Example 2, wherein the pull-up module is configured to receive a set of pull-up inputs from the one or more inputs, and generate a logical value to enable / disable the pull-up branch in which the pull-up module is located; and / or the pull-down module is configured to receive a set of pull-down inputs from the one or more inputs, and generate a logical value to enable / disable the pull-down branch in which the pull-down module is located.

[0104] Example 4. The device according to Example 3, wherein when the logical value generated by the pull-up module is logic 1 or when the pull-up branch does not include a pull-up module, the pull-up branch is enabled, and / or when the logical value generated by the pull-down module is logic 1 or when the pull-down branch does not include a pull-down module, the pull-down branch is enabled.

[0105] Example 5. The apparatus according to any one of Examples 1 to 4, wherein the one or more pull-up branches are coupled to the one or more pull-down branches one by one and correspondingly.

[0106] Example 6. The apparatus according to any one of Examples 1 to 5, wherein each pull-up branch of the one or more pull-up branches includes a pull-up module and a pull-up capacitor coupled in series between a first voltage and the output of the apparatus, and / or each pull-down branch of the one or more pull-down branches includes a pull-down module and a pull-down capacitor coupled in series between a second voltage and the output of the apparatus.

[0107] Example 7. The apparatus according to any one of Examples 2 to 6, wherein the pull-up module is a P-type module and the pull-down module is an N-type module.

[0108] Example 8. The apparatus according to Example 7, wherein the P-type module includes one or more P-type metal oxide semiconductor (PMOS) transistors and the N-type module includes one or more N-type metal oxide semiconductor (NMOS) transistors.

[0109] Example 9. The apparatus according to any one of Examples 5 to 8, wherein the pull-up module in a pull-up branch is a PMOS transistor, the source of the PMOS transistor is coupled to the first voltage and the drain is coupled to the other end of the pull-up capacitor, and the pull-down module in the corresponding pull-down branch is an NMOS transistor, the source of the NMOS transistor is coupled to the second voltage and the drain is coupled to the other end of the pull-down capacitor, wherein the common gate of the PMOS transistor and the NMOS transistor receives an input to the apparatus.

[0110] Example 10. The apparatus according to any one of Examples 5 to 8, wherein the pull-up module in a pull-up branch includes n PMOS transistors coupled in parallel, the sources of the n PMOS transistors coupled in parallel are all coupled to the first voltage and the drain is coupled to the other end of the pull-up capacitor, and the pull-down module in the corresponding pull-down branch includes n NMOS transistors coupled in series between the other end of the pull-down capacitor and the second voltage, wherein n is an integer greater than 1, and each of the n PMOS transistors and each of the n NMOS transistors form a pair to receive one of the n inputs to the apparatus from the common gate of the pair.

[0111] Example 11. The device according to any one of Examples 5 to 8, wherein the pull-up module in one pull-up branch includes n PMOS transistors connected in series between a first voltage and a pull-up capacitor, and the pull-down module in a corresponding pull-down branch includes n NMOS transistors connected in parallel between a pull-down capacitor and a second voltage, where n is an integer greater than 1, and each of the n PMOS transistors and each of the n NMOS transistors form a pair to receive one of the n inputs to the device from a common gate of the pair.

[0112] Example 12. The device according to any one of Examples 5 to 8, wherein the device includes a plurality of pull-up branches and the same number of pull-down branches, where at least one pull-up branch and its corresponding pull-down branch are configured as the device shown in Example 9, at least one pull-up branch and its corresponding pull-down branch are configured as the device shown in Example 10, and / or

[0113] at least one pull-up branch and its corresponding pull-down branch are configured as the device shown in Example 11.

[0114] Example 13. The device according to any one of Examples 5 to 8, wherein the device includes two connected parts, each part being configured as the device shown in Example 9, where an input of one part is coupled to an output of the other part, and an input of the other part is coupled to an output of the one part.

[0115] Example 14. The device according to any one of Examples 1 to 12, wherein the capacitance value of each pull-up capacitor is used as a weight for the logical input of the pull-up branch in which each pull-up capacitor is located, the logical input of the pull-up branch being the logical value generated by the pull-up module in the same pull-up branch or being logical 1 when there is no pull-up module, the total equivalent capacitance value of all pull-up branches is the weighted sum of the logical inputs of each pull-up branch of the device, and / or the capacitance value of each pull-down capacitor is used as a weight for the logical input of the pull-down branch in which each pull-down capacitor is located, the logical input of the pull-down branch being the logical value generated by the pull-down module in the same pull-down branch or being logical 1 when there is no pull-down module, the total equivalent capacitance value of all pull-down branches is the weighted sum of the logical inputs of each pull-down branch of the device.

[0116] Example 15. Application of the device according to Example 14 in an artificial neural network, wherein the output voltage of the device is used as the output of at least one neuron in the artificial neural network, the output voltage being a function of the total equivalent capacitance value of all pull-up branches of the device and / or a function of the total equivalent capacitance value of all pull-down branches of the device. Example 16. An artificial neural network system, comprising: the device shown in Example 14; and

[0117] Activation function module, which in operation is configured to: receive a signal from the output of the device as an input to the activation function module, and process the received signal to generate an output of the artificial neural network system, such that the output of the artificial neural network system is a function of the weighted sum of the logical inputs of each pull-up branch in the device, and / or a function of the weighted sum of the logical inputs of each pull-down branch in the device. Example 17. An artificial neural network system, comprising: a device as shown in Example 14; a separate pull-up capacitor coupled between a first voltage and the output of the device, and / or a separate pull-down capacitor coupled between the output of the device and a second voltage; and an activation function module, which in operation is configured to: receive a signal from the output of the device as an input to the activation function module, process the received signal to generate an output of the artificial neural network system, such that the output of the artificial neural network system is a function of the sum of the weighted sum of the logical inputs of each pull-up branch in the device and the capacitance value of the separate pull-up capacitor, and / or a function of the sum of the weighted sum of the logical inputs of each pull-down branch in the device and the capacitance value of the separate pull-down capacitor.

[0118] Example 18. The system according to Example 16 or 17, wherein at least one to all of the capacitors used in the system are configurable capacitors having variable capacitance values.

[0119] Example 19. A method, comprising: a device as shown in Example 14, which receives one or more inputs; using each pull-up capacitor to reduce the power of each pull-up branch in which the pull-up capacitor is located; and / or using each pull-down capacitor to reduce the power of each pull-down branch in which the pull-down capacitor is located.

[0120] Example 20. A method, comprising: a device as shown in Example 14, which receives one or more inputs;

[0121] using the capacitance value of each pull-up capacitor as a weight for the logical output generated by a pull-up module coupled in series with the pull-up capacitor, or using the capacitance value of each pull-up capacitor as a weight for logic 1 when there is no pull-up module, and / or using the capacitance value of each pull-down capacitor as a weight for the logical output generated by a pull-down module coupled in series with the pull-down capacitor, or using the capacitance value of each pull-down capacitor as a weight for logic 1 when there is no pull-down module; applying the device to a neural network system; and applying an activation function to the output voltage of the device to generate an output as the neural network system.

[0122] It should be noted that all capacitors in the device, system or method as illustrated in the above examples may have fixed capacitance values or variable capacitance values.

[0123] Although specific embodiments of the present disclosure have been shown and described, those skilled in the art will understand that changes, variations, and modifications can be made based on the teachings herein without departing from the spirit and scope of the present disclosure. Accordingly, the present disclosure is intended to embrace all such alternatives, modifications, and variations that fall within the spirit and broad scope of the appended claims.

Claims

1. A device comprising: A pull-up network and a pull-down network, both coupled to the output of the device, When the device is in operation, the pull-up network is coupled between a first voltage and the output, the pull-up network includes one or more pull-up branches coupled in parallel, each pull-up branch has a pull-up capacitor with one end coupled to the output, and the pull-down network is coupled between a second voltage lower than the first voltage and the output, the pull-down network includes one or more pull-down branches coupled in parallel, each pull-down branch has a pull-down capacitor with one end coupled to the output, wherein, when the device is in operation, each pull-up branch and / or each pull-down branch is configured to receive one or more inputs to the device.

2. The device according to claim 1, wherein: At least one of the pull-up branches further comprises a pull-up module coupled in series with the other end of the pull-up capacitor in the corresponding pull-up branch, and / or At least one of the pull-down branches further includes a pull-down module coupled in series with the other end of the pull-down capacitor in the corresponding pull-down branch.

3. The device according to claim 2, wherein: The pull-up module is configured to receive a pull-up input set from the one or more inputs, and generate a logic value to enable / disable the pull-up branch where the pull-up module is located, and / or The pull-down module is configured to receive a pull-down input set from the one or more inputs, and to generate a logic value to enable / disable a pull-down branch where the pull-down module is located.

4. The device according to claim 3, wherein: When the logic value generated by the pull-up module is logic 1 or when the pull-up branch does not include the pull-up module, enabling the pull-up branch, and / or When the logic value generated by the pull-down module is logic 1 or when the pull-down branch does not include the pull-down module, the pull-down branch is enabled. 5 . The apparatus according to claim 1 , wherein the one or more pull-up branches are individually and correspondingly coupled to the one or more pull-down branches.

6. The device according to any one of claims 1 to 4, wherein Each of the one or more pull-up branches comprises a pull-up module and a pull-up capacitor coupled in series between the first voltage and an output of the device, and / or Each of the one or more pull-down branches includes a pull-down module and a pull-down capacitor coupled in series between the second voltage and an output of the device.

7. The device according to claim 5, wherein Each of the one or more pull-up branches comprises a pull-up module and a pull-up capacitor coupled in series between the first voltage and an output of the device, and / or Each of the one or more pull-down branches includes a pull-down module and a pull-down capacitor coupled in series between the second voltage and an output of the device. 8 . The device according to claim 2 , wherein the pull-up module is a P-type module, and the pull-down module is an N-type module.

9. The apparatus of claim 8, wherein the one or more pull-up branches are individually and correspondingly coupled to the one or more pull-down branches.

10. The apparatus of claim 6, wherein the pull-up module is a P-type module, and the pull-down module is an N-type module.

11. The apparatus of claim 7, wherein the pull-up module is a P-type module, and the pull-down module is an N-type module. 12 . The apparatus of claim 7 , wherein the pull-up module comprises one or more PMOS transistors, and the pull-down module comprises one or more NMOS transistors.

13. The device according to claim 7, wherein the pull-up module in one pull-up branch is a PMOS transistor, a source of the PMOS transistor is coupled to the first voltage, and a drain is coupled to the other end of the pull-up capacitor, and the pull-down module in a corresponding one pull-down branch is an NMOS transistor, a source of the NMOS transistor is coupled to the second voltage, and a drain is coupled to the other end of the pull-down capacitor, wherein a common gate of the PMOS transistor and the NMOS transistor receives an input to the device.

14. The device according to claim 7, wherein the pull-up module in one pull-up branch comprises n PMOS transistors coupled in parallel, sources of the n PMOS transistors coupled in parallel are all coupled to the first voltage and drains are coupled to the other end of the pull-up capacitor, and the pull-down module in a corresponding one pull-down branch comprises n NMOS transistors coupled in series between the other end of the pull-down capacitor and the second voltage, wherein n is an integer greater than 1, and each of the n PMOS transistors coupled in parallel and each of the n NMOS transistors form a pair to receive one of the n inputs to the device from a common gate of the pair.

15. The device according to claim 7, wherein the pull-up module in one pull-up branch includes n PMOS transistors connected in series between the first voltage and the pull-up capacitor, and the pull-down module in the corresponding one pull-down branch includes n NMOS transistors connected in parallel between the pull-down capacitor and the second voltage, wherein n is an integer greater than 1, and each of the n PMOS transistors and each of the n NMOS transistors form a pair to receive one of the n inputs to the device from a common gate of the pair.

16. The device of claim 7, wherein the device comprises a plurality of pull-up branches and the same number of pull-down branches, wherein at least one pull-up branch and its corresponding pull-down branch are configured as in the device of claim 13, at least one pull-up branch and its corresponding pull-down branch are configured as in the device of claim 14, and / or at least one pull-up branch and its corresponding pull-down branch are configured as in the device of claim 15.

17. The apparatus of claim 7, wherein the apparatus comprises two connected parts, each of the two connected parts being configured as the apparatus of claim 13, wherein an input of one part is coupled to an output of the other part, and an input of the other part is coupled to an output of the one part.

18. The device according to any one of claims 1 to 4, wherein: The capacitance value of each pull-up capacitor is used as a weight for the logic input of the pull-up branch where each pull-up capacitor is located, the logic input of the pull-up branch is a logic value generated by a pull-up module in the same pull-up branch or is a logic 1 when there is no pull-up module, and the total equivalent capacitance value of all pull-up branches is a weighted sum of the logic inputs of each pull-up branch of the device, and / or The capacitance value of each pull-down capacitor is used as the weight of the logic input of the pull-down branch where each pull-down capacitor is located. The logic input of the pull-down branch is the logic value generated by the pull-down module in the same pull-down branch or is logic 1 when there is no pull-down module. The total equivalent capacitance value of all pull-down branches is the weighted sum of the logic inputs of each pull-down branch of the device.

19. The device according to claim 5, wherein: The capacitance value of each pull-up capacitor is used as a weight for the logic input of the pull-up branch where each pull-up capacitor is located, the logic input of the pull-up branch is a logic value generated by a pull-up module in the same pull-up branch or is a logic 1 when there is no pull-up module, and the total equivalent capacitance value of all pull-up branches is a weighted sum of the logic inputs of each pull-up branch of the device, and / or The capacitance value of each pull-down capacitor is used as the weight of the logic input of the pull-down branch where each pull-down capacitor is located. The logic input of the pull-down branch is the logic value generated by the pull-down module in the same pull-down branch or is logic 1 when there is no pull-down module. The total equivalent capacitance value of all pull-down branches is the weighted sum of the logic inputs of each pull-down branch of the device.

20. The device according to claim 6, wherein: The capacitance value of each pull-up capacitor is used as a weight for the logic input of the pull-up branch where each pull-up capacitor is located, the logic input of the pull-up branch is a logic value generated by a pull-up module in the same pull-up branch or is a logic 1 when there is no pull-up module, and the total equivalent capacitance value of all pull-up branches is a weighted sum of the logic inputs of each pull-up branch of the device, and / or The capacitance value of each pull-down capacitor is used as the weight of the logic input of the pull-down branch where each pull-down capacitor is located. The logic input of the pull-down branch is the logic value generated by the pull-down module in the same pull-down branch or is logic 1 when there is no pull-down module. The total equivalent capacitance value of all pull-down branches is the weighted sum of the logic inputs of each pull-down branch of the device.

21. The device according to claim 7, wherein: The capacitance value of each pull-up capacitor is used as a weight for the logic input of the pull-up branch where each pull-up capacitor is located, the logic input of the pull-up branch is a logic value generated by a pull-up module in the same pull-up branch or is a logic 1 when there is no pull-up module, and the total equivalent capacitance value of all pull-up branches is a weighted sum of the logic inputs of each pull-up branch of the device, and / or The capacitance value of each pull-down capacitor is used as the weight of the logic input of the pull-down branch where each pull-down capacitor is located. The logic input of the pull-down branch is the logic value generated by the pull-down module in the same pull-down branch or is logic 1 when there is no pull-down module. The total equivalent capacitance value of all pull-down branches is the weighted sum of the logic inputs of each pull-down branch of the device.

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