Structure for preparing wafer-level system-in-package by using hybrid bonding technology

Abstract

A structure for preparing a wafer-level system-in-package by using a hybrid bonding technology comprises a wafer-level CIS chip and a second type of wafer-level chip, and the wafer-level CIS chip and the second type of wafer-level chip are integrated together by using a Hybrid Bonding technology. According to the invention, (1) a Hybrid Bonding bonding technology is used for bonding, and the technology can realize higher-density contact connection (more than one million of contacts can be manufactured in a 1 * 1cm chip) and smaller-contact spacing connection (the spacing can be reduced to below 1 micron); and (2) the CIS chip is integrated with other types of chips, and the preparation of a system integrated electronic product with high performance, low power consumption, miniaturization, heterogeneous process integration and low cost is realized. And (3) the whole packaging process is wafer-level packaging, the packaging efficiency is high, the cost is low, and the productivity is high.

Description

Technical Field

[0001] The present invention relates to a semiconductor chip packaging structure, and particularly to a structure for fabricating a wafer-level system-level package using hybrid bonding technology. Background Art

[0002] Hybrid Bonding technology means that in addition to the copper bumps that are recessed at room temperature on the two wafers (or chips) to be bonded, other non-conductive parts of the two wafers (or chips) facing each other also need to be adhered. After the hybrid bonding process is completed, there is no gap between the wafers (or chips), and no epoxy resin is required for filling. The hybrid bonding process flow chart is as Figure 1 shown. Figure 1 Hybrid bonding flow chart: (a) Appearance of the test piece before bonding, (b) Dielectric material bonding step, (c) Copper contact bonding process at elevated temperature, (d) Internal stress distribution state of the contacts at high temperature.

[0003] An image sensor chip (CMOS Inage Sensor, CIS) is an image sensor based on semiconductor CMOS technology and has been widely commercialized since the mid-1990s. Currently, CIS chips have been widely used in multiple fields such as mobile phones, cameras, automotive electronics, and security. With the increasing requirements for the packaging of high-performance, low-power, miniaturized, heterogeneous process integrated, and low-cost system-integrated electronic products in mobile consumer electronic products such as mobile phones, computers, and digital cameras, high-density, multi-type chip system-level packaging products have gradually become the mainstream in the new generation of electronic products. Therefore, how to integrate CIS chips with other types of chips to form system-integrated electronic products has always been a hot technology in the field of chip packaging. Summary of the Invention

[0004] To solve the above technical problems, the purpose of the present invention is to provide a structure for fabricating a wafer-level system-level package using hybrid bonding technology.

[0005] A structure for fabricating a wafer-level system-level package using hybrid bonding technology includes a wafer-level CIS chip and a second type of wafer-level chip; the wafer-level CIS chip includes an upper surface and a lower surface of the CIS chip, and a photosensitive area and a conductive structure are provided on the upper surface of the CIS chip;

[0006] A paste film layer with high light-transmitting characteristics and a glass layer are sequentially provided on the upper surface of the CIS chip;

[0007] The back surface of the wafer-level CIS chip is thinned, and a non-conductive layer is formed;

[0008] A conductive via structure is provided at a position corresponding to the conductive structure of the wafer-level CIS chip on the non-conductive layer;

[0009] A conductive structure is provided at the conductive via structure;

[0010] The second type of wafer-level chip includes a chip upper surface and a chip lower surface, and a chip conductive structure is provided on the chip upper surface;

[0011] A protective film layer is pasted on the upper surface of the second type of wafer-level chip;

[0012] The back surface of the second type of wafer-level chip is thinned to form a non-conductive layer;

[0013] A conductive via structure is formed at a position corresponding to the conductive structure of the second type of wafer-level chip. The conductive via structure penetrates the non-conductive layer and the second type of wafer-level chip; the position where the conductive via structure is formed on the wafer-level chip is offset from the position where the chip conductive structure is located;

[0014] A conductive structure is formed at the structure conductive via structure.

[0015] Furthermore, a wafer-level CIS chip with a conductive structure and a second type of wafer-level chip with a conductive structure are bonded by a hybrid bonding technique to form a bonding structure. The bonding structure includes a non-conductive layer formed after bonding two wafers and a conductive structure formed after bonding two wafers;

[0016] Remove the film layer on the upper surface of the wafer obtained after bonding two wafers of the bonding structure, and form a first insulating layer and a conductive via structure;

[0017] A first metal redistribution layer is provided on the wafer-level structure;

[0018] A second insulating layer and a conductive via structure are provided on the first metal redistribution layer;

[0019] A second metal redistribution layer is provided on the second insulating layer and the conductive via structure;

[0020] Ball mounting is completed on the second metal redistribution layer. The ball mounting is a solder ball structure.

[0021] Furthermore, the wafer chip on which ball mounting is completed is diced to obtain a structure in which a single CIS chip is integrated with other types of chips.

[0022] Furthermore, the material of the insulating layer is an epoxy resin or a silicon oxide insulating material.

[0023] The beneficial effects of the present invention mainly include the following three points: (1) Using the hybrid bonding technology for bonding, which can achieve higher-density contact connections (more than one million contacts can be fabricated within a 1×1 cm chip) and smaller pitch connections (the pitch can be reduced to less than 1 micron). (2) Integrating the CIS chip with other types of chips to realize the preparation of system-integrated electronic products with high performance, low power consumption, miniaturization, heterogeneous process integration, and low cost. (3) The entire packaging process is wafer-level packaging, with high packaging efficiency, low cost, and large production capacity. Description of the Drawings

[0024] Figure 1 Hybrid bonding flowchart: (a) Appearance of the test piece before bonding, (b) Dielectric material bonding step, (c) Copper contact bonding process at elevated temperature, (d) Internal stress distribution state of the contacts at high temperature.

[0025] Figure 2 It is a structural diagram of a wafer-level image sensor (CIS) chip.

[0026] Figure 3 It is for Figure 2 A structural diagram showing a paste film layer and a glass layer with high light-transmitting characteristics are sequentially formed on the upper surface of the structure shown.

[0027] Figure 4 It is for Figure 3 A structural diagram showing the back surface of the structure shown is thinned and a non-conductive layer in the hybrid bonding technology is formed.

[0028] Figure 5 It is for Figure 4 A structural diagram showing a conductive via structure is formed at a position corresponding to the conductive structure of the wafer-level CIS chip on the structure shown.

[0029] Figure 6 It is for Figure 5 A conductive structure is formed at the conductive via structure of the structure shown.

[0030] Figure 7 It is a second type of wafer-level chip structure.

[0031] Figure 8 It is for Figure 7 A structural diagram showing a protective film layer is pasted on the upper surface of the second type of wafer-level chip shown.

[0032] Figure 9 It is for Figure 8 A structural diagram showing the back surface of the second type of wafer-level chip shown is thinned and a non-conductive layer in the hybrid bonding technology is formed.

[0033] Figure 10 It is for Figure 9Structural diagram of forming a conductive via structure at a position corresponding to the second type of wafer-level chip conductive structure on the shown structure.

[0034] Figure 11 To form a conductive structure at the conductive via structure of the Figure 10 shown structure.

[0035] Figure 12 Structural diagram of bonding the wafer-level CIS chip obtained in step (5) and the second type of wafer-level chip obtained in step (10) through hybrid bonding technology.

[0036] Figure 13 To remove Figure 12 the film layer on the upper surface of the wafer obtained by bonding two wafers as shown and form the first insulating layer and the conductive via structure.

[0037] Figure 14 To form Figure 13 a structural diagram of the first metal redistribution layer on the shown wafer-level structure.

[0038] Figure 15 To form Figure 14 a structural diagram of the second insulating layer and the conductive via structure on the shown wafer-level structure.

[0039] Figure 16 To form Figure 15 a structural diagram of the second metal redistribution layer (i.e., the pad) on the shown wafer-level structure.

[0040] Figure 17 To form Figure 16 a structural diagram of completing the ball mounting process on the shown wafer-level structure.

[0041] Figure 18 To integrate Figure 17 a single CIS chip obtained by cutting the shown wafer with other types of chips together. Detailed implementation manners

[0042] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0043] (1) Clean the surface of the wafer-level image sensor (CIS) chip as shown. Among them, 10 is the chip, 11 is the photosensitive area of the CIS chip, and 12 is the conductive structure (i.e., Al Pad) of the CIS chip. 201 is the upper surface of the CIS chip, and 202 is the lower surface of the CIS chip. Figure 2

[0044] Figure 2 (2) Sequentially form a paste film layer and a glass layer with high light transmittance characteristics on the upper surface of the wafer-level CIS chip shown to obtain Figure 3 ​​The structure shown in FIG. 13 is an adhesive film layer with high light transmittance, 14 is a glass layer with high light transmittance, and 203 is the surface of the glass layer.

[0045] (3) Yes Figure 3 The back side of the wafer-level CIS chip is thinned and a non-conductive layer in the hybrid bonding technology is formed to obtain the following Figure 4 The structure shown in FIG. 15 is a non-conductive layer, and the material of the layer in this embodiment is SiO2. 204 is the upper surface of the non-conductive layer 15.

[0046] (4) Figure 4 A conductive through-hole structure is formed at a position corresponding to the conductive structure of the wafer-level CIS chip on the structure shown in FIG. Figure 5 As shown in the structure, the conductive via structure penetrates the non-conductive layer 15 and the CIS chip 10. 205 is a conductive via structure.

[0047] (5) Figure 5 A conductive structure is formed at the conductive through-hole structure shown in the structure, and a conductive structure is obtained as shown in the figure. Figure 6 The structure shown in FIG. 16 is a conductive structure.

[0048] (6) For Figure 7 The surface of the second type of wafer-level chip shown is cleaned. 101 is the chip, 102 is the chip conductive structure (ie, AlPad), 301 is the upper surface of the chip, and 302 is the lower surface of the chip.

[0049] (7) Figure 7 The second type of wafer-level chip shown in FIG. 1 is provided with a protective film layer pasted on the upper surface thereof, and the Figure 8 The structure shown in FIG. 103 is a protective film layer, and 303 is an upper surface of the protective film layer.

[0050] (8) Yes Figure 8 The back side of the second type of wafer-level chip is thinned and a non-conductive layer in a hybrid bonding technology is formed to obtain a Figure 9 The structure shown in FIG. 104 is a non-conductive layer, and the material of the layer in this embodiment is SiO2. 304 is the upper surface of the non-conductive layer 104.

[0051] (9) Figure 9 A conductive through-hole structure is formed at a position corresponding to the second type of wafer-level chip conductive structure on the structure shown in FIG. Figure 10 The structure shown in FIG. 1 shows a conductive through hole structure that penetrates the non-conductive layer 104 and the chip 101. 305 is a conductive through hole structure. The conductive through hole structure formed on the wafer-level chip must be located at a position that is staggered with the conductive structure of the chip.

[0052] (10) Figure 10 A conductive structure is formed at the conductive through-hole structure shown in the structure, and a conductive structure is obtained as shown in the figure.Figure 11 The structure shown. Among them, 105 is the conductive structure.

[0053] (11) Bond the wafer-level CIS chip obtained in step (5) and the second type of wafer-level chip obtained in step (10) through hybrid bonding technology to obtain the structure as Figure 12 shown. Among them, 106 is the non-conductive layer formed after bonding two wafers, and 107 is the conductive structure formed after bonding two wafers.

[0054] (12) Remove the upper surface film layer 103 of the wafer obtained after bonding two wafers as Figure 12 shown, and form the first insulating layer and the conductive via structure to obtain the structure as Figure 13 shown. Among them, 108 is the first insulating layer, 305 is the upper surface of the first insulating layer, and 306 is the conductive via structure formed on the first insulating layer. (13) Form the first metal redistribution layer on the wafer-level structure as Figure 13 shown to obtain the structure as Figure 14 shown. Among them, 109 is the first metal redistribution layer.

[0055] (14) Form the second insulating layer and the conductive via structure on the wafer-level structure as Figure 14 shown to obtain the structure as Figure 15 shown. Among them, 110 is the second insulating layer, 307 is the upper surface of the second insulating layer, and 308 is the conductive via structure formed on the second insulating layer.

[0056] (15) Form the second metal redistribution layer (i.e., the pad) on the wafer-level structure as Figure 15 shown to obtain the structure as Figure 16 shown. Among them, 111 is the second metal redistribution layer.

[0057] (16) Complete the ball mounting process on the wafer-level structure as Figure 16 shown to obtain the structure as Figure 17 shown. Among them, 112 is the solder ball structure.

[0058] (17) Cut the wafer as Figure 17 shown to obtain the structure of a single CIS chip integrated with other types of chips as Figure 18 shown.

[0059] As Figure 18As shown in the structure, in this embodiment, a CIS chip and other types of chips are integrated together through wafer-level packaging technology by means of hybrid bonding technology, and finally a system-integrated electronic product with high performance, low power consumption, miniaturization, heterogeneous process integration, and low cost is obtained. The specific layers in this structure are as follows: 10 - CIS chip, 11 - CIS photosensitive area, 12 - CIS conductive structure, 13 - high-transparency adhesive film layer, 14 - high-transparency glass layer, 101 - second type of chip, 102 - second type of chip conductive structure, 106 - non-bonding layer, 107 - conductive structure, 108 - first insulating layer, 109 - first metal redistribution layer, 110 - second insulating layer, 111 - second metal redistribution layer (pad), 112 - conductive structure (solder ball).

[0060] It should be noted that: in the description of the present invention, the meaning of "a plurality of" is two or more, unless otherwise specifically defined. In the present invention, unless otherwise clearly specified and limited, terms such as "installed", "connected", "connected", "fixed" and other terms should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection; the circuits described in the present invention are all common circuits in the art, and other related components are all existing common components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0061] For those skilled in the art, it is obvious that the present invention patent is not limited to the details of the above exemplary embodiments, and without departing from the spirit or basic characteristics of the present invention patent, the present invention patent can be implemented in other specific forms. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present invention patent is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the same elements of the claims are intended to be included in the present invention patent. Any reference signs in the claims should not be regarded as limiting the claimed claims.

Claims

1. A structure for preparing a wafer-level system-level package using hybrid bonding technology, characterized in that: It includes a wafer-level CIS chip and a second-type wafer-level chip; the wafer-level CIS chip includes a CIS chip upper surface and a CIS chip lower surface, and the CIS chip upper surface is provided with a photosensitive area and a conductive structure; The upper surface of the CIS chip is provided with an adhesive film layer and a glass layer with high light transmittance in sequence; The back side of the wafer-level CIS chip is thinned and a non-conductive layer is formed; A conductive through-hole structure is arranged on the non-conductive layer at a position corresponding to the conductive structure of the wafer-level CIS chip; A conductive structure is provided at the conductive through-hole structure; The second type of wafer-level chip comprises a chip upper surface and a chip lower surface, and the chip upper surface is provided with a chip conductive structure; A protective film layer is attached to the upper surface of the second type wafer-level chip; The back side of the second type of wafer-level chip is thinned and a non-conductive layer is formed; A conductive through-hole structure is formed at a position corresponding to the conductive structure of the second type of wafer-level chip on the non-conductive layer, and the conductive through-hole structure penetrates the non-conductive layer and the second type of wafer-level chip; the conductive through-hole structure formed on the wafer-level chip is located at a position staggered from the position of the conductive structure of the chip; A conductive structure is formed at the conductive through-hole structure; The wafer-level CIS chip with a conductive structure is bonded to the second type of wafer-level chip with a conductive structure by hybrid bonding technology to form a bonding structure, wherein the bonding structure includes a non-conductive layer formed after the two wafers are bonded and a conductive structure formed after the two wafers are bonded; Removing the film layer on the wafer surface obtained by bonding two wafers of the bonding structure, and forming a first insulating layer and a conductive through-hole structure; A first metal redistribution layer is disposed on the first insulating layer and the conductive via structure; A second insulating layer and a conductive via structure are disposed on the first metal redistribution layer; A second metal redistribution layer is disposed on the second insulating layer and the conductive via structure; Ball planting is completed on the second metal redistribution layer, and the ball planting is a solder ball structure.

2. The structure for preparing a wafer-level system-level package using hybrid bonding technology according to claim 1, characterized in that: The insulating layer is made of epoxy resin or silicon oxide insulating material.

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