Electronic package

Abstract

An electronic package includes forming at least one recess and a plurality of openings on a first side of a carrier, forming a plurality of conductive posts in the plurality of openings, and accommodating a first electronic component in the recess to form a plurality of conductive elements electrically connecting the plurality of conductive posts and the first electronic component on a second side of the carrier, and forming a circuit structure on the first side of the carrier to electrically connect the plurality of conductive posts and the first electronic component, so that the carrier is made of a semiconductor material, and the thermal expansion coefficients of the carrier and the first electronic component are matched to facilitate the dispersion of thermal stress.

Description

Technical Field

[0001] This application relates to a semiconductor device, especially an electronic package that can reduce energy consumption. Background Art

[0002] To ensure the continuous miniaturization and multifunctionality of electronic products and communication devices, semiconductor packaging needs to develop towards smaller sizes and have high functionality. For example, in advanced packaging processes, common packaging types such as 2.5D packaging processes, Fan-Out wiring combined with Embedded Bridge components (abbreviated as FO-EB), etc. Among them, FO-EB has advantages such as low cost and many material suppliers compared to 2.5D packaging processes.

[0003] Figure 1 FIG. 1 is a cross-sectional schematic view of an existing semiconductor package 1 of FO-EB. In this semiconductor package 1, a first semiconductor chip 11 and a plurality of conductive pillars 13 are disposed on a circuit structure 14 having a circuit layer 141, and then a first encapsulation layer 15 is used to cover the first semiconductor chip 11 and these conductive pillars 13. After that, a circuit structure 10 electrically connecting the first semiconductor chip 11 and these conductive pillars 13 is formed on the first encapsulation layer 15. Then, a plurality of second semiconductor chips 16 electrically connecting the circuit structure 10 are disposed on the circuit structure 10, and a second encapsulation layer 18 is used to cover these second semiconductor chips 16. Among them, the existing semiconductor package 1 is mainly placed on a circuit board (not shown) through a plurality of conductive elements 17 by the circuit structure 14.

[0004] However, in the existing semiconductor package 1, the coefficient of thermal expansion (CTE) of the first encapsulation layer 15 and the first semiconductor chip 11 does not match, and it is easy to have an uneven thermal stress situation. As a result, during thermal cycling, the first encapsulation layer 15 warps, leading to cracking of the semiconductor package 1 (especially the first and second semiconductor chips 11, 16). In addition, in the above-mentioned process, due to the uneven surface of the first encapsulation layer 15, it is easy to cause difficulties in subsequent processes.

[0005] Therefore, how to overcome the problems of the above-mentioned prior art has actually become an urgent issue to be solved currently. Summary of the Utility Model

[0006] In view of the above-mentioned deficiencies of the prior art, the present application provides an electronic package, comprising: a carrier having opposite first and second sides, wherein the carrier is provided with at least one groove and a plurality of openings, and the groove and the openings communicate with the first side and the second side; a plurality of conductive posts disposed in the plurality of openings; a first electronic component disposed in the groove; a plurality of conductive components disposed on the second side of the carrier and electrically connected to the plurality of conductive posts and the first electronic component; and a circuit structure disposed on the first side of the carrier and electrically connected to the plurality of conductive posts and the first electronic component.

[0007] The present application also provides a method for manufacturing an electronic package, comprising: providing a carrier having opposite first and second sides, wherein at least one groove and a plurality of openings are formed on the first side of the carrier, and the bottom surface of the groove and the bottom surfaces of the plurality of openings have a plurality of recesses; forming a plurality of conductive components in the plurality of recesses, forming a plurality of conductive posts in the plurality of openings, and placing a first electronic component in the groove to electrically connect the plurality of conductive components to the plurality of conductive posts and the first electronic component; forming a circuit structure on the first side of the carrier, and the circuit structure electrically connects the plurality of conductive posts and the first electronic component; and removing a part of the material on the second side of the carrier to expose the plurality of conductive components and to communicate the groove and the plurality of openings with the first side and the second side.

[0008] The present application further provides a method for manufacturing an electronic package, comprising: providing a carrier having opposite first and second sides, wherein a groove and a plurality of openings are formed on the first side of the carrier; forming a plurality of conductive posts in the plurality of openings, and placing a first electronic component in the groove; forming a circuit structure on the first side of the carrier, and the circuit structure electrically connects the plurality of conductive posts and the first electronic component; removing a part of the material on the second side of the carrier to expose the conductive posts and the first electronic component and to communicate the groove and the plurality of openings with the first side and the second side; and forming a plurality of conductive components on the conductive posts and the first electronic component to electrically connect the plurality of conductive components to the plurality of conductive posts and the first electronic component.

[0009] In the foregoing electronic package and its manufacturing method, the carrier is a plate made of semiconductor material.

[0010] In the foregoing electronic package and its manufacturing method, the first electronic component includes an electronic body made of a silicon substrate.

[0011] In the foregoing electronic package and its manufacturing method, at least one second electronic component electrically connected to the circuit structure is provided on the circuit structure. Further, it may include encapsulating the second electronic component with an encapsulation layer.

[0012] As described above, in the electronic package and its manufacturing method of the present application, mainly through the design of the carrier, the coefficient of thermal expansion between the carrier and the first electronic component is matched, which is beneficial to dispersing thermal stress. Therefore, compared with the prior art, when the present application undergoes a thermal cycle, warping of the carrier can be avoided, and thus fragmentation of the electronic package can be prevented. Description of the Drawings

[0013] Figure 1 It is a schematic cross-sectional view of a conventional semiconductor package.

[0014] Figures 2A to 2F It is a schematic cross-sectional view of the first embodiment of the manufacturing method of the electronic package of the present application.

[0015] Figures 3A to 3E It is a schematic cross-sectional view of the second embodiment of the manufacturing method of the electronic package of the present application.

[0016] Description of the Main Component Symbols

[0017] 1 Semiconductor package

[0018] 10, 20 Circuit structure

[0019] 11 First semiconductor chip

[0020] 13, 23 Conductive pillars

[0021] 14 Circuit structure

[0022] 141, 201 Circuit layer

[0023] 15 First encapsulation layer

[0024] 16 Second semiconductor chip

[0025] 17 Conductive element

[0026] 18 Second encapsulation layer

[0027] 2, 3 Electronic package

[0028] 2a First electronic component

[0029] 200 Insulating layer

[0030] 202 Electrical contact pad

[0031] 21 Electronic body

[0032] 21a First conductor

[0033] 21b First protective layer

[0034] 210 Conductive via

[0035] 22 Circuit section

[0036] 22a Second conductor

[0037] 22b Second protective layer

[0038] 220 Passivation layer

[0039] 221 Conductive trace

[0040] 230, 330 Opening

[0041] 24, 34 Carrier

[0042] 24a, 34a First side

[0043] 24b, 34b Second side

[0044] 240, 340 Groove

[0045] 25 Coating layer

[0046] 26 Second electronic component

[0047] 26a Conductive bump

[0048] 260, 27a Solder material

[0049] 262 Underfill

[0050] 27 Conductive component

[0051] 270 Metal body

[0052] 271 Metal post

[0053] 28 Encapsulation layer

[0054] 90 Recess

[0055] S Cutting path. Detailed implementation manners

[0056] The following illustrates the implementation manners of the present application through specific specific examples. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification.

[0057] It should be noted that the structures, proportions, sizes, etc. shown in the attached drawings of this specification are only used to cooperate with the content disclosed in the specification for the understanding and reading of those skilled in the art, and are not used to limit the conditions for the implementation of this application. Therefore, they do not have substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size, without affecting the efficacy that this application can produce and the purpose that can be achieved, should still fall within the scope that can be covered by the technical content disclosed in this application. At the same time, the terms such as "upper", "first", "second", "one", etc. cited in this specification are only for the convenience of clear narration and are not used to limit the scope for the implementation of this application. The change or adjustment of their relative relationship, without substantial change in the technical content, should also be regarded as the scope that this application can implement.

[0058] Figures 2A to 2F It is a cross-sectional schematic view of the first embodiment of the manufacturing method of the electronic package 2 of this application.

[0059] As Figure 2A shown, a carrier 24 is provided, and the carrier 24 has at least one groove 240 and a plurality of openings 230. Among them, the bottom surface of the groove 240 and the bottom surfaces of the plurality of openings 230 have a plurality of recesses 90.

[0060] In this embodiment, the carrier 24 is, for example, a plate made of a semiconductor material (such as silicon or glass), which has opposite first side 24a and second side 24b, so that the groove 240 and the openings 230 are formed on the first side 24a. For example, the groove 240, the recesses 90, and the openings 230 can be formed by etching or laser methods, so that the groove 240, the recesses 90, and the openings 230 do not penetrate the carrier 24.

[0061] As Figure 2B shown, a plurality of conductive elements 27 are formed in the plurality of recesses 90, a plurality of conductive posts 23 are formed in the plurality of openings 230, and at least one first electronic component 2a is accommodated in the groove 240.

[0062] The described first electronic component 2a includes an electronic body 21, a circuit portion 22, a plurality of first conductors 21a formed on the electronic body 21, and a plurality of second conductors 22a formed on the circuit portion 22 and electrically connected to the circuit portion 22, and the first electronic component 2a is accommodated in the groove 240 with its circuit portion 22 corresponding thereto.

[0063] In this embodiment, the electronic body 21 is made of a silicon-based material, such as a semiconductor chip, which has a plurality of conductive vias 210 penetrating the electronic body 21, such as through-silicon vias (TSV), to electrically connect the circuit portion 22 and the plurality of first conductors 21a. For example, the circuit portion 22 includes at least one passivation layer 220 and conductive traces 221 bonded to the passivation layer 220 to electrically connect the conductive traces 221 to the conductive vias 210 and the plurality of second conductors 22a. It should be understood that there are various aspects of the element structure having the conductive vias 210 and there is no particular limitation.

[0064] Furthermore, the first conductor 21a and the second conductor 22a are metal pillars such as copper pillars, and a first protective layer 21b is formed on the electronic body 21 to cover the first conductor 21a with the first protective layer 21b, and a second protective layer 22b is formed on the circuit portion 22 to cover the second conductor 22a with the second protective layer 22b, so that the first electronic component 2a is bonded to the carrier 24 with the second protective layer 22b thereon. For example, the first protective layer 21b is made of an insulating film or a polyimide (PI) material, and the second protective layer 22b is a non-conductive film (NCF) or other material that is easily adhered to the carrier 24.

[0065] The conductive pillar 23 is made of a metal material such as copper or a solder material, and can be formed by electroplating or other methods.

[0066] In this embodiment, a coating layer 25 can be first formed on the wall surface of the opening 230 to cover the conductive pillars 23 with the coating layer 25. For example, the coating layer 25 is an insulating material, such as polyimide (PI), dry film, an encapsulation colloid such as epoxy resin, or a molding compound.

[0067] The plurality of conductive elements 27 electrically connect the conductive pillars 23 and the second conductors 22a of the first electronic component 2a.

[0068] In this embodiment, the conductive element 27 includes a metal body 270 such as an under bump metallurgy (UBM) or a wiring layer, and a metal pillar 271 bonded to the metal body 270, such as a copper pillar, to form a solder material 27a such as a solder bump or a solder ball on the end surface of the metal pillar 271. Among them, one aspect of the metal body 270 is used to contact the second conductors 22a, and another aspect of the metal body 270 is used to contact the conductive pillars 23.

[0069] Furthermore, part of the conductive element 27 can be first formed on the first electronic component 2a, and then the conductive element 27 of the first electronic component 2a can be inserted into the recess 90. Alternatively, all of the conductive element 27 is formed in the recess 90, and then the second conductor 22a of the first electronic component 2a is electrically connected to the conductive element 27.

[0070] As Figure 2C shown, a circuit structure 20 is formed on the first side 24a of the carrier 24, and the circuit structure 20 is electrically connected to the conductive pillar 23 and the first conductor 21a.

[0071] In this embodiment, the circuit structure 20 includes at least one insulating layer 200 and a circuit layer 201 disposed on the insulating layer 200, such as the specification of a redistribution layer (RDL). Among them, the outermost insulating layer 200 can be used as a solder mask layer, and the outermost circuit layer 201 is exposed outside the solder mask layer for use as an electrical contact pad 202, such as a micro pad (commonly known as μ-pad).

[0072] Furthermore, the material for forming the circuit layer 201 is copper, and the material for forming the insulating layer 200 is a dielectric material such as Polybenzoxazole (PBO), Polyimide (PI), Prepreg (PP), etc., or a solder mask material such as green paint or ink.

[0073] As Figure 2D shown, a plurality of second electronic components 26 are disposed on the circuit structure 20, and then the second electronic components 26 are encapsulated by a packaging layer 28.

[0074] The second electronic component 26 described above is an active component, a passive component, or a combination of the two. The active component is, for example, a semiconductor chip, and the passive component is, for example, a resistor, a capacitor, and an inductor.

[0075] In this embodiment, the second electronic component 26 is, for example, a semiconductor chip such as a graphics processing unit (GPU), a High Bandwidth Memory (HBM), etc., without particular limitation. For example, the first electronic component 2a serves as a bridge die, which is electrically connected to the circuit structure 20 through the first conductor 21a to electrically bridge at least two second electronic components 26.

[0076] Furthermore, the second electronic component 26 has a plurality of conductive bumps 26a such as copper blocks to electrically connect to the electrical contact pads 202 through the solder materials 260 of the plurality of solder bumps, and the encapsulation layer 28 can simultaneously encapsulate the second electronic components 26 and the conductive bumps 26a. For example, a UBM (not shown) can be formed on the electrical contact pads 202 to facilitate the bonding of the conductive bumps 26a.

[0077] The encapsulation layer 28 is an insulating material such as polyimide (PI for short), dry film, encapsulation colloid such as epoxy resin, or molding compound, and can be formed on the circuit structure 20 by lamination or molding. It should be understood that the material for forming the encapsulation layer 28 can be the same as or different from the material of the coating layer 25.

[0078] In this embodiment, an underfill 262 can be first formed between the second electronic component 26 and the circuit structure 20 to encapsulate the conductive bumps 26a, and then the encapsulation layer 28 is formed to encapsulate the underfill 262 and the second electronic component 26. Alternatively, the formation of the underfill 262 can be omitted, and the encapsulation layer 28 can directly encapsulate the conductive bumps 26a and the second electronic component 26.

[0079] As Figure 2E shown, a part of the material on the second side 24b of the carrier 24 is removed to expose the conductive element 27, and the groove 240 and the openings 230 communicate the first side 24a and the second side 24b.

[0080] In this embodiment, a part of the material on the second side 24b of the carrier 24 is removed by etching or other means.

[0081] Due to the design that the groove 240 does not penetrate the carrier 24, after removing a part of the material on the second side 24b of the carrier 24, the carrier 24 still encapsulates the first electronic component 2a, so that the first electronic component 2a is not exposed to the external environment (or air), thus avoiding damage to the first electronic component 2a. In addition, the first electronic component 2a is disposed in the groove 240 of the carrier 24, and there is no need to use a Die Attach Film (DAF), which can avoid peeling and hole problems.

[0082] As Figure 2F shown, a dicing process is performed along the dicing path S as Figure 2E shown to obtain a plurality of electronic packages 2.

[0083] Subsequently, the electronic package 2 can be disposed on an electronic device (not shown) such as a circuit board through the conductive elements 27.

[0084] In addition, part of the material of the encapsulation layer 28 can be removed through a planarization process, such as grinding, to make the upper surface of the encapsulation layer 28 flush with the upper surface of the second electronic component 26, so that the second electronic component 26 is exposed from the encapsulation layer 28.

[0085] Therefore, in the manufacturing method of the present application, a plate body made of semiconductor material is mainly used as the carrier 24 to wrap the first electronic component 2a, so that the coefficient of thermal expansion (CTE) between the carrier 24 and the first electronic component 2a is matched, which is beneficial to dispersing thermal stress. Therefore, compared with the prior art, during thermal cycling of the present application, warping of the carrier 24 can be avoided, so that reliability problems such as cracking of the electronic package 2 or the first electronic component 2a (even the second electronic component 26), poor ball conditions (i.e., the conductive component 27 falls off and causes electrical open circuit), non-wetting of the conductive component 27, or delamination of the circuit structure 20 can be avoided, thereby improving the reliability of the terminal electronic products (such as computers, mobile phones, etc.) applying the electronic package. In addition, by providing a plurality of recesses 90 on the bottom surface of the groove 240 and the bottom surfaces of the plurality of openings 230 in the carrier 24 for forming the conductive components 27 therein subsequently, the contact area of the conductive components 27 can be increased, and problems such as detachment or cracking can be improved.

[0086] Furthermore, the carrier 24 is a hard silicon structure and is not prone to thermal deformation, so the surface of its first side 24a can be maintained flat. Therefore, the circuit structure 20 of the present application can be formed flat on the carrier 24, enabling the circuit layer 201 to effectively connect to the conductive posts 23 and the first conductor 21a, which is beneficial to improving the electrical yield of the electronic package 2.

[0087] In addition, by forming the openings 230 in the carrier 24, the wall surfaces thereof have better flatness, so a vertically conductive circuit with better structure, that is, the conductive post 23, can be obtained to improve the reliability of the product.

[0088] Figures 3A to 3E It is a cross-sectional schematic view of the second embodiment of the manufacturing method of the electronic package 3 of the present application. The difference between this embodiment and the first embodiment lies in the omission of the recesses 90, and the other manufacturing processes are substantially the same, so the same parts will not be described again.

[0089] As Figure 3A shown, a carrier 34 is provided, and the carrier 34 has opposite first side 34a and second side 34b, and is provided with at least one groove 340 and a plurality of openings 330.

[0090] As Figure 3BAs shown, a plurality of conductive posts 23 are formed in the plurality of openings 330, and at least one first electronic component 2a is accommodated in the groove 340.

[0091] As Figure 3C shown, a circuit structure 20 is formed on the first side 34a of the carrier 34, and the circuit structure 20 is electrically connected to the conductive post 23 and the first conductor 21a.

[0092] As Figure 3D shown, a plurality of second electronic components 26 are disposed on the circuit structure 20, and then the plurality of second electronic components 26 are encapsulated with a packaging layer 28.

[0093] As Figure 3E shown, a part of the material on the second side 34b of the carrier 34 is removed to expose the second protective layer 22b, the second conductor 22a and the conductive post 23, and the groove 340 and the openings 330 communicate with the first side 34a and the second side 34b. Then, a plurality of conductive components 27 are formed on the plurality of second conductors 22a and the plurality of conductive posts 23. After that, a dicing process is performed to obtain a plurality of electronic packages 3.

[0094] This application also provides an electronic package 2, 3, including: a carrier 24, 34, at least one first electronic component 2a, a plurality of conductive posts 23, a plurality of conductive components 27, and a circuit structure.

[0095] The carrier 24, 34 has opposite first and second sides 24a and 24b, wherein the carrier 24, 34 has at least one groove 240, 340 and a plurality of openings 230, 330, and the groove 240, 340 and the openings 230, 330 communicate with the first side 24a, 34a and the second side 24b, 34b.

[0096] The plurality of conductive posts 23 are disposed in the plurality of openings 230, 330.

[0097] The first electronic component 2a is disposed in the groove 240, 340.

[0098] The conductive component 27 is disposed on the second side 24b, 34b of the carrier 24, 34 and is electrically connected to the conductive post 23 and the first electronic component 2a.

[0099] The circuit structure 20 is disposed on the first side 24a, 34a of the carrier 24, 34 and is electrically connected to the conductive post 23 and the first electronic component 2a.

[0100] In one embodiment, the carrier 24, 34 is a plate made of semiconductor material.

[0101] In one embodiment, the first electronic component 2a includes an electronic body 21 made of a silicon substrate.

[0102] In one embodiment, at least one second electronic component 26 electrically connected to the circuit structure 20 is provided on the circuit structure 20. Further, the electronic packages 2, 3 further include a packaging layer 28 covering the second electronic component 26.

[0103] In summary, for the electronic package and its manufacturing method of the present application, by using a plate body made of a semiconductor material as a carrier, the coefficient of thermal expansion (CTE) between the carrier and the first electronic component is matched, which is beneficial to dispersing thermal stress. Therefore, when the present application is in a thermal cycle, warping of the carrier can be avoided, and thus fragmentation of the electronic package can be avoided.

[0104] The above embodiments are only used to exemplarily illustrate the principles and effects of the present application, rather than to limit the present application. Any person skilled in the art can modify the above embodiments without departing from the spirit and scope of the present application. Therefore, the scope of the rights protection of the present application shall be as listed in the claims.

Claims

1. An electronic package, characterized in that: include: A carrier having a first side and a second side opposite to each other, and provided with a groove and a plurality of openings, wherein the groove and the plurality of openings are connected to the first side and the second side; A plurality of conductive posts disposed in the plurality of openings; A first electronic component is disposed in the groove; A plurality of conductive elements, which are disposed on the second side of the carrier and electrically connect the plurality of conductive pillars and the first electronic element; as well as The circuit structure is disposed on the first side of the carrier and electrically connects the plurality of conductive pillars and the first electronic element.

2. The electronic package according to claim 1, wherein: The carrier is a plate made of semiconductor material.

3. The electronic package according to claim 1, wherein: The first electronic component includes an electronic body of a silicon substrate.

4. The electronic package according to claim 1, wherein: A second electronic element electrically connected to the circuit structure is disposed on the circuit structure.

5. The electronic package as claimed in claim 4, characterized in that The electronic package also includes a packaging layer covering the second electronic component.

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