Circuit for suppressing surge current of high-power load
By connecting series resistors and parallel field effect tubes on the filter capacitor, the problem of excessive inductance cost and volume in the prior art is solved, effectively suppressing the surge current of high-power loads and maintaining the integrity of the original circuit design.
Patent Information
- Application Number
- CN202422084636.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-27
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-08-27
AI Technical Summary
When the prior art suppresses inrush current of high-power loads, the cost and volume of the inductor are too large, and the requirements for filter capacitors are increased, affecting the circuit design.
The series resistor is connected to the filter capacitor and the field effect tube is connected to the series resistor. The field effect tube is turned off immediately when powering on the power supply. By increasing the internal resistance of the filter capacitor, the surge current is reduced. After the surge instantly passes, the control field effect transistor turns on and restores the filter capacitor function.
It effectively reduces the instantaneous inrush current of the product when powering on, and at the same time, it hardly affects the original circuit design, reduces the use of inductors, and reduces the cost and volume.
Smart Images
Figure CN223052752U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of circuit design, and particularly relates to a circuit for suppressing inrush current of high-power loads, which is applicable to products with large capacitance of input filter capacitors for high-power loads and requiring small inrush current.
Background Art
[0002] For products with high-power loads to ensure low power supply ripple, generally, a larger capacitance of the filter capacitor is required, resulting in a larger input inrush current when the product is powered on. The upper-level power supply system of the product may be instantaneously pulled down the output power supply voltage under the influence of too large inrush current, thus affecting the circuit function, or the Fuse (i.e., fuse) connected in series at the upper level may be burned out.
[0003] Please refer to Figure 1 As shown, it is a schematic diagram of a circuit for suppressing inrush current in the prior art, in which an inductor L100 is connected in series at the front stage of a capacitor C100, and the inrush current is reduced by using the characteristic of the inductor to suppress current mutation.
[0004] Figure 1 Problems and disadvantages of the existing technical solution shown:
[0005] ①. The inductor L100 is affected by the working current of the product. The larger the load R L The larger the current-carrying capacity required for the inductor L100. The cost increases with the increase of the current.
[0006] ②. The greater the power consumption of the load R L The larger the filter capacitor C100. To suppress a larger inrush current, the inductor L100 needs a larger inductance value. The cost increases with the increase of the filter capacitor C100.
[0007] ③. Due to the inductor L100 with large current and large inductance value, the volume is too large and a higher structural space is required. This limits the structural design.
[0008] Therefore, it is necessary to propose a new technical solution to solve the above problems.
Content of the Utility Model
[0009] One of the purposes of the utility model is to provide a circuit for suppressing inrush current of high-power loads, which can not only reduce the inrush current when the product is powered on, but also hardly affect the original circuit design.
[0010] According to one aspect of the present utility model, the present utility model provides a circuit for suppressing inrush current of a high-power load, which includes: a voltage conversion circuit, whose input end is connected to the power input terminal Vin, and whose output end is connected to the power output terminal Vout; a capacitor C100, one end of which is connected to the power input terminal Vin, and the other end of which is connected to node A; a resistor R102, one end of which is connected to the node A, and the other end of which is grounded; a switch control circuit, which includes a MOS transistor Q103 and a resistor R103, the first connection end of the MOS transistor Q103 is connected to the node A, the second connection end of which is grounded, and the control end of which is connected to node D through the resistor R103; a voltage sampling circuit, whose input end is connected to the power input terminal Vin, and whose output end outputs a sampling voltage, and the sampling voltage is generated by the voltage sampling circuit based on the voltage of the power input terminal Vin; a main control circuit, whose power supply end is connected to the power output terminal Vout, and whose input end is connected to the output end of the voltage sampling circuit; a driving circuit, whose power supply end is connected to the power input terminal Vin, whose input end is connected to the first output end of the main control circuit, and whose output end is connected to the node D.
[0011] Compared with the prior art, in the present utility model, a resistor is connected in series with the filter capacitor, and a field effect transistor is connected in parallel with the series resistor. At the moment when the power supply is powered on, the field effect transistor is controlled to turn off. By connecting a resistor in series with the filter capacitor, it is equivalent to increasing the internal resistance of the filter capacitor, so that the working current at the moment of power-on is hindered by the resistor and the inrush current is reduced; after the inrush moment has passed, the field effect transistor is controlled to turn on to short-circuit the series resistor and restore the function of the filter capacitor, thereby achieving both reducing the inrush current of the product at the moment of power-on and hardly affecting the original circuit design.
Description of the Drawings
[0012] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained according to these drawings. Among them:
[0013] Figure 1 It is a schematic diagram of a circuit for suppressing inrush current in the prior art;
[0014] Figure 2 It is a schematic diagram of the circuit for suppressing inrush current of a high-power load in an embodiment of the present utility model.
Detailed Embodiments
[0015] In order to make the above-mentioned objects, features, and advantages of the present utility model more obvious and understandable, the present utility model will be further described in detail below with reference to the drawings and specific embodiments.
[0016] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present utility model. The phrase "in one embodiment" that appears in different places in this specification does not necessarily refer to the same embodiment, nor is it an individual or alternative embodiment that is mutually exclusive with other embodiments. Unless otherwise specified, the terms "coupled", "connected", "joined", and "connected" that indicate electrical connection in this article all mean directly or indirectly connected. For example, when A is connected to B, it includes both direct electrical connection between A and B and connection between A and B through electrical components or circuits.
[0017] In the description of the present utility model, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present utility model and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the present utility model.
[0018] Please refer to Figure 2 as shown, which is a schematic diagram of a circuit for suppressing inrush current of a high-power load in one embodiment of the present utility model. Figure 2 The circuit for suppressing inrush current of the high-power load shown includes a voltage conversion circuit, a filter capacitor C100, a resistor R102, a switch control circuit 210, a voltage sampling circuit 220, a main control circuit U2, and a drive circuit 230. In Figure 2 the specific embodiment shown, the main control circuit U2 is an MCU (Microcontroller Unit, i.e., micro control unit). In one embodiment, the voltage conversion circuit is an LDO (Low-dropout regulator, i.e., low-voltage differential linear voltage regulator) power supply circuit U1.
[0019] Among them, the input terminal Vin of the LDO power supply circuit U1 is connected to the power input terminal Vin, its output terminal Vout is connected to the power output terminal Vout, and its ground terminal GND is grounded; one end of the filter capacitor C100 is connected to the power input terminal Vin, and the other end is connected to node A; one end of the resistor R102 is connected to node A, and the other end is grounded; the switch control circuit 210 includes a MOS transistor (metal oxide semiconductor, hereinafter referred to as a field effect transistor) Q103 and a resistor R103. The first connection terminal of the MOS transistor Q103 is connected to node A, its second connection terminal is grounded, and its control terminal is connected to node D through the resistor R103; the input terminal of the voltage sampling circuit 220 is connected to the power input terminal Vin, and its output terminal outputs a sampling voltage, which is generated by the voltage sampling circuit 220 based on the voltage of the power input terminal Vin; the power supply terminal VCC of the main control circuit U2 is connected to the power output terminal Vout, and its input terminal ADC is connected to the output terminal of the voltage sampling circuit 220; the power supply terminal of the drive circuit 230 is connected to the power input terminal Vin, its input terminal is connected to the first output terminal I / O1 of the main control circuit U2, and its output terminal is connected to node D.
[0020] At the instant when the system is powered on (or at the instant when the power input terminal Vin is powered on), the main control circuit U2 does not work, and the first output terminal I / O1 of the main control circuit U2 outputs an invalid drive signal, and the drive circuit 230 controls the MOS transistor Q103 to turn off (or cut off) based on the voltage of the power input terminal Vin; after the instant when the system is powered on (or after the instant when the power input terminal Vin is powered on), the LDO power supply circuit U1 supplies power to the main control circuit U2 through its output terminal Vout, and the main control circuit U2 works. If the main control circuit U2 detects that the system power supply is stable (or the power supply of the power input terminal Vin is stable) based on the sampling voltage output by the voltage sampling circuit 220, then the first output terminal I / O1 of the main control circuit U2 outputs a valid drive signal, and the drive circuit 230 controls the MOS transistor Q103 to turn on based on this valid drive signal. In this way, at the instant when the power supply (or the power input terminal Vin) is powered on, the MOS transistor Q103 is controlled to turn off, and by connecting the resistor R102 in series with the filter capacitor C100, it is equivalent to increasing the internal resistance of the filter capacitor C100, so that the working current at the instant of power on is hindered by the resistor and the inrush current is reduced; after the inrush instant has passed, the MOS transistor Q103 is controlled to turn on, short-circuiting the series resistor R102 and restoring the function of the filter capacitor C100, thus achieving both reducing the inrush current at the instant of product power on and hardly affecting the original circuit design.
[0021] The drive circuit 230 includes a resistor R104, a resistor R105, a resistor R106, a triode Q100, a triode Q101, and a triode Q102. Among them, one end of the resistor R106 is connected to the power input terminal Vin, and the other end is connected to the node B; one end of the resistor R104 is connected to the power input terminal Vin, and the other end is connected to the node C; the first connection end of the triode Q102 is connected to the node C, the second connection end is grounded, and the control end is connected to the node B through the resistor R105; the node B can be used as the input end of the drive circuit 230 and is connected to the first output end I / O1 of the main control circuit U2; the first connection end of the triode Q101 is connected to the power input terminal Vin, the control end is connected to the node C, and the second connection end is connected to the node D; the first connection end of the triode Q100 is connected to the node D, the control end is connected to the node C, and the second connection end is grounded; the node D can be used as the output end of the drive circuit 230.
[0022] The voltage sampling circuit 220 includes a resistor R100 and a resistor R101. One end of the resistor R100 is connected to the power input terminal Vin, and the other end is connected to the node E; one end of the resistor R101 is connected to the node E, and the other end is grounded; the node E is the output end of the voltage sampling circuit 220, and the voltage of the node E is the sampling voltage.
[0023] In Figure 2 In the specific embodiment shown, the drive circuit 230 further includes a capacitor C102. One end of the capacitor C102 is connected to the power input terminal Vin, and the other end is connected to the node B; the switch control circuit 210 further includes a capacitor C101. One end of the capacitor C101 is connected to the control end of the MOS transistor Q103, and the other end is grounded.
[0024] In Figure 2 In the specific embodiment shown, the MOS transistor Q103 is an NMOS transistor. The first connection end, the second connection end, and the control end of the MOS transistor Q103 are respectively the drain D, the source S, and the gate G of the NMOS transistor; the triode Q100 is a PNP type triode. The first connection end, the second connection end, and the control end of the triode Q100 are respectively the emitter, the collector, and the base of the PNP type triode; the triode Q101 is an NPN type triode. The first connection end, the second connection end, and the control end of the triode Q101 are respectively the collector, the emitter, and the base of the NPN type triode; the triode Q102 is an NPN type triode. The first connection end, the second connection end, and the control end of the triode Q102 are respectively the collector, the emitter, and the base of the NPN type triode.
[0025] Figure 2 The circuit for suppressing the inrush current of the high-power load shown also includes a load R L , load R LThe power supply terminal is connected to the power output terminal Vout, and its enable terminal EN is connected to the second output terminal I / O2 of the main control circuit U2. At the instant when the system is powered on (or at the instant when the power input terminal Vin is powered on), the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled, causing the load R L not to work; after the instant when the system is powered on (or after the instant when the power input terminal Vin is powered on), if the main control circuit U2 detects that the system power supply is stable (or the power supply of the power input terminal Vin is stable) based on the sampled voltage output by the voltage sampling circuit 220, its second output terminal I / O2 outputs a valid enable signal Enable, causing the load R L to work.
[0026] The following is a specific introduction Figure 2 to the working process of the circuit for suppressing the inrush current of the high-power load shown in Figure 2 In the specific embodiment shown, the conduction voltages of the triodes Q100, Q101, and Q102 are 0.7V. In other embodiments, the conduction voltages of the triodes Q100, Q101, and Q102 can also be other voltage values.
[0027] At the instant when the system is powered on (or at the instant when the power input terminal Vin is powered on), the default power-on state of the first output terminal I / O1 of the main control circuit U2 is high level or floating state (that is, the invalid drive signal output by the first output terminal I / O1 of the main control circuit U2 is high level or floating state). The base (b) of the triode Q102 is pulled up to high level by the resistor R106. The Vbe of the triode Q102 (VBE refers to the voltage difference between the base and emitter of the triode) > 0.7V, and the triode Q102 is set to the saturation state (that is, the triode Q102 conducts). The Vce of the triode Q102 (representing the voltage difference between the collector and emitter of the triode) will < 0.3V, and the Vbe of the triode Q101 will < 0.3V and be in the cut-off state (that is, the triode Q101 is turned off). The voltage of the emitter (e) of the triode Q101 (that is, the voltage of node D) < 0.3V. The Vgs (that is, the gate-source voltage) of the field effect transistor (or MOS transistor) Q103 is less than Vgs(th) (that is, the turn-on voltage of the MOS transistor), and the field effect transistor (or MOS transistor) Q103 is in the cut-off (or turned-off) state.
[0028] That is to say, at the instant when the system is powered on (or at the instant when the power input terminal Vin is powered on), the main control circuit U2 does not work. The triode Q102 in the drive circuit 230 conducts, the triode Q101 is cut off, and the triode Q100 conducts, thereby controlling the voltage of node D to make the MOS transistor Q103 cut off (or turned off). Since the series impedance of the filter capacitor C100 and the resistor R102 is much smaller than that of the other parallel circuits, the transient inrush current is:
[0029] I_inrush≈Vin÷(ESR C100 +R102)
[0030] The resistance value of resistor R102 is selected as x times of ESR C100 , and the corresponding inrush current can be reduced to 1 / (1 + x), which can effectively reduce the inrush current. ESR is Equivalent Series Resistance, that is, equivalent series resistance. Usually, ESR C100 is less than 100 mΩ. Therefore, even if resistor R102 is 10 times of ESR C100 , it is only 1 Ω. At this time, the internal resistance of the filter capacitor circuit (which includes filter capacitor C100, resistor R102 and field effect transistor Q103) is equivalent to ESR C100 +R102.
[0031] Since at the instant when the system is powered on (or at the instant when the power input terminal Vin is powered on), the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled (or at this time, the enable terminal EN is designed to default to the Disabled state), therefore, the load R L does not work.
[0032] After the system is powered on instantaneously (or after the power input terminal Vin is powered on instantaneously), the LDO power supply circuit U1 starts to work normally. The output terminal Vout of the LDO power supply circuit U1 supplies power to the main control circuit U2 and the load R L . After the main control circuit U2 is powered on and starts to work, after the resistors R100 and R101 are connected in series for voltage division, the analog voltage signal (i.e., the reference voltage signal) of node E is collected by the input terminal ADC of the main control circuit U2 to identify the voltage state of the power input terminal Vin. When it is judged that the power input terminal Vin is within the correct working voltage range (i.e., when it is detected that the power supply of the power input terminal Vin is stable), the first output terminal I / O1 of the main control circuit U2 is set to a low level (which is a valid drive signal). The Vbe of the triode Q102 is less than the conduction voltage of 0.7 V, and the triode Q102 is cut off (or turned off). The voltage of the collector (c) of the triode Q102 is approximately equal to the voltage of the power input terminal Vin. Through the emitter diode of the triode Q101 (i.e., the triode Q101 is turned on), the working voltage of the emitter (e) of the triode Q101 is Vin - 0.7 V. The Vgs of the field effect transistor Q103 will be greater than Vgs(th), and the field effect transistor Q103 is in the saturation state (i.e., the field effect transistor Q103 is turned on), and the resistor R102 will be connected in parallel with the RDS_Q103 of the field effect transistor Q103. At this time, the internal resistance of the filter capacitor circuit (which includes filter capacitor C100, resistor R102 and field effect transistor Q103) ≈ ESR C100+(RDS_Q103||R102). RDS_Q103 is the on-resistance of the D-S (i.e., drain and source) of the field-effect transistor Q103. Usually, this value is about 10 mΩ, which hardly affects the original circuit design. The filter capacitor C100 functions normally.
[0033] That is to say, after the system is powered on instantaneously (or after the power input terminal Vin is powered on instantaneously), if the main control circuit U2 detects the stable power supply of the power input terminal Vin based on the sampled voltage output by the voltage sampling circuit 220, the first output terminal I / O1 of the main control circuit U2 outputs a valid drive signal, so that the triode Q102 in the drive circuit 230 is turned off, the triode Q101 is turned on, and the triode Q100 is turned off, thereby controlling the voltage of the node D to turn on the MOS transistor Q103.
[0034] After the filter capacitor C100 functions normally, the main control circuit U2 controls the second output terminal I / O2 to set the enable terminal EN to the Enable state to enable the load R L to start normal operation.
[0035] In Figure 2 the circuit for suppressing inrush current of the high-power load shown, the filter capacitor C100, resistor R102, MOS transistor Q103, resistor R103, triode Q101, triode Q100, resistor R104, triode Q102, resistor R105, resistor R106, resistor R100, resistor R101, main control circuit U2, and LDO power supply circuit U1 are core components and are theoretically essential. At the instant of power-on, the first output terminal I / O2 of the main control circuit U2 is at a high level or floating. It is necessary to make the triode Q102 default to the saturation state at the instant of power-on through the resistors R106 and R105. Vc_Q102 is about 0.3 V, and the output levels Ve_Q101 of the triodes Q101 and Q100 are pulled down by the saturation state of the triode Q102 to about 0.3 V, so that the field-effect transistor Q103 is in the cut-off state, and the inrush current when the system is powered on is limited by the resistor R102 and drops to about 1 / (1 + x) (note: x = R102 ÷ ESR C100) When the LDO power supply circuit U1 outputs Vout normally after the transient passes, the main control circuit U2 starts to work normally. The ADC at the input end of the main control circuit U2 can determine whether the power input terminal Vin is stable through the divided voltage analog signal of the resistor R100 and the resistor R101. After determining that the power input terminal Vin is stable, the first output terminal I / O1 outputs a low level, and the triode Q102 is cut off (or turned off). The resistor R104 can raise the potential of Vc_Q102 when the field effect transistor Q102 is cut off to Vin (Vin voltage is greater than the working voltage of the main control circuit U2. For example: Vin = 9V - 16V, usually the working voltage of the main control circuit U2 is 3.3V or 5V and cannot quickly switch the field effect transistor Q103). The resistor R103 can slow down the switching speed of the field effect transistor Q103 and smoothly switch the working state of the field effect transistor Q103, so that the levels driven and output by the triodes Q101 and Q100 are approximately equal to the voltage of the power input terminal Vin, so that the field effect transistor Q103 can be completely switched from the cut-off state to the saturation state, and the internal resistance of the filter capacitor loop of the system is reduced to ESR C100 +(RDS_Q103||R102), and the filter capacitor C100 works normally. It realizes both reducing the inrush current at the moment of power-on of the product and hardly affecting the original circuit design.
[0036] In Figure 2 In the circuit for suppressing inrush current of high-power loads shown, the capacitors C101 and C102 are non-core components. The capacitor C102 is used to make the rising saturation state response of the triode Q102 faster, and the capacitor C101 is used to make the field effect transistor Q103 switch between the cut-off / saturation states more smoothly.
[0037] It should be particularly noted that: the filter capacitor C100 can be a parallel connection of multiple capacitors and then series-connected with the resistor R102; the field effect transistor Q103 can be P or N-channel. The core concept is that the field effect transistor Q103 is in the cut-off state at the moment of power-on and in the saturation state after the power-on is stable. If the field effect transistor Q103 is P or N-channel, the corresponding driving method can be selected.
[0038] In summary, for the circuit provided by the present utility model for suppressing inrush current of high-power loads, a resistor R102 is connected in series with the filter capacitor C100, and a field-effect transistor Q103 is connected in parallel with the series resistor R102. At the instant when the power is applied to the power input terminal Vin, the field-effect transistor Q103 is controlled to turn off. By connecting the resistor R102 in series with the filter capacitor C100, it is equivalent to increasing the internal resistance of the filter capacitor C100, so that the working current at the instant of power-on is hindered by the resistor and the inrush current is reduced. After the inrush instant has passed, after the LDO power supply circuit U1 is powered on, it supplies power to the main control circuit U2. The main control circuit U2 judges whether the power supply of the power input terminal Vin is stable based on the sampling voltage output by the voltage sampling circuit 220 received through its input terminal ADC. If it is detected that the power supply of the power input terminal Vin is stable, the main control circuit U2 outputs a valid drive signal through its first output terminal I / O1, so that the drive circuit 230 controls the MOS transistor Q103 to turn on based on this valid control signal, short-circuits the series resistor R102, and restores the function of the filter capacitor C100, thereby achieving the reduction of the inrush current at the instant of power-on of the product with almost no impact on the original circuit design.
[0039] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present utility model do not depart from the scope of the claims of the present utility model. Correspondingly, the scope of the claims of the present utility model is not limited solely to the foregoing specific embodiments.
Claims
1. A circuit for suppressing surge current of a high-power load, characterized in that: It includes: A voltage conversion circuit, whose input terminal is connected to the power input terminal Vin, and whose output terminal is connected to the power output terminal Vout; A capacitor C100, one end of which is connected to the power input terminal Vin, and the other end of which is connected to the node A; A resistor R102, one end of which is connected to the node A, and the other end of which is grounded; A switch control circuit, comprising a MOS transistor Q103 and a resistor R103, wherein a first connection end of the MOS transistor Q103 is connected to the node A, a second connection end thereof is grounded, and a control end thereof is connected to the node D via the resistor R103; A voltage sampling circuit, whose input end is connected to the power input end Vin, and whose output end outputs a sampling voltage, wherein the sampling voltage is generated by the voltage sampling circuit based on the voltage of the power input end Vin; A main control circuit, whose power supply terminal is connected to the power supply output terminal Vout, and whose input terminal is connected to the output terminal of the voltage sampling circuit; The driving circuit has a power supply terminal connected to the power input terminal Vin, an input terminal connected to the first output terminal of the main control circuit, and an output terminal connected to the node D.
2. The circuit for suppressing surge current of a high-power load according to claim 1, characterized in that: When the power input terminal Vin is powered on, the main control circuit does not work, the first output terminal of the main control circuit outputs an invalid drive signal, and the drive circuit controls the MOS tube Q103 to turn off based on the voltage of the power input terminal Vin; After the power input terminal Vin is powered on, the voltage conversion circuit supplies power to the main control circuit through its output terminal, and the main control circuit works. If the main control circuit detects that the power input terminal Vin is powered stably based on the sampled voltage, the first output terminal of the main control circuit outputs a valid drive signal, and the drive circuit controls the MOS tube Q103 to be turned on based on the valid drive signal.
3. The circuit for suppressing surge current of a high-power load according to claim 2, characterized in that: The driving circuit includes a resistor R104, a resistor R105, a resistor R106, a transistor Q100, a transistor Q101 and a transistor Q102. One end of the resistor R106 is connected to the power input terminal Vin, and the other end thereof is connected to the node B; one end of the resistor R104 is connected to the power input terminal Vin, and the other end thereof is connected to the node C; the first connection end of the transistor Q102 is connected to the node C, the second connection end thereof is grounded, and the control end thereof is connected to the node B via the resistor R105; the node B is connected to the first output end of the main control circuit; the first connection end of the transistor Q101 is connected to the power input terminal Vin, the control end thereof is connected to the node C, and the second connection end thereof is connected to the node D; the first connection end of the transistor Q100 is connected to the node D, the control end thereof is connected to the node C, and the second connection end thereof is grounded, The voltage conversion circuit is an LDO power supply circuit.
4. The circuit for suppressing surge current of a high-power load according to claim 3, characterized in that: The voltage sampling circuit includes a resistor R100 and a resistor R101. One end of the resistor R100 is connected to the power input terminal Vin, and the other end thereof is connected to the node E; One end of the resistor R101 is connected to the node E, and the other end thereof is grounded; The node E is the output end of the voltage sampling circuit, and the voltage of the node E is the sampling voltage.
5. The circuit for suppressing surge current of a high-power load according to claim 4, characterized in that: The driving circuit further includes a capacitor C102 , one end of which is connected to the power input terminal Vin, and the other end of which is connected to the node B.
6. The circuit for suppressing surge current of a high-power load according to claim 5, characterized in that: The switch control circuit further includes a capacitor C101, one end of which is connected to the control end of the MOS transistor Q103, and the other end of which is grounded.
7. The circuit for suppressing surge current of a high-power load according to claim 3, characterized in that: When the power input terminal Vin is powered on, the main control circuit does not work, the transistor Q102 in the drive circuit is turned on, the transistor Q101 is turned off, and the transistor Q100 is turned on, thereby controlling the voltage of the node D so that the MOS transistor Q103 is turned off; After the power input terminal Vin is powered on, if the main control circuit detects that the power supply of the power input terminal Vin is stable based on the sampled voltage, the first output terminal of the main control circuit outputs a valid drive signal, so that the transistor Q102 in the drive circuit is turned off, the transistor Q101 is turned on, and the transistor Q100 is turned off, thereby controlling the voltage of the node D to turn on the MOS tube Q103.
8. The circuit for suppressing surge current of a high-power load according to claim 7, characterized in that: The MOS transistor Q103 is an NMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q103 are respectively the drain, the source and the gate of the NMOS transistor; The transistor Q100 is a PNP transistor, and the first connection end, the second connection end and the control end of the transistor Q100 are respectively the emitter, the collector and the base of the PNP transistor; The transistor Q101 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q101 are respectively the collector, the emitter and the base of the NPN transistor; The transistor Q102 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q102 are respectively the collector, the emitter and the base of the NPN transistor.
9. The circuit for suppressing surge current of a high-power load according to claim 8, characterized in that: The invalid driving signal is in a high level or floating state; The effective driving signal is at a low level.
10. The circuit for suppressing surge current of a high-power load according to claim 2, characterized in that: It also includes the load R L , The load R L The power supply terminal is connected to the power supply output terminal Vout, and the enable terminal EN is connected to the second output terminal of the main control circuit. When the power input terminal Vin is powered on, the second output terminal of the main control circuit outputs an invalid enable signal, so that the load R L Not working; After the power input terminal Vin is powered on, if the main control circuit detects that the system power supply is stable based on the sampled voltage, its second output terminal outputs a valid enable signal, so that the load R L Work.