Circuit capable of suppressing surge voltage and surge current

Abstract

The utility model provides a circuit capable of suppressing surge voltage and surge current, comprising a resistor R100, one end of which is connected with a power supply input end and the other end of which is connected with a power supply output end; one end of the filter capacitor C100 is connected with the power supply output end, and the other end of the filter capacitor C100 is grounded; the switch control circuit comprises an MOS (Metal Oxide Semiconductor) tube Q100, a resistor R101 and a resistor R102; a first voltage sampling circuit; a second voltage sampling circuit; the power supply input end of the voltage conversion circuit is connected with the power supply output end; the power supply input end of the master control circuit is connected with the power supply output end of the voltage conversion circuit, the first input end of the master control circuit is connected with the output end of the first voltage sampling circuit, and the second input end of the master control circuit is connected with the output end of the second voltage sampling circuit; the input end of the driving circuit is connected with the first output end of the main control circuit, and the output end of the driving circuit is connected with the node A. Compared with the prior art, the surge suppression circuit not only can suppress surge current of an input end and surge voltage of an IC end, but also hardly affects the original circuit design.

Description

Technical Field

[0001] The utility model relates to the technical field of circuit design, and particularly relates to a circuit capable of suppressing surge voltage and surge current.

Background Art

[0002] Surge current, surge voltage, and power supply voltage ripple are important parameters of a circuit. In circuit design, they are conflicting parameters. To reduce the power supply voltage ripple to meet the design requirements, a larger filter capacitor is required, and the corresponding surge current may exceed the specification requirements and become ineffective. Or due to too large inductance components on the power supply harness or too large surge voltage caused by the inductance in series in the circuit, there is a risk of breaking down the IC (integrated circuit).

[0003] Please refer to Figure 1 As shown, it is a schematic diagram of a circuit capable of suppressing surge voltage and surge current in the prior art. It uses an inductor L100 to suppress the surge current and a TVS (Transient Voltage Suppressor) D100 to suppress the surge voltage at the input end.

[0004] Figure 1 Problems and disadvantages of the existing technical solution shown:

[0005] ①. The inductor L100 is affected by the working current of the product. The larger the load RL, the greater the current-carrying capacity required for the inductor L100. The cost increases with the increase of the current.

[0006] ②. The greater the power consumption of the load RL, the larger the filter capacitor C100. To suppress a larger surge current, the inductor L100 needs a larger inductance value. The cost increases with the increase of the filter capacitor C100.

[0007] ③. Due to the inductor L100 with large current and large inductance value, its volume is too large and requires a relatively large structural space. This limits the structural design.

[0008] ④. The TVS tube D100 can only clamp the voltage at the input end and cannot directly protect the surge voltage at the IC end.

[0009] Therefore, it is necessary to propose a new technical solution to solve the above problems.

Content of the Utility Model

[0010] One of the purposes of the utility model is to provide a circuit capable of suppressing surge voltage and surge current, which can not only suppress the surge current at the input end and the surge voltage at the IC end, but also hardly affect the original circuit design.

[0011] According to one aspect of the present utility model, the present utility model provides a circuit capable of suppressing surge voltage and surge current, which includes: a resistor R100, one end of which is connected to the power input terminal Vin, and the other end of which is connected to the power output terminal Vout; a filter capacitor C100, one end of which is connected to the power output terminal Vout, and the other end of which is grounded; a switch control circuit, which includes an MOS transistor Q100, a resistor R101, and a resistor R102. The first connection end of the MOS transistor Q100 is connected to the power input terminal Vin, and the second connection end of it is connected to the power output terminal Vout; one end of the resistor R101 is connected to the power input terminal Vin, and the other end of it is connected to the control end of the MOS transistor Q100; one end of the resistor R102 is connected to the control end of the MOS transistor Q100, and the other end of it is connected to node A; a first voltage sampling circuit, whose input terminal is connected to the power input terminal Vin, and whose output terminal outputs a first sampling voltage ADC_Vin, and the first sampling voltage ADC_Vin is generated by the first voltage sampling circuit based on the voltage of the power input terminal Vin; a second voltage sampling circuit, whose input terminal is connected to the power output terminal Vout, and whose output terminal outputs a second sampling voltage ADC_Vout, and the second sampling voltage ADC_Vout is generated by the second voltage sampling circuit based on the voltage of the power output terminal Vout; a voltage conversion circuit, whose power supply input terminal VCC is connected to the power output terminal Vout, and which outputs a conversion voltage through its power supply output terminal Vout1 during operation; a main control circuit, whose power supply input terminal VCC is connected to the power supply output terminal Vout1 of the voltage conversion circuit, its first input terminal is connected to the output terminal of the first voltage sampling circuit, and its second input terminal is connected to the output terminal of the second voltage sampling circuit; a driving circuit, whose input terminal D is connected to the first output terminal of the main control circuit, and whose output terminal is connected to node A.

[0012] Compared with the prior art, the present utility model can suppress the surge current at the input end of the circuit and the surge voltage at the IC end instantaneously when power is turned on. After the IC is awakened and the MCU starts to work normally, it can switch back to the original circuit design state, so that the original circuit design is hardly affected. In addition, it can also monitor whether the working current of the load exceeds the upper limit value, and correspondingly set to turn on the series resistor at the power supply end to limit the surge current.

Description of the Drawings

[0013] In order to more clearly illustrate the technical solutions of the embodiments of the present utility model, the drawings required for the description of the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts. Among them:

[0014] Figure 1 It is a schematic diagram of a circuit in the prior art that can suppress surge voltage and surge current;

[0015] Figure 2 It is a schematic diagram of a circuit in an embodiment of the present invention that can suppress surge voltage and surge current.

Specific Embodiments

[0016] To make the above objects, features, and advantages of the present invention more obvious and understandable, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0017] As used herein, the term "one embodiment" or "embodiment" refers to a specific feature, structure, or characteristic that may be included in at least one implementation of the present invention. The phrase "in one embodiment" appearing in different places in this specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment that excludes other embodiments. Unless otherwise specified, the terms "coupled", "connected", "linked", and "joined" indicating electrical connection herein all mean directly or indirectly connected. For example, when A is connected to B, it includes both A and B being directly electrically connected, and also A being connected to B through electrical components or circuits.

[0018] In the description of the present invention, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "front", "rear", "front", "back", "left", "right", "vertical", "perpendicular", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present invention.

[0019] Please refer to Figure 2 as shown, which is a schematic diagram of a circuit in an embodiment of the present invention that can suppress surge voltage and surge current. Figure 2 The circuit shown that can suppress surge voltage and surge current includes a resistor R100, a filter capacitor C100, a switch control circuit 210, a first voltage sampling circuit 220, a second voltage sampling circuit 230, a voltage conversion circuit U1, a main control circuit U2, and a drive circuit 240. In Figure 2 the specific embodiment shown, the main control circuit U2 is an MCU (Microcontroller Unit, i.e., micro control unit); the voltage conversion circuit U1 is an IC (integrated circuit).

[0020] One end of a resistor R100 is connected to a power input terminal Vin, and the other end thereof is connected to a power output terminal Vout; one end of a filter capacitor C100 is connected to the power output terminal Vout, and the other end thereof is grounded; a switch control circuit 210 includes a MOS transistor (metal oxide semiconductor, hereinafter referred to as a field effect transistor) Q100, a resistor R101, and a resistor R102. A first connection end of the MOS transistor Q100 is connected to the power input terminal Vin, and a second connection end thereof is connected to the power output terminal Vout; one end of the resistor R101 is connected to the power input terminal Vin, and the other end thereof is connected to a control end of the MOS transistor Q100; one end of the resistor R102 is connected to the control end of the MOS transistor Q100, and the other end thereof is connected to a node A; an input end of a first voltage sampling circuit 220 is connected to the power input terminal Vin, and an output end thereof outputs a first sampling voltage ADC_Vin. The first sampling voltage ADC_Vin is generated by the first voltage sampling circuit 220 based on a voltage of the power input terminal Vin; an input end of a second voltage sampling circuit 230 is connected to the power output terminal Vout, and an output end thereof outputs a second sampling voltage ADC_Vout. The second sampling voltage ADC_Vout is generated by the second voltage sampling circuit 230 based on a voltage of the power output terminal Vout; a power supply input terminal VCC of a voltage conversion circuit U1 is connected to the power output terminal Vout, and a converted voltage is output through a power supply output terminal Vout1 thereof during operation. The converted voltage is generated by the voltage conversion circuit U1 through voltage conversion based on the voltage of the power output terminal Vout; a power supply input terminal VCC of a main control circuit U2 is connected to the power supply output terminal Vout1 of the voltage conversion circuit U1. A first input end ADC1 thereof is connected to an output end of the first voltage sampling circuit 220, and a second input end ADC2 thereof is connected to an output end of the second voltage sampling circuit 230; an input end D of a driving circuit 240 is connected to a first output end I / O1 of the main control circuit U2, and an output end thereof is connected to the node A.

[0021] At the instant when the system is powered on (or at the instant when the power input terminal Vin is powered on), the voltage conversion circuit U1 is in a sleep state, the main control circuit U2 does not work, the first output terminal I / O1 of the main control circuit U2 outputs an invalid drive signal, and the drive circuit 240 controls the MOS transistor Q100 to turn off (or cut off) based on this invalid drive signal; after the system is powered on (or after the power input terminal Vin is powered on), the voltage conversion circuit U1 is awakened, the voltage conversion circuit U1 supplies power to the main control circuit U2 through its power supply output terminal Vout1, the main control circuit U2 works, and if the main control circuit U2 detects that the voltage / current of the power input terminal Vin is stable based on the first sampled voltage ADC_Vin and the second sampled voltage ADC_Vout, then the first output terminal I / O1 of the main control circuit U2 outputs a valid drive signal, and the drive circuit 240 controls the MOS transistor Q100 to conduct based on this valid drive signal. In this way, at the instant when the power supply (or the power input terminal Vin) is powered on, the MOS transistor Q100 is controlled to turn off, and by connecting the resistor R100 in series between the power input terminal Vin and the power output terminal Vout, the inrush current is reduced, and the inrush voltage of the power supply input terminal VCC of the voltage conversion circuit U1 is suppressed through the voltage division effect; after the voltage / current of the power input terminal Vin is stable, the MOS transistor Q100 is controlled to conduct, short-circuiting the series resistor R100 and restoring the original circuit design state, so as to achieve the suppression of the inrush current of the power input terminal Vin and the inrush voltage of the power supply input terminal VCC of the voltage conversion circuit U1, with almost no impact on the original circuit design.

[0022] The drive circuit 240 includes a resistor R103, a resistor R104, and a triode Q101. Among them, one end of the resistor R103 is connected to the input terminal D (or node D) of the drive circuit 240, and the other end is connected to the node E; one end of the resistor R104 is connected to the node E, and the other end is grounded; the first connection end of the triode Q101 is connected to the node A, the second connection end is grounded, and the control end is connected to the node E.

[0023] The first voltage sampling circuit 220 includes a resistor R105 and a resistor R106. One end of the resistor R105 is connected to the power input terminal Vin, and the other end is connected to the node B; one end of the resistor R106 is connected to the contact point B, and the other end is grounded; the node B is the output terminal of the first voltage sampling circuit 220, and the voltage of the node B is the first sampled voltage ADC_Vin.

[0024] The second voltage sampling circuit 230 includes a resistor R107 and a resistor R108. One end of the resistor R107 is connected to the power output terminal Vout, and the other end is connected to the node C; one end of the resistor R108 is connected to the contact point C, and the other end is grounded; the node C is the output terminal of the second voltage sampling circuit 230, and the voltage of the node C is the second sampled voltage ADC_Vout.

[0025] In Figure 2 In the specific embodiment shown, the drive circuit 240 further includes a capacitor C101. One end of the capacitor C101 is connected to the node E, and the other end is grounded. The switch control circuit 210 further includes a capacitor C102. One end of the capacitor C102 is connected to the power input terminal Vin, and the other end is connected to the control terminal of the MOS transistor Q100. The capacitors C101 and C102 are non-essential components. The function of the capacitor C101 is to make the switching of the triode Q101 from the cut-off (or off) state to the saturation (or on) state smoother. The function of the capacitor C102 is to make the switching of the field effect transistor Q100 from the cut-off (or off) state to the saturation (or on) state smoother.

[0026] In Figure 2 In the specific embodiment shown, the MOS transistor Q100 is a PMOS transistor. The first connection terminal, the second connection terminal, and the control terminal of the MOS transistor Q100 are respectively the source, the drain, and the gate of the PMOS transistor;

[0027] The triode Q101 is an NPN type triode. The first connection terminal, the second connection terminal, and the control terminal of the triode Q101 are respectively the collector, the emitter, and the base of the NPN type triode.

[0028] Figure 2 The circuit capable of suppressing surge voltage and surge current shown further includes a load RL. The power supply terminal of the load RL is connected to the power output terminal Vout, and its enable terminal EN is connected to the second output terminal I / O2 of the main control circuit U2. At the instant of system power-on (or at the instant of power-on at the power input terminal Vin), the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled, so that the load RL does not work. After the instant of system power-on, if the second output terminal I / O2 of the main control circuit U2 outputs a valid enable signal Enable, then the load RL works.

[0029] In Figure 2 In the circuit capable of suppressing surge voltage and surge current shown, the voltage conversion circuit U1 includes signal ports (for example, the CAN_H interface and the CAN_L interface), which are used to receive wake-up signals. When no wake-up signal is received, the voltage conversion circuit U1 is in a sleep state. When a wake-up signal is received, the voltage conversion circuit U1 is awakened.

[0030] In Figure 2 In the specific embodiment shown, the signal ports of the voltage conversion circuit U1 include the CAN_H interface and the CAN_L interface, which are respectively connected to the CAN_H interface and the CAN_L interface in the connector J1 through the CAN_H line and the CAN_L line. In addition, the VCC interface in the connector J1 is connected to the power input terminal Vin, and the GND interface in the connector J1 is grounded.

[0031] In the field of electrical control, CAN is the abbreviation of Controller Area Network. It is a bus technology used to transmit data and information in automotive control systems. The "L" and "H" are used to distinguish two different CAN lines, where "L" represents low level and "H" represents high level. These two lines play an important role in automotive control systems. For the specific usage, reference can be made to the prior art and will not be elaborated here.

[0032] In Figure 2 In the circuit capable of suppressing surge voltage and surge current shown, the voltage conversion circuit U1 is provided with communication ports (for example, Rx interface and Tx interface), the main control circuit U2 is provided with communication ports (for example, Rx interface and Tx interface), and the communication ports of the voltage conversion circuit U1 are communicatively connected to the communication ports of the main control circuit U2. When the voltage conversion circuit U1 does not send a drive instruction to the main control circuit U2 through the communication ports (for example, Rx interface and Tx interface), the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled, causing the load RL not to work; when the voltage conversion circuit U1 sends a drive instruction to the main control circuit U2 through the communication ports (for example, Rx interface and Tx interface), the second output terminal I / O2 of the main control circuit U2 outputs a valid enable signal Enable, causing the load RL to work.

[0033] In Figure 2 In the specific embodiment shown, the communication ports of the voltage conversion circuit U1 include an Rx (receive) interface and a Tx (transport, i.e., transmit) interface, and the communication ports of the main control circuit U2 include an Rx (receive) interface and a Tx (transport, i.e., transmit) interface. Among them, the Rx interface of the voltage conversion circuit U1 is connected to the Tx interface of the main control circuit U2, and the Tx interface of the voltage conversion circuit U1 is connected to the Rx interface of the main control circuit U2. For the specific usage of Tx and Rx communication, reference can be made to the prior art and will not be elaborated here.

[0034] The following specifically introduces Figure 2 the working process of the circuit capable of suppressing surge voltage and surge current shown.

[0035] 1. At the instant of system power-on (or at the instant of power-on at the power input terminal Vin):

[0036] The enable terminal EN of the load RL is designed to default to the Disabled state (i.e., the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled), causing the load RL not to work. The voltage conversion circuit U1 is an IC (i.e., integrated circuit) with a sleep function. Before it receives a wake-up signal through CAN_H and CAN_L or before the IC is initialized, the power supply output terminal Vout1 of the voltage conversion circuit U1 does not output voltage (about 0V). Therefore, the output of the first output terminal I / O1 of the main control circuit U2 is 0V (i.e., the invalid drive signal is at a low level). The Vbe of the triode Q101 (Vbe refers to the voltage difference between the base and emitter of the triode) is about 0V, which is less than the Vbe conduction voltage drop (for example, the conduction voltage drop is 0.7V). The triode Q101 is in the cut-off (or off) state, and Ic_Q101 (Ic is the collector current of the triode) is approximately equal to 0A. The current through the resistor R101 and the resistor R102 is 0A, and the operating voltage across the resistor R101 is about 0V, that is, the Vgs voltage of the field effect transistor Q100 (i.e., the gate-source voltage of the field effect transistor) is about 0V. Currently, Vgs is less than the Vgs(th) of the field effect transistor (i.e., the turn-on voltage), and the field effect transistor Q100 is in the cut-off (or off) state.

[0037] The circuit load resistance at the moment of power-on is approximately R100 + ESR_C100, and the transient inrush current is:

[0038] I_inrush≈Vin÷(R100+ESR_C100)

[0039] ESR is Equivalent Series Resistance, that is, equivalent series resistance.

[0040] At the same time, due to the existence of the capacitor C100, the operating voltage of the IC (i.e., the voltage conversion circuit U1) at the moment of power-on is approximately:

[0041] Vout≈Vin*(ESR_C100 / (ESR_C100+R100))

[0042] Therefore, the larger the resistance R100, the smaller the corresponding inrush current.

[0043] Due to the existence of the capacitor C100, the operating voltage of the U1 IC at the moment of power-on (i.e., the operating voltage of the power supply input terminal VCC of the voltage conversion circuit U1) is approximately:

[0044] Vout≈Vin*(ESR_C100 / (ESR_C100+R100)), and the larger the R100, the smaller the inrush voltage at the U1 IC end.

[0045] That is, the surge voltage at the IC end (i.e., the power supply input terminal VCC of the voltage conversion circuit U1) is not directly supplied by the power supply input terminal Vin, so it is also affected by the series voltage division of ESR_C100 and R100. The larger the resistance R100, the smaller the surge voltage at the IC end. Among them, since the voltage conversion circuit U1 is in a sleep state at the instant of system power-on (or at the instant of power-on at the power supply input terminal Vin), the voltage conversion circuit U1 does not send a driving instruction to the main control circuit U2 through communication connection. Therefore, the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled (or the enable terminal EN is designed to default to the Disabled state at this time). Therefore, the load RL does not work.

[0046] That is to say, at the instant of system power-on (or at the instant of power-on at the power supply input terminal Vin), the voltage conversion circuit U1 is in a sleep state, the main control circuit U2 does not work, and the first output terminal I / O1 of the main control circuit U2 outputs an invalid driving signal. This invalid driving signal turns off the triode Q101 in the driving circuit 240, thereby controlling the voltage at the node A to turn off the MOS transistor Q100.

[0047] 2. After the instant of system power-on (or after the instant of power-on at the power supply input terminal Vin):

[0048] After the initialization of the voltage conversion circuit U1 is completed and a wake-up signal is received through CAN_H and CAN_L, the power supply output terminal Vout1 of the voltage conversion circuit U1 will output a supply voltage. After the main control circuit U2 is powered by the power supply output terminal Vout1 of the voltage conversion circuit U1, it starts to work. The main control circuit U2 detects whether the supply voltage / current of the power supply input terminal Vin is stable through the first sampling voltage ADC_Vin and the second sampling voltage ADC_Vout. If the main control circuit U2 detects that the supply voltage / current of the power supply input terminal Vin is stable based on the first sampling voltage ADC_Vin and the second sampling voltage ADC_Vout (for example, the first sampling voltage ADC_Vin and the second sampling voltage ADC_Vout are basically equal), then the first output terminal I / O1 of the main control circuit U2 outputs a high level (which is a valid drive signal). Through resistors R103 and R104, the Vbe of the triode Q101 is about 0.7V, and the triode Q101 is in a saturated (or conducting) state. Vce_Q101 (Vce is the voltage difference between the collector and emitter of the triode) will be less than 0.3V, that is, the Vgs voltage of the field effect transistor Q100 ≈ -(Vin - 0.3V) * (R101 / (R101 + R102)). It is designed that the Vgs at this time is greater than the Vgs(th) (i.e., the turn-on voltage) of the field effect transistor, and the field effect transistor Q100 is in a saturated (or conducting) state, short-circuiting the power supply input terminal Vin in series with the resistor R100 and restoring the original circuit design state. The series resistor R100 is about the DC on-resistance of the field effect transistor Q100, which is about 10mΩ and hardly affects the original circuit design.

[0049] That is to say, after the power supply input terminal Vin is powered on instantaneously, the voltage conversion circuit U1 is awakened and the main control circuit U2 works. If the main control circuit U2 detects that the supply voltage / current of the power supply input terminal Vin is stable based on the first sampling voltage ADC_Vin and the second sampling voltage ADC_Vout, the first output terminal I / O1 of the main control circuit U2 outputs a valid drive signal, and this valid drive signal makes the triode Q101 in the drive circuit 240 conduct, thereby controlling the voltage at node A to make the MOS transistor Q100 conduct.

[0050] 3. After detecting that the supply voltage / current of the power supply input terminal Vin is stable, the enable terminal EN of the load RL is allowed to switch from the Disabled state to the Enable state.

[0051] Specifically, after detecting that the supply voltage / current at the power input terminal Vin is stable, when the voltage conversion circuit U1 does not send a driving instruction to the main control circuit U2 through the communication port (for example, the Rx interface and the Tx interface), the second output terminal I / O2 of the main control circuit U2 outputs an invalid enable signal Disabled, causing the load RL not to work; when the voltage conversion circuit U1 sends a driving instruction to the main control circuit U2 through the communication port (for example, the Rx interface and the Tx interface), the second output terminal I / O2 of the main control circuit U2 outputs a valid enable signal Enable, causing the load RL to work.

[0052] 4. When there is a surge current during the instantaneous operation or the process of the load RL, the difference between the first sampled voltage ADC_Vin and the second sampled voltage ADC_Vout is captured to determine whether the working current of the load RL exceeds the upper limit current. If the working current of the load RL exceeds the upper limit current, I / O1 can be set to a low level, causing the field effect transistor Q100 to be in a cut-off (or off) state, and the resistor R100 is connected in series to the circuit to suppress the surge current. After the circuit is stable, I / O1 is switched back to a high level, causing the field effect transistor Q100 to be in a saturation (or on) state, and the circuit returns to its original state. The impact of the surge current brought by the load RL is effectively suppressed.

[0053] That is to say, when there is a surge current during the instantaneous operation of the load RL or during the working process of the load RL, if the main control circuit U2 detects that the working current of the load RL exceeds the upper limit current based on the first sampled voltage ADC_Vin and the second sampled voltage ADC_Vout, the first output terminal I / O1 of the main control circuit U2 outputs an invalid driving signal (for example, a low level), and the driving circuit 240 controls the MOS transistor Q100 to turn off based on this invalid driving signal; if the main control circuit U2 detects that the working current of the load RL does not exceed the upper limit current based on the first sampled voltage ADC_Vin and the second sampled voltage ADC_Vout, the first output terminal I / O1 of the main control circuit U2 outputs a valid driving signal (for example, a high level), and the driving circuit 240 controls the MOS transistor Q100 to turn on based on this valid driving signal.

[0054] It should be noted specifically that:

[0055] 1. The resistor R100 can be a parallel connection of multiple resistors;

[0056] 2. The field effect transistor Q100 can be of other driving methods or other types of MOS transistors. The core is that it can short-circuit the resistor R100, and at the same time, it can also utilize the on-state DC resistance of the field effect transistor Q100. By sampling the voltage difference across both ends of the field effect transistor Q100 in the saturation state through the first voltage sampling circuit 220 and the second voltage sampling circuit 230, and dividing it by the on-state DC resistance R100, it is possible to infer whether the working current of the load RL exceeds the upper limit value.

[0057] 3. The main control circuit U2 can be any other IC with a sleep function. The power supply output terminal Vout1 is the power supply after corresponding sleep wake-up. This sleep wake-up signal can be other level signals.

[0058] 4. Before the load RL starts, the working current of the IC (i.e., the main control circuit U2) is only about several tens of mA, and the voltage drop caused by the power resistor R100 does not affect the normal operation of the IC.

[0059] In summary, for the circuit capable of suppressing surge voltage and surge current provided by the present utility model, a resistor R100 is connected in series between the power supply input terminal Vin and the power supply output terminal Vout, and a MOS transistor Q100 is connected in parallel to the resistor R100. In this way, at the instant when the power supply (or the power supply input terminal Vin) is powered on, the MOS transistor Q100 is controlled to turn off. By connecting the resistor R100 in series between the power supply input terminal Vin and the power supply output terminal Vout, the surge current is reduced, and the surge voltage at the power supply input terminal VCC of the voltage conversion circuit U1 is suppressed through the action of resistor voltage division. The IC (i.e., the voltage conversion circuit U1) with a sleep wake-up function will output a power supply output voltage Vout1 after being woken up. After the MCU (i.e., the main control circuit U2) starts to work, by comparing the voltage difference across both ends of the series resistor R100 at the power supply input terminal Vin between the first sampled voltage ADC_Vin and the second sampled voltage ADC_Vout, it is determined that the voltage / current at the power supply input terminal Vin has stabilized, then the field effect transistor Q100 is driven to turn on, short-circuiting the series resistor R100 at the power supply end, and restoring the original circuit design state. Thus, it realizes the suppression of the surge current at the power supply input terminal Vin and the surge voltage at the IC end, and can also short-circuit the series resistor at the power supply end following the sleep wake-up of the IC, restoring to the original circuit design, with almost no impact on the original circuit design. In addition, the present utility model can also monitor whether the working current of the load RL exceeds the upper limit value, and correspondingly set to turn on the series resistor R100 at the power supply end to limit the surge current.

[0060] It should be noted that any modifications made by those skilled in the art to the specific embodiments of the present utility model do not depart from the scope of the claims of the present utility model. Correspondingly, the scope of the claims of the present utility model is not limited solely to the foregoing specific embodiments.

Claims

1. A circuit capable of suppressing surge voltage and surge current, characterized in that: It includes: A resistor R100, one end of which is connected to the power input terminal Vin, and the other end of which is connected to the power output terminal Vout; A filter capacitor C100, one end of which is connected to the power output terminal Vout, and the other end of which is grounded; A switch control circuit, comprising a MOS tube Q100, a resistor R101 and a resistor R102, wherein a first connection end of the MOS tube Q100 is connected to the power input end Vin, and a second connection end thereof is connected to the power output end Vout; one end of the resistor R101 is connected to the power input end Vin, and the other end thereof is connected to the control end of the MOS tube Q100; one end of the resistor R102 is connected to the control end of the MOS tube Q100, and the other end thereof is connected to a node A; A first voltage sampling circuit, whose input end is connected to the power input end Vin, and whose output end outputs a first sampling voltage ADC_Vin, wherein the first sampling voltage ADC_Vin is generated by the first voltage sampling circuit based on the voltage of the power input end Vin; A second voltage sampling circuit, whose input terminal is connected to the power output terminal Vout, and whose output terminal outputs a second sampling voltage ADC_Vout, wherein the second sampling voltage ADC_Vout is generated by the second voltage sampling circuit based on the voltage of the power output terminal Vout; A voltage conversion circuit, whose power supply input terminal VCC is connected to the power supply output terminal Vout, and which outputs a conversion voltage through its power supply output terminal Vout1 when in operation; A main control circuit, whose power supply input terminal VCC is connected to the power supply output terminal Vout1 of the voltage conversion circuit, whose first input terminal is connected to the output terminal of the first voltage sampling circuit, and whose second input terminal is connected to the output terminal of the second voltage sampling circuit; The driving circuit has an input terminal D connected to the first output terminal of the main control circuit, and an output terminal connected to the node A.

2. The circuit capable of suppressing surge voltage and surge current according to claim 1, characterized in that: When the power input terminal Vin is powered on, the voltage conversion circuit is in a dormant state, the main control circuit does not work, the first output terminal of the main control circuit outputs an invalid drive signal, and the drive circuit controls the MOS tube Q100 to be turned off based on the invalid drive signal; After the power input terminal Vin is powered on, the voltage conversion circuit is awakened, and the voltage conversion circuit supplies power to the main control circuit through its power output terminal Vout1. The main control circuit works. If the main control circuit detects that the voltage / current of the power input terminal Vin has stabilized based on the first sampling voltage and the second sampling voltage, the first output terminal of the main control circuit outputs a valid driving signal, and the driving circuit controls the MOS tube Q100 to be turned on based on the valid driving signal.

3. The circuit capable of suppressing surge voltage and surge current according to claim 2, characterized in that: The driving circuit includes a resistor R103, a resistor R104 and a transistor Q101. One end of the resistor R103 is connected to the input terminal D of the driving circuit, and the other end thereof is connected to the node E; One end of the resistor R104 is connected to the node E, and the other end thereof is grounded; The first connection end of the transistor Q101 is connected to the node A, the second connection end thereof is grounded, and the control end thereof is connected to the node E.

4. The circuit capable of suppressing surge voltage and surge current according to claim 3, characterized in that: The first voltage sampling circuit includes a resistor R105 and a resistor R106, one end of the resistor R105 is connected to the power input terminal Vin, and the other end thereof is connected to a node B; one end of the resistor R106 is connected to the node B, and the other end thereof is grounded; the node B is the output end of the first voltage sampling circuit, and the voltage of the node B is the first sampling voltage; The second voltage sampling circuit includes a resistor R107 and a resistor R108, one end of the resistor R107 is connected to the power output terminal Vout, and the other end thereof is connected to a node C; one end of the resistor R108 is connected to the node C, and the other end thereof is grounded; the node C is the output end of the second voltage sampling circuit, and the voltage of the node C is the second sampling voltage.

5. The circuit capable of suppressing surge voltage and surge current according to claim 4, characterized in that: The driving circuit further includes a capacitor C101, one end of the capacitor C101 is connected to the node E, and the other end thereof is grounded; The switch control circuit further includes a capacitor C102 , one end of which is connected to the power input terminal Vin, and the other end of which is connected to the control terminal of the MOS transistor Q100 .

6. The circuit capable of suppressing surge voltage and surge current according to claim 3, characterized in that: The invalid driving signal turns off the transistor Q101 in the driving circuit, thereby controlling the voltage of the node A to turn off the MOS transistor Q100; The effective driving signal turns on the transistor Q101 in the driving circuit, thereby controlling the voltage of the node A to turn on the MOS transistor Q100.

7. The circuit capable of suppressing surge voltage and surge current according to claim 6, characterized in that: The MOS transistor Q100 is a PMOS transistor, and the first connection terminal, the second connection terminal and the control terminal of the MOS transistor Q100 are the source, the drain and the gate of the PMOS transistor respectively; The transistor Q101 is an NPN transistor, and the first connection end, the second connection end and the control end of the transistor Q101 are respectively the collector, the emitter and the base of the NPN transistor.

8. The circuit capable of suppressing surge voltage and surge current according to claim 2, characterized in that: It also includes the load RL, The power supply terminal of the load RL is connected to the power supply output terminal Vout, and the enable terminal EN is connected to the second output terminal of the main control circuit. When the power input terminal Vin is powered on, the second output terminal of the main control circuit outputs an invalid enable signal, so that the load RL does not work; After the power input terminal Vin is powered on, if the second output terminal I / O2 of the main control circuit outputs a valid enable signal, the load RL is enabled to operate.

9. The circuit capable of suppressing surge voltage and surge current according to claim 8, characterized in that: The voltage conversion circuit also includes a signal port for receiving a wake-up signal. When the wake-up signal is not received, the voltage conversion circuit is in a dormant state; When the wake-up signal is received, the voltage conversion circuit is awakened.

10. The circuit capable of suppressing surge voltage and surge current according to claim 9, characterized in that: The voltage conversion circuit is connected to the main control circuit for communication, and when the voltage conversion circuit does not send a driving instruction to the main control circuit through the communication connection, the second output terminal of the main control circuit outputs an invalid enable signal, so that the load RL does not work; When the voltage conversion circuit sends a driving instruction to the main control circuit through the communication connection, the second output terminal of the main control circuit outputs a valid enable signal to enable the load RL to operate.

11. The circuit capable of suppressing surge voltage and surge current according to any one of claims 8 to 10, characterized in that: When the load RL is running instantaneously or there is a surge current during the operation of the load RL, if the main control circuit detects that the operating current of the load RL exceeds the upper limit current based on the first sampling voltage ADC_Vin and the second sampling voltage ADC_Vout, the first output end of the main control circuit outputs an invalid drive signal, and the drive circuit controls the MOS tube Q100 to be turned off based on the invalid drive signal; if the main control circuit detects that the operating current of the load RL does not exceed the upper limit current based on the first sampling voltage ADC_Vin and the second sampling voltage ADC_Vout, the first output end of the main control circuit outputs a valid drive signal, and the drive circuit controls the MOS tube Q100 to be turned on based on the valid drive signal.

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