Switching tube switching circuit for battery active equalization and battery management system

Abstract

The utility model discloses a switch tube switching circuit for active equalization of a battery and a battery management system. The switch tube switching circuit comprises an interface expander, a state controller, a multiplexer and a switch tube array circuit, the switch tube array circuit is arranged between the balanced power supply and the plurality of battery bodies; the multiplexer is electrically connected with the switching tube array circuit, and the multiplexer is used for controlling the state of the switching tube array circuit, so that only a voltage path between one battery body and the balanced power supply is conducted at the same time; the interface expander is electrically connected with the multiplexer through the state controller; and the state controller is used for controlling the working state of each output channel of the multiplexer at the same moment. According to the switching tube switching circuit, efficient control over the switching tube array circuit and single control over any battery body are achieved, so that the reliability and safety performance of the battery equalization system are effectively improved, and equalization signals with large current and high voltage level can be borne.

Description

Technical Field

[0001] The utility model relates to the technical field of battery equalization, in particular to a switching tube switching circuit for active battery equalization and a battery management system. Background Art

[0002] In modern battery management systems, the equalization management of battery packs is a crucial link. Due to differences in manufacturing processes and usage environments, there are often inconsistencies in the capacity, voltage, etc. of individual cells in a battery pack. This inconsistency will lead to a decline in the overall performance of the battery pack, shorten the battery life, and may even cause safety problems. Therefore, performing equalization management on the battery pack to ensure that the voltage and capacity between individual battery cells are as consistent as possible is one of the core tasks of the battery management system.

[0003] At present, battery equalization technologies are mainly divided into passive equalization and active equalization. Passive equalization reduces the voltage of battery cells with higher voltages by consuming excess energy. This method has low energy utilization efficiency and low efficiency. Active equalization, on the other hand, transfers energy from battery cells with higher voltages to battery cells with lower voltages through the transfer of electrical energy, thereby achieving voltage equalization between battery cells. It has the advantages of high energy utilization efficiency and high efficiency. Therefore, active equalization technology has gradually become a research and application hotspot.

[0004] Although active equalization technology has many advantages, an active equalization system requires a complex control circuit. Secondly, due to the large number of battery cells, how to effectively control the equalization process of each individual battery cell and avoid an increase in circuit complexity and cost caused by multiple batteries participating in equalization simultaneously is also an important technical challenge.

[0005] Currently, limited by the small current-carrying capacity of traditional solid-state relays, MOS transistors are generally used as power switching tubes for large-current active equalization. The drive control of MOS transistors generally has the following two categories. One is a drive method mainly based on an integrated charge pump inside an integrated chip, and the other is an isolated drive method mainly based on optoelectronic devices.

[0006] For the first type of control method, the circuit is relatively simple, but the common-mode rejection ability is poor. In addition, the withstand voltage level of the integrated chip is generally low. For the second type of control method, a relatively high withstand voltage level can be achieved. However, the switches on each battery are individually controlled using the I / O ports of the MCU. When the number of battery strings is large, a large number of I / O resources are required. In addition, due to the individual control by the MCU, if the MCU runs away or the control logic is abnormal, resulting in multiple I / O pins enabling output simultaneously, it will cause a battery short circuit and damage circuit components. Summary of the Utility Model

[0007] The object of the present utility model is to provide a switching transistor switching circuit and a battery management system for battery active equalization, which have a high withstand voltage level and can precisely control each battery cell separately.

[0008] To achieve the above object, the present utility model provides a switching transistor switching circuit for battery active equalization, which includes an interface expander, a state controller, a multiplexer, and a switching transistor array circuit;

[0009] The switching transistor array circuit is disposed between the equalization power supply and a plurality of battery bodies, and the switching transistor array circuit is used to control the on / off of the power supply path between each battery body and the equalization power supply;

[0010] The multiplexer is electrically connected to the switching transistor array circuit, and the multiplexer is used to control the state of the switching transistor array circuit, so that only one voltage path between a battery body and the equalization power supply is conducted at the same time;

[0011] The interface expander is electrically connected to the multiplexer through the state controller, and the interface expander is used to control the output state of the multiplexer through the state controller and based on the control instruction of the controller;

[0012] The state controller is used to control the working state of each output channel of the multiplexer at the same time.

[0013] Preferably, the multiplexer includes at least two decoders, and each decoder is electrically connected to a part of the switching transistors in the switching transistor array circuit.

[0014] Preferably, the state controller includes an inverter, the input end of the inverter is electrically connected to the interface expander, and the output end of the inverter is electrically connected to the enable end of one or more of the decoders.

[0015] Preferably, the switching transistor array circuit includes a plurality of first switching transistor units, a plurality of second switching transistor units, and a first connection end and a second connection end;

[0016] Both ends of any one of the battery bodies are respectively electrically connected to the multiplexer through the control end of a first switching transistor unit, and both ends of any one of the battery bodies are also respectively electrically connected to the first connection end and the second connection end through the two conducting ends of a first switching transistor unit;

[0017] A unidirectional diode is further disposed between each first switching transistor unit and the multiplexer, and the two unidirectional diodes at both ends of any one of the battery bodies are arranged face to face;

[0018] Both ends of any one of the battery bodies are also electrically connected to the two second switch tube units through the first connection end and the second connection end respectively. Two second switch tube units belonging to both ends of any one of the battery bodies are also electrically connected to the positive and negative terminals of the equalizing power supply respectively.

[0019] Preferably, both the first switch tube unit and the second switch tube unit include two MOS tubes connected in series back to back.

[0020] Preferably, the control end of any one of the first switch tube units is electrically connected to the multiplexer through a first optocoupler. A second optocoupler is also provided at the control end of any one of the second switch tube units. Two second optocouplers corresponding to both ends of the same battery body are connected in series, and the two series-connected second optocouplers are also electrically connected to the first connection end and the second connection end through a third optocoupler.

[0021] The present invention also provides a battery management system, which includes a battery pack, an equalizing power supply, a controller, and a switch tube switching circuit as described above. The battery pack includes several battery bodies, and the controller is electrically connected to the interface expander.

[0022] Preferably, the controller is electrically connected to the interface expander through any one of the interfaces of I2C, SPI, and UART.

[0023] Compared with the prior art, the switch tube switching circuit provided by the above technical solution of the present invention uses the combination of an interface expander, a state controller, and a multiplexer to achieve efficient control of the switch tube array circuit, and further achieves the purpose of individually controlling each battery body. In this way, at any moment, even if an incorrect control signal is output due to the deviation of the master controller, only one battery body will be affected, rather than all battery bodies, thereby effectively improving the reliability and safety performance of the battery equalization system, and moreover, it can carry equalization signals with large current and high voltage levels. Description of the Drawings

[0024] Figure 1 It is a schematic structural diagram of the battery management system in the embodiment of the present invention.

[0025] Figure 2 It is a circuit connection diagram of two decoders and an interface expander in the embodiment of the present invention.

[0026] Figure 3 It is a circuit connection diagram of three decoders and an interface expander in the embodiment of the present invention.

[0027] Figure 4 It is a battery pack with three battery bodies in the embodiment of the present invention.

[0028] Figure 5 This is a partial circuit schematic diagram of the switch tube array circuit in the embodiment of the present invention.

[0029] Figure 6 This is another partial circuit schematic diagram of the switch tube array circuit in the embodiment of the present invention. Detailed implementation manners

[0030] To describe in detail the technical content, structural features, achieved objectives and effects of the present invention, the following will be described in detail in conjunction with the implementation manners and with reference to the accompanying drawings.

[0031] This embodiment discloses a battery management system for managing the active balancing operation of a battery pack, so that the voltages and currents of the individual battery cells in the battery pack are in a balanced state. It should be noted that the battery cells in this embodiment are rechargeable batteries.

[0032] Such as Figure 1 , the battery management system includes a balancing power supply 15, a controller 10 and a switch tube switching circuit that are matched with the battery pack.

[0033] The switch tube switching circuit includes an interface expander 11, a state controller 12, a multiplexer 13 and a switch tube array circuit 14.

[0034] The switch tube array circuit 14 is arranged between the balancing power supply 15 and a plurality of battery cells BAT, and the switch tube array circuit 14 is used to control the on / off of the power supply path between each battery cell BAT and the balancing power supply 15.

[0035] The multiplexer 13 is electrically connected to the switch tube array circuit 14, and the multiplexer 13 is used to control the state of the switch tube array circuit 14, so that only one voltage path between a battery cell BAT and the balancing power supply 15 is conducted at the same time.

[0036] The interface expander 11 is electrically connected to the multiplexer 13 through the state controller 12, and the interface expander 11 is used to control the output state of the multiplexer 13 through the state controller 12 and based on the control instruction of the controller 10.

[0037] The state controller 12 is used to control the working states of the output channels of the multiplexer 13 at the same time.

[0038] In this embodiment, the combination of the interface expander 11, the state controller 12, and the multiplexer 13 is used to achieve efficient control of the switch transistor array circuit 14, thereby achieving the purpose of individually controlling each battery cell BAT. In this way, at any moment, even if the master controller 10 deviates and outputs an incorrect control signal, only one battery cell BAT will be affected, rather than all battery cells BAT, thus effectively improving the reliability and safety performance of the battery equalization system, and it can carry balanced signals with large current and high voltage levels.

[0039] On the other hand, the multiplexer 13 includes at least two decoders, and each decoder is electrically connected to a part of the switch transistors in the switch transistor array circuit 14. The decoder in this embodiment is a 3-8 decoder. In this way, through one decoder, only three channels of the interface expander 11 need to be occupied to control eight switch channels, thereby effectively saving the number of I / O ports of the interface expander 11.

[0040] Since the number of decoders is at least two, in order to facilitate the state controller 12 to control that only one of the two or more decoders is in the output state at any moment, the state controller 12 in this embodiment includes an inverter. The input end of the inverter is electrically connected to the interface expander 11, and the output end of the inverter is electrically connected to the enable end of one or more of the decoders.

[0041] For example Figure 2 , taking two decoders U1 and U2 as an example, an inverter F1 is configured. The input end of this inverter F1 and the enable end of one of the decoders U1 are electrically connected to the I / O port I01 of the interface expander 11 together, and the output end of the inverter F1 is electrically connected to the enable end of the other decoder U2. When the I / O port I01 of the interface expander 11 outputs a high level, the decoder U1 is activated and outputs an 8-bit control instruction according to the outputs of the I / O ports I05, I06, and I07 of the interface expander 11, and only one of these 8-bit control instructions is a high level. On the contrary, at another moment, when the I / O port I01 of the interface expander 11 outputs a low level, the decoder U2 is activated and outputs an 8-bit control instruction according to the outputs of the I / O ports I02, I03, and I04 of the interface expander 11, and only one of these 8-bit control instructions is a high level.

[0042] For example Figure 3, when configuring three decoders U1, U2, and U3, two inverters F1 and F2 need to be configured. The input terminal of inverter F1 is electrically connected to the I / O port I06 of interface expander 11, and the input terminal of inverter F2 is electrically connected to the I / O port I07 of interface expander 11. For the three enable terminals of decoder U1: E1 is grounded, E2 is electrically connected to the I / O port I07, and E3 is electrically connected to the output terminal of inverter F1; for the three enable terminals of U2: E1 is grounded, E2 is electrically connected to the output terminal of inverter F2, and E3 is electrically connected to the output terminal of inverter F1; for the three enable terminals of U3: E1 is grounded, E2 is electrically connected to the output terminal of F2, and E3 is electrically connected to the I / O port I06.

[0043] For the above three decoders U1, U2, and U3, when E2 is at low level 0 and E3 is at high level 1, the decoder is activated.

[0044] Thus, when IO7 of interface expander 11 is 0 and IO6 is 0, U1 is activated;

[0045] when IO7 of interface expander 11 is 1 and IO6 is 0, U2 is activated;

[0046] when IO7 of interface expander 11 is 1 and IO6 is 1, U3 is activated;

[0047] when IO7 of interface expander 11 is 0 and IO6 is 1, all three decoders do not work;

[0048] That is, it is ensured that only one decoder works properly at the same time.

[0049] On the other hand, please refer to Figure 1 、 Figures 4 to 6 , the switching transistor array circuit 14 includes a plurality of first switching transistor units P1, a plurality of second switching transistor units P2, a first connection terminal CELL+ and a second connection terminal CELL-.

[0050] Both ends of any battery body BAT are respectively electrically connected to the multiplexer 13 through the control terminal of a first switching transistor unit P1, and both ends of any battery body BAT are also respectively electrically connected to the first connection terminal CELL+ and the second connection terminal CELL- through the two conduction terminals of a first switching transistor unit P1.

[0051] A unidirectional diode is also provided between each first switching transistor unit P1 and the multiplexer 13, and the two unidirectional diodes at both ends of any battery body BAT are arranged in an end-to-end manner.

[0052] Both ends of any battery cell BAT are also electrically connected to two second switch unit P2 through a first connection terminal CELL+ and a second connection terminal CELL- respectively. Two second switch units P2 belonging to both ends of any battery cell BAT are also electrically connected to the positive terminal and the negative terminal of the equalizing power supply 15 respectively.

[0053] For example, for Figure 4 the three battery cells BAT in, the negative terminal B0 of the battery cell BAT1 is electrically connected to the interface Y0 of the decoder U1 through the control terminal of the first switch unit P10 and the one-way diode D1; the positive terminal B1 of the battery cell BAT1 is electrically connected to the interface Y0 of the decoder U1 through the control terminal of the first switch unit P11 and the one-way diode D2, and D1 and D2 are arranged opposite to each other.

[0054] The negative terminal B0 of the battery cell BAT1 is electrically connected to the negative pole BUS- of the equalizing power supply 15 through the second connection terminal CELL-, and the positive terminal B1 of the battery cell BAT1 is electrically connected to the positive pole BUS+ of the equalizing power supply 15 through the first connection terminal CELL+.

[0055] In this embodiment, by using the same pair of first connection terminal CELL+ and second connection terminal CELL-, the first switch unit P1 and the second switch unit P2 at both ends of each battery cell BAT are connected together. The interface expander 11 can control any battery cell BAT to be connected to the equalizing power supply 15 at any time through a small number of I / O ports for energy conversion.

[0056] On the other hand, both the first switch unit P1 and the second switch unit P2 include two MOS transistors connected in series back-to-back. Through the setting of two back-to-back MOS transistors, the voltage backflow between the battery cells BAT can be effectively prevented.

[0057] On the other hand, the control terminal of any first switch unit P1 is electrically connected to the multiplexer 13 through the first optocoupler G1. A second optocoupler G2 is also provided at the control terminal of any second switch unit P2. Two second optocouplers G2 corresponding to both ends of the same battery cell BAT are connected in series, and the two series-connected second optocouplers G2 are also electrically connected to the first connection terminal CELL+ and the second connection terminal CELL- through the third optocoupler G3.

[0058] As Figures 1 to 6 , taking a battery pack with 16 battery cells BAT as an example, the multiplexer 13 includes two 3-8 decoders, and the state controller 12 includes an inverter.

[0059] Figures 4 to 6The specific circuit connection diagram of the switch tube array circuit 14 of the three battery bodies BAT is shown. For the connection of the switch tube array circuit 14 of more battery bodies BAT, it can be extended on this basis and will not be specifically shown here.

[0060] When it is necessary to control one of the battery bodies BAT (such as BAT2) to start active balancing, the following operations are performed:

[0061] (1) The controller 10 controls the interface expander 11, that is, U0's IO1 outputs a high level. At this time, the low 8-section 3-8 decoder U1 is enabled, and the high 8-section 3-8 decoder U2 is prohibited from working;

[0062] (2) The controller 10 controls U0's IO5, IO6, and IO7 to output low levels, low levels, and high levels respectively. At this time, the Y1 pin of the decoder U1 outputs a low level, and the other Y0~Y7 pins maintain high levels;

[0063] (3) Since the Y1 pin of U1 is at a low level and BAL2 is at a low level, the oppositely arranged unidirectional diodes D3 and D4 are both conducting. The first optocoupler G11 at the positive terminal B2 of the battery body BAT2 and the first optocoupler G12 at the negative terminal B1 are conducting. Therefore, the corresponding positive and negative MOS transistors Q3, Q4, Q5, and Q6 of the battery body BAT2 are conducting normally. The negative terminal B1 of the battery body BAT2 is connected to the first connection terminal CELL+, and the positive terminal B2 of the battery body BAT2 is connected to the second connection terminal CELL-;

[0064] (4) Since the potential of the second connection terminal CELL- is higher than that of the first connection terminal CELL+, the third optocoupler G30 is conducting normally, and the third optocoupler G31 is disconnected. At this time, the second optocouplers G20 and G21 are conducting normally, and the MOS transistors Q13, Q14, Q15, and Q16 are conducting normally. Therefore, CELL- is connected to BUS+, and CELL+ is connected to BUS-. That is, the negative terminal B1 of the battery body BAT2 is connected to BUS-, and the positive terminal B2 of the battery body BAT2 is connected to BUS+;

[0065] (5) After the positive and negative poles of the battery body BAT2 are respectively connected to BUS+ and BUS-, energy conversion is carried out between the battery body BAT2 and the active balancing power supply 15.

[0066] On the other hand, the controller 10 is electrically connected to the interface expander 11 through any one of the I2C, SPI, and UART interfaces.

[0067] The above-disclosed are only the preferred embodiments of the present invention. Of course, the scope of the rights of the present invention cannot be limited by this. Therefore, equivalent changes made according to the scope of the patent application of the present invention still fall within the scope covered by the present invention.

Claims

1. A switch tube switching circuit for active battery balancing, characterized in that: It includes an interface expander, a state controller, a multiplexer and a switch tube array circuit; The switch tube array circuit is arranged between the balanced power source and a plurality of battery bodies, and the switch tube array circuit is used to control the on / off of the power path between each battery body and the balanced power source; The multiplexer is electrically connected to the switch tube array circuit, and the multiplexer is used to control the state of the switch tube array circuit so that only one voltage path between the battery body and the balanced power supply is turned on at the same time; The interface expander is electrically connected to the multiplexer through the state controller, and the interface expander is used to control the output state of the multiplexer through the state controller and based on the control instruction of the controller; The state controller is used to control the working state of each output channel of the multiplexer at the same time.

2. The switch tube switching circuit for active battery balancing according to claim 1, characterized in that: The multiplexer includes at least two decoders, each of which is electrically connected to a portion of switch tubes in the switch tube array circuit.

3. The switch tube switching circuit for active battery balancing according to claim 2, characterized in that: The state controller comprises an inverter, an input end of the inverter is electrically connected to the interface expander, and an output end of the inverter is electrically connected to an enable end of one or more of the decoders.

4. The switch tube switching circuit for active battery balancing according to claim 1, characterized in that: The switch tube array circuit comprises a plurality of first switch tube units, a plurality of second switch tube units, and a first connection end and a second connection end; Two ends of any one of the battery bodies are electrically connected to the multiplexer through a control end of the first switch tube unit, and two ends of any one of the battery bodies are also electrically connected to the first connection end and the second connection end through two conduction ends of the first switch tube unit; A unidirectional diode is further arranged between each of the first switch tube units and the multiplexer, and the two unidirectional diodes at both ends of any battery body are arranged opposite to each other; The two ends of any battery body are also electrically connected to the two second switch tube units through the first connection end and the second connection end, and the two second switch tube units belonging to the two ends of any battery body are also electrically connected to the positive terminal and the negative terminal of the balanced power supply, respectively.

5. The switch tube switching circuit for active battery balancing according to claim 4, characterized in that: The first switch tube unit and the second switch tube unit each include two MOS tubes connected back to back in series.

6. The switch tube switching circuit for active battery balancing according to claim 4, characterized in that: The control end of any of the first switch tube units is electrically connected to the multiplexer through a first optocoupler, and the control end of any of the second switch tube units is also provided with a second optocoupler, which is connected in series with two of the second optocouplers corresponding to the two ends of the same battery body, and the two second optocouplers connected in series are also electrically connected to the first connection end and the second connection end through a third optocoupler.

7. A battery management system, characterized in that: It comprises a battery pack, a balanced power supply, a controller and a switch tube switching circuit as described in any one of claims 1 to 6, wherein the battery pack comprises a plurality of battery bodies, and the controller is electrically connected to the interface expander.

8. The battery management system according to claim 7, characterized in that: The controller is electrically connected to the interface expander via any one of the interfaces including I2C, SPI and UART.

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