Power level circuit and bootstrap circuit
By designing pre-charge circuits and comparison circuits in the bootloader circuit of the power stage module, the charging and discharging of the bootloader capacitor is solved, and the problem of excessive discharge of the bootloader capacitor in the discontinuous conduction mode is achieved, and the stable conduction of the high-side switch and the high stability of the circuit are achieved.
Patent Information
- Application Number
- CN202422205273.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2025-07-01
- Estimated Expiration
- 2034-09-09
AI Technical Summary
In the discontinuous conduction mode of the power stage module, the bootstrap capacitor is over-discharged, resulting in the high-side switch being unable to turn on, affecting the stability of the circuit.
A bootstrap circuit including a bootstrap capacitor, a first precharge circuit and a second precharge circuit is designed. By comparing the circuit and the charging switch circuit, the charging and discharging of the bootstrap capacitor are controlled to ensure that the voltage difference is maintained within the preset voltage range.
Effectively prevent excessive discharge of the bootstrap capacitor, ensure that the high-side switch can be turned on when needed, and improve the stability and reliability of the circuit.
Smart Images
Figure CN223052927U_ABST
Abstract
Description
Technical Field
[0001] The present utility model relates to a power stage circuit and a bootstrap circuit, and particularly to a power stage circuit and a bootstrap circuit applicable to a power converter circuit. Background Art
[0002] In the related art of power stage modules, when the power stage module operates in the discontinuous-conduction mode (DCM) for too long, the bootstrap capacitor in the power stage module often discharges excessively, resulting in the inability of the high-side switch in the power stage module to conduct when conduction is required subsequently. Therefore, it is necessary to propose new circuits and / or methods to solve the above problems. Summary of the Utility Model
[0003] One aspect of the present utility model is a power stage circuit. The power stage circuit includes a switching circuit, a driving circuit, and a bootstrap circuit. The switching circuit includes a low-side switch and a high-side switch, wherein the low-side switch and the high-side switch are coupled to a switching node of the power stage circuit. The driving circuit is coupled to the low-side switch and the high-side switch and is used to drive the low-side switch and the high-side switch to conduct alternately according to a control signal. The bootstrap circuit is coupled to the switching circuit and the driving circuit and includes a bootstrap capacitor and a first pre-charging circuit, wherein the bootstrap capacitor is coupled to the switching node and a bootstrap node of the power stage circuit, the first pre-charging circuit is coupled to the switching node and the bootstrap node, and includes a charging switch circuit and a comparison circuit. The comparison circuit and the charging switch circuit are coupled to each other and are coupled to the bootstrap node. During a first period when both the low-side switch and the high-side switch are off, the bootstrap capacitor is charged by the first pre-charging circuit when the voltage difference across the bootstrap capacitor is lower than a first preset limit voltage value, and discharges when the voltage difference is higher than a second preset limit voltage value, so that the voltage difference is maintained within a preset voltage range, wherein the preset voltage range is determined by two different critical voltages of the comparison circuit.
[0004] In some embodiments, the charging switch circuit includes a charging switch and a unidirectional conduction switch, and the charging switch and the unidirectional conduction switch are coupled between the comparison circuit, a power supply signal, and the bootstrap node. During the first period, the bootstrap capacitor discharges to the bootstrap node until the voltage difference decreases from a preset voltage value to be lower than the first preset limit voltage value. During the first period, the charging switch and the unidirectional conduction switch switch from an off state to an on state when the voltage difference is lower than the first preset limit voltage value, so that the bootstrap capacitor is charged, and the charging switch and the unidirectional conduction switch switch from the on state to the off state when the voltage difference increases to be higher than the second preset limit voltage value, so that the bootstrap capacitor discharges to the bootstrap node.
[0005] In some embodiments, the comparison circuit is a hysteresis comparator. The preset voltage range is between the first preset limit voltage value and the second preset limit voltage value, and the hysteresis voltage of the hysteresis comparator is the difference between the two different critical voltages of the comparison circuit. The first pre-charge circuit further includes a voltage source, which is coupled between the switching node and the comparison circuit. The first preset limit voltage value is the fixed voltage of the voltage source, and the second preset limit voltage value is the fixed voltage plus the hysteresis voltage.
[0006] In some embodiments, the bootstrap circuit further includes a second pre-charge circuit, and the second pre-charge circuit is coupled to the bootstrap node and is configured to charge the bootstrap capacitor during a second period when the low-side switch is turned on, so as to increase the voltage difference to a preset voltage value greater than the second preset limit voltage value. The first pre-charge circuit and the second pre-charge circuit are configured to stop charging the bootstrap capacitor during a third period when the high-side switch is turned on.
[0007] In some embodiments, the bootstrap circuit further includes a first unidirectional conduction switch, and the first unidirectional conduction switch is coupled to a first power signal and the bootstrap node. During the second period when the low-side switch is turned on, the switching node switches to the ground voltage level, and the first unidirectional conduction switch switches from the off state to the on state to switch the bootstrap node to the first voltage level, and the bootstrap capacitor is charged according to the first voltage level and the ground voltage level, so as to increase the voltage difference to a preset voltage value greater than the second preset limit voltage value. The preset voltage value is determined by the voltage level of the first power signal and the conduction voltage of the first unidirectional conduction switch.
[0008] In some embodiments, the first pre-charge circuit further includes a voltage source, the charge switch circuit includes a charge switch and a second unidirectional conduction switch, the voltage source is coupled to the switching node and the first input terminal of the comparison circuit, the second input terminal of the comparison circuit is coupled to the bootstrap node, the signal output terminal of the comparison circuit is coupled to the control terminal of the charge switch, the charge switch is coupled to a second power signal, and the second unidirectional conduction switch is coupled to the charge switch and the bootstrap node. During the first period, the switching node switches to the output voltage level, the bootstrap node switches to a second voltage level generated according to the output voltage level and the preset voltage value, the bootstrap capacitor discharges to the bootstrap node, so that the bootstrap node drops from the second voltage level to a level lower than the third voltage level. The comparison circuit controls the charge switch and the second unidirectional conduction switch to switch from the off state to the on state when the bootstrap node is lower than the third voltage level, so as to increase the bootstrap node to a level higher than the fourth voltage level, and the comparison circuit controls the charge switch and the second unidirectional conduction switch to switch from the on state to the off state when the bootstrap node is higher than the fourth voltage level, so as to lower the bootstrap node to a level lower than the third voltage level. The difference between the third voltage level and the fourth voltage level is the difference between the two different critical voltages of the comparison circuit, and the two different critical voltages are associated with the fixed voltage provided by the voltage source.
[0009] In some embodiments, during the third period when the high-side switch is on, the switching node switches to the input voltage level, the bootstrap node switches to a fifth voltage level generated according to the input voltage level and the preset voltage value, so that the first unidirectional conduction switch, the charge switch and the second unidirectional conduction switch all switch to the off state, and the bootstrap capacitor discharges to the bootstrap node.
[0010] Another aspect of the present utility model is a bootstrap circuit. The bootstrap circuit is applicable to a power stage circuit including a driving circuit, a high-side switch, and a low-side switch, and includes a bootstrap capacitor, a first pre-charging circuit, and a second pre-charging circuit. The bootstrap capacitor is coupled to a switching node and a bootstrap node of the power stage circuit, wherein the high-side switch and the low-side switch are coupled to the switching node, and the driving circuit is coupled to the switching node and the bootstrap node. The first pre-charging circuit is coupled to the bootstrap node and is configured to charge the bootstrap capacitor during a first period when the low-side switch is turned on, so as to increase the voltage difference across the bootstrap capacitor to a preset voltage value. The second pre-charging circuit is coupled to the switching node and the bootstrap node, wherein during a second period when both the low-side switch and the high-side switch are turned off, the second pre-charging circuit is configured to charge the bootstrap capacitor when the voltage difference decreases from the preset voltage value to be lower than a first preset limit voltage value, and is configured to stop charging the bootstrap capacitor when the voltage difference increases from the first preset limit voltage value to be higher than a second preset limit voltage value, so as to maintain the voltage difference within a preset voltage range, wherein the second pre-charging circuit includes a charging switch circuit and a comparison circuit, and the comparison circuit and the charging switch circuit are coupled to each other and are coupled to the bootstrap node, and the preset voltage range is determined by two different critical voltages of the comparison circuit.
[0011] In some embodiments, the first pre-charging circuit includes a first unidirectional conduction switch, and the first unidirectional conduction switch is coupled to a first power supply signal and the bootstrap node. During the first period, the switching node switches to a ground voltage level, the first unidirectional conduction switch switches from an off state to an on state to switch the bootstrap node to a first voltage level, and the bootstrap capacitor is charged according to the first voltage level and the ground voltage level, so that the voltage difference increases to the preset voltage value. The preset voltage value is determined by the voltage level of the first power supply signal and the conduction voltage of the first unidirectional conduction switch.
[0012] In some embodiments, the second pre - charge circuit includes a voltage source, the charge - switch circuit includes a charge switch and a second unidirectional conduction switch. The voltage source is coupled to the switching node and the first input terminal of the comparison circuit. The second input terminal of the comparison circuit is coupled to the bootstrap node. The signal output terminal of the comparison circuit is coupled to the control terminal of the charge switch. The charge switch is coupled to a second power signal, and the second unidirectional conduction switch is coupled to the charge switch and the bootstrap node. During the second period, the switching node switches to the output voltage level, the bootstrap node switches to a second voltage level generated according to the output voltage level and the preset voltage value. The bootstrap capacitor discharges to the bootstrap node, so that the bootstrap node is reduced to a level lower than a third voltage level generated according to the output voltage level and the fixed voltage of the voltage source. When the bootstrap node is lower than the third voltage level, the comparison circuit controls the charge switch and the second unidirectional conduction switch to switch from the off state to the on state, so as to increase the bootstrap node by the hysteresis voltage of the comparison circuit. And when the bootstrap node increases the hysteresis voltage, the comparison circuit controls the charge switch and the second unidirectional conduction switch to switch from the on state to the off state, so as to reduce the bootstrap node to a level lower than the third voltage level. The voltage level of the second power signal is greater than the voltage level of the first power signal.
[0013] In summary, by maintaining the voltage difference across the bootstrap capacitor within a preset voltage range in the discontinuous conduction mode, the driving circuit can drive the high - side switch to switch to the on state through the high - side driving signal with an enabling level when the high - side switch needs to be turned on subsequently, without encountering the problem that the high - side switch cannot be turned on due to excessive discharge of the bootstrap capacitor. Therefore, the power - stage circuit and the bootstrap circuit of the present invention have advantages such as high stability. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 FIG. is a circuit block diagram of a power - stage circuit and its control circuit according to some embodiments of the present invention.
[0015] Figure 2A FIG. is a timing diagram of some signals related to the power - stage circuit according to some embodiments of the present invention.
[0016] Figure 2B For Figure 2A an enlarged timing diagram of some signals in
[0017] Figure 3 FIG. is a flowchart of a driving method for a bootstrap circuit in a power - stage circuit according to some embodiments of the present invention.
[0018] Figure 4 FIG. is a circuit schematic diagram of a second pre - charge circuit according to some embodiments of the present invention. Detailed implementation manners
[0019] Embodiments are given below and described in detail with reference to the accompanying drawings. However, the specific embodiments described are only used to explain the present invention and not to limit the present invention. The description of the structure and operation is not used to limit the execution order. Any structure formed by recombining elements and having equivalent functions is within the scope covered by the present invention.
[0020] The terms used throughout the specification and claims, unless otherwise specified, generally have their ordinary meanings as used in this field, in the content disclosed herein, and in the specific context.
[0021] Regarding the "coupled" or "connected" used herein, it can refer to two or more elements being in direct physical or electrical contact with each other, or being in indirect physical or electrical contact with each other. It can also refer to two or more elements operating or acting on each other.
[0022] Please refer to Figure 1 , Figure 1 FIG. is a circuit block diagram of a power stage circuit 100 and a control circuit 20 illustrated according to some embodiments of the present invention. In some embodiments, the power stage circuit 100 and the control circuit 20 can form a power converter circuit, such as a DC / DC converter, a single-phase or multi-phase buck converter, etc. The power stage circuit 100 can be coupled to a load node NL via an inductor element L, and the load node NL can be electrically coupled to a load device (not shown in the figure), such as a central processing unit (CPU), etc. In this way, the power converter circuit formed by the power stage circuit 100 and the control circuit 20 can supply power to the load device.
[0023] In some embodiments, as Figure 1 shown, the power stage circuit 100 includes a switch circuit 11, a drive circuit 13, and a bootstrap circuit 15. The switch circuit 11 includes a high-side switch QH and a low-side switch QL. The high-side switch QH is coupled to an input signal VIN and a switching node SW of the power stage circuit 100, and the low-side switch QL is coupled to the switching node SW and a ground signal GND. In addition, the switching node SW is coupled to the load node NL via the inductor element L. Specifically, the high-side switch QH and the low-side switch QL can each be implemented by a transistor (such as an N-type metal oxide semiconductor transistor, etc.), but the present invention is not limited thereto.
[0024] As Figure 1As shown, the driving circuit 13 includes a driver 131, a high-side buffer circuit BH, and a low-side buffer circuit BL. The driver 131 is coupled to the control circuit 20 to receive a control signal PWM output by the control circuit 20, and is configured to output a high-side driving signal GH and a low-side driving signal GL according to the control signal PWM. The signal input terminal of the high-side buffer circuit BH is coupled to the driver 131 to receive the high-side driving signal GH, and the signal output terminal of the high-side buffer circuit BH is coupled to the high-side switch QH. The signal input terminal of the low-side buffer circuit BL is coupled to the driver 131 to receive the low-side driving signal GL, and the signal output terminal of the low-side buffer circuit BL is coupled to the low-side switch QL. From the description of the driving circuit 13 above, in some embodiments, the driving circuit 13 is coupled to the high-side switch QH and the low-side switch QL, and is coupled to the control circuit 20.
[0025] In the above embodiments, the driver 131 can be implemented by one or more gate drivers, and the high-side buffer circuit BH and the low-side buffer circuit BL can each be implemented by one or more buffer amplifiers. That is to say, the high-side driving signal GH and the low-side driving signal GL can be buffered to the gate terminals of the transistors in the high-side switch QH and the low-side switch QL respectively.
[0026] In some embodiments, the driving circuit 13 is configured to drive the low-side switch QL and the high-side switch QH to conduct alternately according to the control signal PWM. Specifically, the control signal PWM can be a periodic signal, such as a pulse width modulation signal, etc. Next, the operation of the driving circuit 13 driving the switch circuit 11 will be further described in conjunction with Figure 2A to further illustrate the operation of the driving circuit 13 driving the switch circuit 11. Figure 2A FIG. is a timing diagram of some signals related to the power stage circuit 100 according to some embodiments of the present invention.
[0027] In some embodiments, as Figure 2A shown, during the period when the power stage circuit 100 operates in the continuous-conduction mode (CCM) (for example, Figure 2A during the periods P1 to P2 and P4 to P5), the high-side driving signal GH and the low-side driving signal GL output according to the control signal PWM are also both periodic signals. The high-side driving signal GH and the control signal PWM are substantially in phase with each other. For example, when the high-side driving signal GH is at the enabling level (such as Figure 2A the high voltage level shown), the control signal PWM may also be at the enabling level. The high-side driving signal GH (or the control signal PWM) and the low-side driving signal GL are substantially out of phase with each other. For example, when the high-side driving signal GH is at the disabling level (such as Figure 2AWhen the low-voltage level shown is present, the low-side drive signal GL may be at the enable level. Specifically, the enable level is the voltage level that can turn on the high-side switch QH or the low-side switch QL, and the disable level is the voltage level that can turn off the high-side switch QH or the low-side switch QL. From the above description, it can be seen that through the high-side drive signal GH and the low-side drive signal GL, the high-side switch QH and the low-side switch QL will conduct alternately.
[0028] When the high-side switch QH and the low-side switch QL conduct alternately, a voltage signal SSW is generated at the switching node SW. Figure 2A As can be seen, during the period when the power stage circuit 100 operates in the continuous conduction mode, the voltage level of the voltage signal SSW will switch between the voltage level of the input signal VIN and the voltage level of the ground signal GND according to the timing. Also, Figure 1 In the embodiment, the capacitive element COUT is coupled between the load node NL and the ground signal GND to form a circuit, such as a low-pass filter circuit, etc., with the inductive element L. This circuit can be used to process the voltage signal SSW to generate an output signal VOUT at the load node NL. In short, the drive circuit 13 can be used to drive the switch circuit 11 to generate an output signal VOUT at the load node NL. It should be understood that the power converter circuit composed of the power stage circuit 100 and the control circuit 20 can supply power to the load device through the output signal VOUT.
[0029] Note that the drive circuit 13 is not limited to driving the high-side switch QH and the low-side switch QL to conduct alternately. In some embodiments, the power stage circuit 100 can be controlled by the control circuit 20 to operate in the discontinuous-conduction mode (DCM). In the discontinuous conduction mode (for example, Figure 2A during the period P3), the drive circuit 13 switches both the high-side drive signal GH and the low-side drive signal GL to the disable level to turn off both the high-side switch QH and the low-side switch QL.
[0030] Continuing from the above description of the drive circuit 13, the power supply terminal of the low-side buffer circuit BL is coupled to the power supply signal VCC, and the ground terminal of the low-side buffer circuit BL is coupled to the ground signal GND. Since the voltage levels of the power supply signal VCC and the ground signal GND are stable, the low-side buffer circuit BL can stably buffer the low-side drive signal GL to the low-side switch QL to ensure that the low-side switch QL conducts or turns off within a preset time.
[0031] The power supply terminal of the high-side buffer circuit BH is coupled to the bootstrap node BT of the power stage circuit 100, and the ground terminal of the high-side buffer circuit BH is coupled to the switching node SW. It should be noted that the power supply terminal of the high-side buffer circuit BH cannot be directly coupled to the power supply signal VCC like the low-side buffer circuit BL. If the power supply terminal of the high-side buffer circuit BH is directly coupled to the power supply signal VCC, since the voltage signal SSW at the switching node SW (i.e., the ground terminal of the high-side buffer circuit BH) will switch to the voltage level of the input signal VIN when the high-side switch QH is turned on, the high-side buffer circuit BH will not be able to buffer the high-side drive signal GH to the high-side switch QH, and the high-side switch QH will be turned off. In view of this, the power stage circuit 100 requires the assistance of the bootstrap circuit 15 to control the voltage difference between the bootstrap node BT and the switching node SW to ensure that the high-side buffer circuit BH can buffer the high-side drive signal GH to the high-side switch QH within a preset time (i.e., ensure that the high-side switch QH is turned on within a preset time).
[0032] Please refer to again Figure 1 , the bootstrap circuit 15 includes a bootstrap capacitor CBT, a pre-charge circuit 151, and a pre-charge circuit 153. The bootstrap capacitor CBT is coupled to the switching node SW and the bootstrap node BT. The pre-charge circuit 151 is coupled to the bootstrap node BT. In addition, the pre-charge circuit 153 is also coupled to the switching node SW and the bootstrap node BT. From the above descriptions of the bootstrap circuit 15, the high-side buffer circuit BH, and the low-side buffer circuit BL, it can be seen that in some embodiments, the bootstrap circuit 15 is coupled to the switch circuit 11 and the drive circuit 13.
[0033] In some further embodiments, the pre-charge circuit 151 includes a unidirectional conduction switch D1. Specifically, the unidirectional conduction switch D1 can be implemented by a diode. The first end of the unidirectional conduction switch D1 (e.g., the anode end of the diode) is coupled to the power supply signal VCC, and the second end of the unidirectional conduction switch D1 (e.g., the cathode end of the diode) is coupled to the bootstrap node BT.
[0034] When operating under forward bias, the unidirectional conduction switch D1 switches to the on state, so that the voltage difference across the unidirectional conduction switch D1 becomes the conduction voltage V OND1 of the unidirectional conduction switch D1. In this embodiment, the unidirectional conduction switch D1 is implemented by a Schottky diode, and its conduction voltage V OND1 is, for example, 0.2 volts. When the unidirectional conduction switch D1 is in the on state, current can flow from the first end of the unidirectional conduction switch D1 to the second end of the unidirectional conduction switch D1. When operating under reverse bias, the unidirectional conduction switch D1 switches to the off state, which causes the current not to flow from the first end of the unidirectional conduction switch D1 to the second end of the unidirectional conduction switch D1.
[0035] Furthermore, the pre-charge circuit 153 includes a voltage source SV, a comparison circuit CMP, and a charging switch circuit 531. The charging switch circuit 531 includes a charging switch QA and a unidirectional conduction switch D2. The voltage source SV is used to provide a fixed voltage VBS. Specifically, the comparison circuit CMP can be implemented by a hysteresis comparator (which can also be referred to as a Schmitt trigger), the unidirectional conduction switch D2 can be implemented by a diode, and the charging switch QA can be implemented by a digital switch circuit. In this embodiment, the unidirectional conduction switch D2 is implemented by a Schottky diode. The voltage source SV is coupled between the switching node SW and the non-inverting input terminal of the comparison circuit CMP (marked as “+” in Figure 1 ). The signal output terminal of the comparison circuit CMP and the control terminal of the charging switch QA are coupled to the node NG. The first terminal of the charging switch QA is coupled to the power supply signal VEE. The first terminal of the unidirectional conduction switch D2 (such as the anode terminal of the diode) and the second terminal of the charging switch QA are coupled to the node NS, and the second terminal of the unidirectional conduction switch D2 (such as the cathode terminal of the diode) and the inverting input terminal of the comparison circuit CMP (marked as “-” in Figure 1 ) are coupled to the bootstrap node BT. From the above description, it can be seen that in some embodiments, the comparison circuit CMP and the charging switch circuit 531 are coupled to each other and are coupled to the bootstrap node BT. In some embodiments, the voltage level of the power supply signal VEE is greater than the voltage level of the power supply signal VCC. In other embodiments, the voltage level of the power supply signal VEE can be the same as the voltage level of the input signal VIN.
[0036] In the above embodiment, the comparison circuit CMP outputs a control signal CS according to the voltage level of the inverting input terminal and the voltage level of the non-inverting input terminal. For example, when the voltage level of the inverting input terminal is lower than the voltage level of the non-inverting input terminal, the comparison circuit CMP outputs a control signal CS with an enabling level. When the voltage level of the inverting input terminal is higher than the voltage level of the non-inverting input terminal by a preset difference, the comparison circuit CMP outputs a control signal CS with a disabling level. Specifically, the preset difference can be, for example, the hysteresis voltage ΔU (such as 0.2 volts) of the hysteresis comparator (or the comparison circuit CMP). The hysteresis voltage ΔU is the difference between two different critical voltages of the comparison circuit CMP. In one embodiment, the above two different critical voltages are associated with the fixed voltage VBS provided by the voltage source SV. In another embodiment, one of the above two different critical voltages is the fixed voltage VBS provided by the voltage source SV, and the other is the sum of the fixed voltage VBS and the hysteresis voltage ΔU.
[0037] In accordance with the above description, when comparing the control signal CS of the output enable level by the comparison circuit CMP, the charging switch QA and the unidirectional conduction switch D2 are switched to the conducting state, enabling current to flow between the first end of the charging switch QA and the bootstrap node BT. When comparing the control signal CS of the output disable level by the comparison circuit CMP, the charging switch QA and the unidirectional conduction switch D2 are switched to the off state, preventing current from flowing between the first end of the charging switch QA and the bootstrap node BT. It should be understood that the operation of the unidirectional conduction switch D2 is similar to that of the unidirectional conduction switch D1, so it will not be elaborated here.
[0038] Next, in conjunction with Figure 2A 、 Figure 2B and Figure 3 the operation of the bootstrap circuit 15 will be further described. Figure 2B is Figure 2A an enlarged view of the voltage signal SBT at the bootstrap node BT, the voltage signal SSW at the switching node SW, and the voltage difference ΔVBT across the bootstrap capacitor CBT in Figure 3 is a flowchart of the driving method 300 illustrated according to some embodiments of the present invention. In some embodiments, as Figure 3 shown, the driving method 300 includes a plurality of operations S301 to S303, but the present invention is not limited thereto.
[0039] In operation S301, during the period P1 when the high-side switch QH is conducting, the bootstrap capacitor CBT discharges to the bootstrap node BT.
[0040] During the period P1, as Figure 2B shown, the voltage signal SSW (i.e., the voltage level of the switching node SW) at the switching node SW switches to the voltage level of the input signal VIN (i.e., the input voltage level), for example, 12 volts. At the beginning of the period P1, the voltage level of the voltage signal SBT (i.e., the voltage level of the bootstrap node BT) at the bootstrap node BT switches to Figure 2B the voltage level V1 shown. Specifically, the voltage level V1 is the voltage level of the input signal VIN plus the voltage difference ΔVBT across the bootstrap capacitor CBT (i.e., the voltage difference between the bootstrap node BT and the switching node SW). At the beginning of the period P1, the voltage difference ΔVBT is substantially the preset voltage value VPS1 (for example, 4.8 volts). Therefore, the voltage level of the voltage signal SBT (for example, 16.8 volts) is greater than the voltage level of the power supply signal VCC (for example, 5 volts), causing the unidirectional conduction switch D1 to operate in reverse bias and switch to the off state.
[0041] In addition, during period P1, the voltage level at the non-inverting input terminal of the comparison circuit CMP is the voltage level of the input signal VIN (i.e., the voltage level of the voltage signal SSW at the switching node SW) plus the fixed voltage VBS of the voltage source SV. In some embodiments, the fixed voltage VBS is less than the voltage level of the power supply signal VCC, such as 4.4 volts. Therefore, the voltage level at the non-inverting input terminal of the comparison circuit CMP is, for example, 16.4 volts. Also, as described above, the voltage level of the voltage signal SBT at the bootstrap node BT (i.e., the inverting input terminal of the comparison circuit CMP) is the voltage level of the input signal VIN plus the preset voltage value VPS1, such as 16.8 volts. At this time, the voltage level at the inverting input terminal of the comparison circuit CMP (e.g., 16.8 volts) is still higher than the voltage level at the non-inverting input terminal of the comparison circuit CMP (e.g., 16.4 volts) by a preset difference (e.g., 0.2 volts), and the comparison circuit CMP generates a control signal CS with a disabling level. Therefore, the charging switch QA in the precharge circuit 153 is turned off according to the control signal CS with the disabling level, and further turns off the unidirectional conduction switch D2 in the precharge circuit 153. In short, the comparison circuit CMP controls both the charging switch QA and the unidirectional conduction switch D2 to be turned off during period P1.
[0042] In short, during period P1, the voltage signal SBT at the bootstrap node BT switches to the voltage level V1, so that the unidirectional conduction switch D1, the charging switch QA, and the unidirectional conduction switch D2 all switch to the off state. In other words, the precharge circuit 151 and the precharge circuit 153 stop charging the bootstrap capacitor CBT during period P1. In this way, the bootstrap capacitor CBT discharges to the bootstrap node BT (the voltage difference ΔVBT correspondingly decreases) to supply power to the high-side buffer circuit BH in the driving circuit 13.
[0043] In operation S302, during period P2 when the low-side switch QL is turned on, the bootstrap capacitor CBT is charged through the precharge circuit 151 to increase the voltage difference ΔVBT to the preset voltage value VPS1.
[0044] During period P2, as Figure 2B shown, the voltage level of the voltage signal SSW at the switching node SW (i.e., the voltage level of the switching node SW) switches to the voltage level of the ground signal GND (i.e., the ground voltage level). At the beginning of period P2, the voltage level of the voltage signal SBT at the bootstrap node BT (i.e., the voltage level of the bootstrap node BT) is the voltage level of the ground signal GND plus the voltage difference ΔVBT, which is lower than the voltage level of the power supply signal VCC, so that the unidirectional conduction switch D1 operates in a forward bias. In this way, the voltage level of the voltage signal SBT switches to the voltage level of the power supply signal VCC minus the conduction voltage V of the unidirectional conduction switch D1 OND1 (i.e., Figure 2BThe voltage level V2 shown). Since the voltage difference ΔVBT does not reach the voltage level of V2 minus the voltage level of the ground signal GND (i.e., the preset voltage value VPS1), the precharge circuit 151 charges the boost capacitor CBT to increase the voltage difference ΔVBT to the preset voltage value VPS1. It should be understood that in the case where the voltage level of the ground signal GND is substantially 0 volts, the preset voltage value VPS1 is equivalent to the voltage level of the power supply signal VCC minus the conduction voltage V of the unidirectional conduction switch D1 OND1 , that is, the preset voltage value VPS1 is equal to the voltage level V2. Accordingly, in some embodiments, the preset voltage value VPS1 is determined by the voltage level of the power supply signal VCC and the conduction voltage V of the unidirectional conduction switch D1 OND1 .
[0045] In addition, during period P2, the voltage level at the non-inverting input terminal of the comparator circuit CMP is the voltage level of the ground signal GND (i.e., the voltage level of the voltage signal SSW at the switching node SW) plus the fixed voltage VBS, such as 4.4 volts. Also, as described above, the voltage level of the voltage signal SBT at the boost node BT (i.e., the inverting input terminal of the comparator circuit CMP) is the voltage level of the power supply signal VCC minus the conduction voltage V OND1 (i.e., the voltage level V2), such as 4.8 volts. At this time, the voltage level at the inverting input terminal of the comparator circuit CMP (e.g., 4.8 volts) is higher than the voltage level at the non-inverting input terminal of the comparator circuit CMP (e.g., 4.4 volts) by a preset difference (e.g., 0.2 volts), and the comparator circuit CMP generates a control signal CS with a disabling level. Therefore, the charging switch QA and the unidirectional conduction switch D2 in the precharge circuit 153 are still controlled by the comparator circuit CMP and are both turned off.
[0046] In some embodiments, the control circuit 20 controls the power stage circuit 100 to operate in a discontinuous conduction mode. Therefore, operation S303 is performed.
[0047] In operation S303, during period P3 when both the low-side switch QL and the high-side switch QH are turned off, when the voltage difference ΔVBT across the boost capacitor CBT decreases from the preset voltage value VPS1 to below a preset limit voltage value VLIM1, the boost capacitor CBT is charged, and when the voltage difference ΔVBT across the boost capacitor CBT increases from the preset limit voltage value VLIM1 to above another preset limit voltage value VLIM2, the charging of the boost capacitor CBT is stopped to maintain the voltage difference ΔVBT across the boost capacitor CBT within a preset voltage range RV.
[0048] During period P3, as Figure 2BAs shown, the voltage level of the voltage signal SSW at the switching node SW is switched to the voltage level of the output signal VOUT (i.e., the output voltage level), for example, 3.3 volts. At the beginning of period P3, the voltage level of the voltage signal SBT at the bootstrap node BT is switched to the voltage level of the output signal VOUT plus a voltage difference ΔVBT that is substantially a preset voltage value VPS1 (i.e., Figure 2B the voltage level V3 shown). Therefore, the voltage level of the voltage signal SBT (e.g., 8.1 volts) is greater than the voltage level of the power supply signal VCC (e.g., 5 volts), so that the unidirectional conduction switch D1 operates with reverse bias.
[0049] In addition, at the beginning of period P3, the voltage level at the non-inverting input terminal of the comparison circuit CMP is the voltage level of the output signal VOUT (i.e., the voltage level of the voltage signal SSW at the switching node SW) plus a fixed voltage VBS, for example, 7.7 volts. Also, as described above, the voltage level of the voltage signal SBT at the bootstrap node BT (i.e., the inverting input terminal of the comparison circuit CMP) is the voltage level of the output signal VOUT plus the preset voltage value VPS1, for example, 8.1 volts. At this time, the voltage level at the inverting input terminal of the comparison circuit CMP (e.g., 8.1 volts) is still higher than the preset difference compared to the voltage level at the non-inverting input terminal of the comparison circuit CMP (e.g., 7.7 volts). Therefore, the charging switch QA and the unidirectional conduction switch D2 in the precharge circuit 153 are still controlled by the comparison circuit CMP and are both turned off.
[0050] In short, at the beginning of period P3, the voltage signal SBT at the bootstrap node BT is switched to the voltage level V3, so that the unidirectional conduction switch D1, the charging switch QA, and the unidirectional conduction switch D2 are all switched to the off state. In this way, the bootstrap capacitor CBT discharges to the bootstrap node BT (the voltage difference ΔVBT correspondingly decreases), so that the voltage level of the voltage signal SBT at the bootstrap node BT starts to decrease from the voltage level V3.
[0051] Continuing from the above description, when the voltage level of the voltage signal SBT at the bootstrap node BT drops below the voltage level of the output signal VOUT plus the fixed voltage VBS (i.e., Figure 2B the voltage level V4 shown, for example, 7.7 volts), the comparison circuit CMP outputs a control signal CS with an enabling level, and the charging switch QA conducts according to the control signal CS with the enabling level, and further makes the unidirectional conduction switch D2 operate with forward bias (i.e., the unidirectional conduction switch D2 conducts). In short, the comparison circuit CMP when the voltage signal SBT drops below the voltage level V4 (i.e., Figure 2BAt the time point T1 shown, control the charging switch QA and the unidirectional conduction switch D2 to switch from the off state to the on state. That is, the pre-charge circuit 153 can start charging the bootstrap capacitor CBT, so that the voltage level of the voltage signal SBT starts to increase from the voltage level V4. It should be understood that at the same time, the voltage difference ΔVBT decreases from the preset voltage value VPS1 to below the preset limit voltage value VLIM1, and then starts to increase from the preset limit voltage value VLIM1. From the above description, it can be seen that during the period P3, the bootstrap capacitor CBT discharges to the bootstrap node BT until the voltage difference ΔVBT decreases from the preset voltage value VPS1 to below the preset limit voltage value VLIM1. According to the above description, the preset limit voltage value VLIM1 is determined by the fixed voltage VBS. Specifically, the preset limit voltage value VLIM1 is equal to the fixed voltage VBS.
[0052] For another example Figure 2B As shown, when the voltage difference ΔVBT increases to above the preset limit voltage value VLIM2 (i.e., the fixed voltage VBS plus the preset difference (represented by the hysteresis voltage ΔU of the hysteresis comparator (i.e., the comparison circuit CMP) in Figure 2B ), the voltage level of the voltage signal SBT at the bootstrap node BT increases to above the voltage level V4 plus the hysteresis voltage ΔU (i.e., Figure 2B the voltage level V5 shown), such as 7.9 volts. At this time, the comparison circuit CMP outputs a control signal CS of the disable level, and the charging switch QA is turned off according to the control signal CS of the disable level, and further turns off the unidirectional conduction switch D2. In short, the comparison circuit CMP controls the charging switch QA and the unidirectional conduction switch D2 to switch from the on state to the off state when the voltage signal SBT increases to above the voltage level V5 (or increases by the hysteresis voltage ΔU) (i.e., Figure 2B at the time point T2 shown). In this way, the bootstrap capacitor CBT discharges to the bootstrap node BT (the voltage difference ΔVBT also correspondingly decreases), so that the voltage level of the voltage signal SBT starts to decrease from the voltage level V5.
[0053] It should be understood that when the voltage level of the voltage signal SBT at the bootstrap node BT drops again to be lower than the voltage level V4 (i.e., the voltage difference ΔVBT drops again to be lower than the preset limit voltage value VLIM1), the pre-charge circuit 153 will charge the bootstrap capacitor CBT again (the voltage difference ΔVBT correspondingly increases). When the voltage level of the voltage signal SBT increases again to be higher than the voltage level V5 (i.e., the voltage difference ΔVBT increases again to be higher than the preset limit voltage value VLIM2), the pre-charge circuit 153 will stop charging the bootstrap capacitor CBT, and the bootstrap capacitor CBT will discharge to the bootstrap node BT (the voltage difference ΔVBT correspondingly decreases). Therefore, during the period P3, the voltage difference ΔVBT across the bootstrap capacitor CBT will vary periodically within the preset voltage range RV (i.e., between the preset limit voltage value VLIM1 and the preset limit voltage value VLIM2).
[0054] It should be noted that by maintaining the voltage difference ΔVBT across the bootstrap capacitor CBT within the preset voltage range RV (i.e., between the preset limit voltage value VLIM1 and the preset limit voltage value VLIM2) in the discontinuous conduction mode, the drive circuit 13 can drive the high-side switch QH to switch to the on state by the high-side drive signal GH with an enabling level when it is necessary to turn on the high-side switch QH subsequently (for example, Figure 2B during the period P4 shown immediately following the period P3), without encountering the problem that the high-side switch QH cannot be turned on due to excessive discharge of the bootstrap capacitor CBT. Therefore, the power stage circuit 100, the bootstrap circuit 15, and the drive method 300 of the present utility model have advantages such as high stability.
[0055] According to the above, the preset limit voltage value VLIM1 is equal to the fixed voltage VBS, and the preset limit voltage value VLIM2 is the fixed voltage VBS plus the hysteresis voltage ΔU of the hysteresis comparator (i.e., the comparison circuit CMP). Therefore, it can be known that the difference between the preset limit voltage value VLIM1 and the preset limit voltage value VLIM2 is the hysteresis voltage ΔU, and the preset voltage range RV between the preset limit voltage value VLIM1 and the preset limit voltage value VLIM2 is determined by the hysteresis voltage ΔU, that is, determined by two different critical voltages of the comparison circuit CMP.
[0056] During the period P4, neither the pre-charge circuit 151 nor the pre-charge circuit 153 charges the bootstrap capacitor CBT (similar to the description of the period P1), and the bootstrap capacitor CBT discharges to the bootstrap node BT. Therefore, as Figure 2B shown, the voltage difference ΔVBT across the bootstrap capacitor CBT will decrease. Then, during the period P5 immediately following the period P4, the pre-charge circuit 151 charges the bootstrap capacitor CBT (similar to the description of the period P2). Therefore, as Figure 2BAs shown, the voltage difference ΔVBT across the bootstrap capacitor CBT increases toward the preset voltage value VPS1. It should be understood that at the end of period P5, the voltage difference ΔVBT has not reached the preset voltage value VPS1 and starts to decrease again because the high-side switch QH switches to the conducting state.
[0057] In the above embodiments, during period P1 or period P4, the voltage level (e.g., voltage level V1) of the voltage signal SBT at the bootstrap node BT may be higher than the voltage level of the power supply signal VEE (the voltage level of the power supply signal VEE is equal to the voltage level of the input signal VIN in some embodiments, e.g., 12 volts). At this time, the unidirectional conduction switch D2 in the precharge circuit 153 can operate in reverse bias to prevent current from flowing from the bootstrap node BT to the power supply signal VEE.
[0058] In the above embodiments, the charging switch circuit 531 (i.e., the charging switch QA and the unidirectional conduction switch D2) is controlled to conduct or turn off by the comparison circuit CMP and the fixed voltage VBS of the voltage source SV to avoid directly charging the bootstrap capacitor CBT with the power supply signal VEE (which has the same voltage level as the input signal VIN in some embodiments). If the bootstrap capacitor CBT is directly charged with the power supply signal VEE, the high-side buffer circuit BH may be burned out due to an excessive voltage difference ΔVBT.
[0059] Then, in conjunction with Figure 4 The circuit structure of the precharge circuit 153 in the bootstrap circuit 15 will be further described. Figure 4 FIG. is a circuit schematic diagram of the precharge circuit 153 illustrated according to some embodiments of the present invention.
[0060] In some embodiments, as Figure 4 shown, Figure 1 In the precharge circuit 153, the charging switch QA is implemented through a level shifter LVL and a transistor QB (e.g., a P-type metal-oxide semiconductor transistor, etc.). Specifically, the level shifter LVL is coupled to the node NG and the control terminal (e.g., the gate terminal) of the transistor QB. The first terminal (e.g., the source terminal) of the transistor QB is coupled to the power supply signal VEE, and the second terminal (e.g., the drain terminal) of the transistor QB is coupled to the node NS to which the first terminal of the unidirectional conduction switch D2 is coupled. The level shifter LVL is used to convert the control signal CS from the enabling level to the conducting level capable of turning on the transistor QB and to convert the control signal CS from the disabling level to the turning-off level capable of turning off the transistor QB.
[0061] Although the present utility model has been disclosed above in an implementation manner, it is not intended to limit the present utility model. Those skilled in the art can make various modifications and refinements without departing from the spirit and scope of the present utility model. Therefore, the protection scope of the present utility model shall be determined by the scope defined by the appended claims.
[0062]
Symbol Description
[0063] 11: Switching circuit
[0064] 13: Driving circuit
[0065] 15: Bootstrap circuit
[0066] 20: Control circuit
[0067] 100: Power stage circuit
[0068] 131: Driver
[0069] 151: Pre-charge circuit
[0070] 153: Pre-charge circuit
[0071] 300: Driving method
[0072] 531: Charge switching circuit
[0073] BH: High-side buffer circuit
[0074] BL: Low-side buffer circuit
[0075] BT: Bootstrap node
[0076] CBT: Bootstrap capacitor
[0077] CMP: Comparison circuit
[0078] COUT: Capacitor element
[0079] CS: Control signal
[0080] D1: Unidirectional conduction switch
[0081] D2: Unidirectional conduction switch
[0082] GH: High-side drive signal
[0083] GL: Low-side drive signal
[0084] GND: Ground signal
[0085] L: Inductor element
[0086] LVL: Level shifter
[0087] NG, NS: Node
[0088] NL: Load Node
[0089] P1, P2, P3, P4, P5: Periods
[0090] PWM: Control Signal
[0091] QA: Charging Switch
[0092] QB: Transistor
[0093] QH: High-Side Switch
[0094] QL: Low-Side Switch
[0095] RV: Preset Voltage Range
[0096] S301~S303: Operations
[0097] SBT, SSW: Voltage Signals
[0098] SV: Voltage Source
[0099] SW: Switching Node
[0100] T1, T2: Time Points
[0101] V1, V2, V3, V4, V5: Voltage Levels
[0102] VBS: Fixed Voltage
[0103] VCC: Power Supply Signal
[0104] VEE: Power Supply Signal
[0105] VIN: Input Signal
[0106] VLIM1, VLIM2: Preset Limiting Voltage Values
[0107] VOUT: Output Signal
[0108] VPS1: Preset Voltage Value
[0109] V OND1 : Conduction Voltage
[0110] ΔU: Hysteresis Voltage
[0111] ΔVBT: Voltage Difference
Claims
1. A power stage circuit, characterized in that: Include: A switch circuit, comprising a low-side switch and a high-side switch, wherein the low-side switch and the high-side switch are coupled to a switching node of the power stage circuit; A driving circuit coupled to the low-side switch and the high-side switch and used for driving the low-side switch and the high-side switch to be turned on alternately according to a control signal; as well as a bootstrap circuit coupled to the switch circuit and the drive circuit, and comprising a bootstrap capacitor and a first pre-charging circuit, wherein the bootstrap capacitor is coupled to the switch node and the bootstrap node of the power stage circuit, the first pre-charging circuit is coupled to the switch node and the bootstrap node, and comprises a charging switch circuit and a comparison circuit, the comparison circuit and the charging switch circuit are coupled to each other and coupled to the bootstrap node, and During a first period when both the low-side switch and the high-side switch are turned off, the bootstrap capacitor is charged by the first pre-charging circuit when the voltage difference across the bootstrap capacitor is lower than a first preset limit voltage value, and is discharged when the voltage difference is higher than a second preset limit voltage value, so that the voltage difference is maintained within a preset voltage range, wherein the preset voltage range is determined by two different critical voltages of the comparison circuit.
2. The power stage circuit according to claim 1, characterized in that: The charging switch circuit includes a charging switch and a unidirectional conduction switch, and the charging switch and the unidirectional conduction switch are coupled between the comparison circuit, the power signal and the bootstrap node, and wherein during the first period, the bootstrap capacitor discharges to the bootstrap node until the voltage difference decreases from a preset voltage value to below the first preset limit voltage value, and During the first period, the charging switch and the unidirectional conduction switch are switched from the off state to the on state when the voltage difference is lower than the first preset limit voltage value, so that the bootstrap capacitor is charged, and the charging switch and the unidirectional conduction switch are switched from the on state to the off state when the voltage difference increases to be higher than the second preset limit voltage value, so that the bootstrap capacitor discharges to the bootstrap node.
3. The power stage circuit according to claim 1, characterized in that: The comparison circuit is a hysteresis comparator, the preset voltage range is between the first preset limit voltage value and the second preset limit voltage value, and the hysteresis voltage of the hysteresis comparator is the difference between the two different threshold voltages of the comparison circuit, and The first pre-charging circuit further includes a voltage source, which is coupled between the switching node and the comparison circuit. The first preset limit voltage value is a constant voltage of the voltage source, and the second preset limit voltage value is the constant voltage plus the hysteresis voltage.
4. The power stage circuit according to claim 1, characterized in that: The bootstrap circuit further comprises a second pre-charging circuit, and the second pre-charging circuit is coupled to the bootstrap node and is used to charge the bootstrap capacitor during a second period during which the low-side switch is turned on, so as to increase the voltage difference to a preset voltage value greater than the second preset limit voltage value, and The first pre-charging circuit and the second pre-charging circuit are used to stop charging the bootstrap capacitor during a third period when the high-side switch is turned on.
5. The power stage circuit according to claim 1, characterized in that: The bootstrap circuit further includes a first unidirectional conduction switch, and the first unidirectional conduction switch is coupled to the first power signal and the bootstrap node. wherein during a second period when the low-side switch is turned on, the switching node is switched to a ground voltage level, the first unidirectional conduction switch is switched from an off state to an on state, so as to switch the bootstrap node to a first voltage level, and the bootstrap capacitor is charged according to the first voltage level and the ground voltage level, so that the voltage difference increases to a preset voltage value greater than the second preset limit voltage value, and The preset voltage value is determined by the voltage level of the first power signal and the conduction voltage of the first unidirectional conduction switch.
6. The power stage circuit according to claim 5, characterized in that: The first pre-charging circuit further includes a voltage source, the charging switch circuit includes a charging switch and a second unidirectional conduction switch, the voltage source is coupled to the switching node and the first input terminal of the comparison circuit, the second input terminal of the comparison circuit is coupled to the bootstrap node, the signal output terminal of the comparison circuit is coupled to the control terminal of the charging switch, the charging switch is coupled to the second power signal, and the second unidirectional conduction switch is coupled to the charging switch and the bootstrap node, wherein during the first period, the switching node is switched to the output voltage level, the bootstrap node is switched to a second voltage level generated according to the output voltage level and the preset voltage value, the bootstrap capacitor discharges to the bootstrap node so that the bootstrap node is reduced from the second voltage level to below a third voltage level, the comparison circuit controls the charging switch and the second unidirectional conduction switch to switch from the off state to the on state when the bootstrap node is below the third voltage level so as to increase the bootstrap node to be above a fourth voltage level, and the comparison circuit controls the charging switch and the second unidirectional conduction switch to switch from the on state to the off state when the bootstrap node is above the fourth voltage level so as to reduce the bootstrap node to be below the third voltage level, and The difference between the third voltage level and the fourth voltage level is the difference between the two different threshold voltages of the comparison circuit, and the two different threshold voltages are associated with the constant voltage provided by the voltage source.
7. The power stage circuit according to claim 6, characterized in that: During a third period when the high-side switch is turned on, the switching node is switched to the input voltage level, and the bootstrap node is switched to a fifth voltage level generated according to the input voltage level and the preset voltage value, so that the first unidirectional conduction switch, the charging switch and the second unidirectional conduction switch are all switched to the off state, and the bootstrap capacitor discharges to the bootstrap node.
8. A bootstrap circuit, characterized in that: Applicable to power stage circuits including driver circuits, high-side switches and low-side switches, and include: a bootstrap capacitor coupled to a switching node and a bootstrap node of the power stage circuit, wherein the high-side switch and the low-side switch are coupled to the switching node, and the driving circuit is coupled to the switching node and the bootstrap node; A first pre-charging circuit is coupled to the bootstrap node and is used to charge the bootstrap capacitor during a first period when the low-side switch is turned on, so as to increase the voltage difference between the two ends of the bootstrap capacitor to a preset voltage value; as well as a second pre-charging circuit coupled to the switching node and the bootstrap node, wherein during the second period when both the low-side switch and the high-side switch are turned off, the second pre-charging circuit is used to charge the bootstrap capacitor when the voltage difference decreases from the preset voltage value to below the first preset limit voltage value, and is used to stop charging the bootstrap capacitor when the voltage difference increases from the first preset limit voltage value to above the second preset limit voltage value, so as to maintain the voltage difference within a preset voltage range, The second pre-charging circuit includes a charging switch circuit and a comparison circuit, and the comparison circuit and the charging switch circuit are coupled to each other and to the bootstrap node, and The preset voltage range is determined by two different threshold voltages of the comparison circuit.
9. The bootstrap circuit according to claim 8, characterized in that: The first pre-charging circuit includes a first unidirectional conduction switch, and the first unidirectional conduction switch is coupled to the first power signal and the bootstrap node. wherein during the first period, the switching node is switched to the ground voltage level, the first unidirectional conduction switch is switched from an off state to an on state, so as to switch the bootstrap node to a first voltage level, and the bootstrap capacitor is charged according to the first voltage level and the ground voltage level, so that the voltage difference increases to the preset voltage value, and The preset voltage value is determined by the voltage level of the first power signal and the conduction voltage of the first unidirectional conduction switch.
10. The bootstrap circuit according to claim 9, characterized in that: The second pre-charging circuit includes a voltage source, the charging switch circuit includes a charging switch and a second unidirectional conduction switch, the voltage source is coupled to the switching node and the first input terminal of the comparison circuit, the second input terminal of the comparison circuit is coupled to the bootstrap node, the signal output terminal of the comparison circuit is coupled to the control terminal of the charging switch, the charging switch is coupled to the second power signal, and the second unidirectional conduction switch is coupled to the charging switch and the bootstrap node, wherein during the second period, the switching node is switched to the output voltage level, the bootstrap node is switched to the second voltage level generated according to the output voltage level and the preset voltage value, the bootstrap capacitor discharges to the bootstrap node to reduce the bootstrap node to a third voltage level lower than the output voltage level and the constant voltage of the voltage source, the comparison circuit controls the charging switch and the second unidirectional conduction switch to switch from the off state to the on state when the bootstrap node is lower than the third voltage level, so as to increase the bootstrap node by the hysteresis voltage of the comparison circuit, and the comparison circuit controls the charging switch and the second unidirectional conduction switch to switch from the on state to the off state when the bootstrap node increases the hysteresis voltage, so as to reduce the bootstrap node to a level lower than the third voltage level, and The voltage level of the second power signal is greater than the voltage level of the first power signal.