Semiconductor device

Abstract

The utility model provides a semiconductor device, which comprises a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure and a plurality of drain structures, and is characterized in that the plurality of source lines are positioned on the substrate, extend along a first direction and are arranged at intervals along a second direction; each source electrode bonding pad is located on the corresponding source electrode line, extends in the second direction and is located between the adjacent source electrode lines; the plurality of unit structures are arranged on the source electrode bonding pad along the first direction and the second direction and are connected with the source electrode bonding pad, and at least two unit structures which are mutually staggered in the first direction are positioned on the same source electrode bonding pad; the gate structures extend in the second direction and are connected with the unit structures located on the same source electrode bonding pad; the plurality of drain electrode structures are respectively located above the corresponding source electrode bonding pads, and each drain electrode structure is connected with the unit structure connected with the corresponding source electrode bonding pad; the utility model improves the electrical performance of the semiconductor device.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a semiconductor device. Background Art

[0002] Semiconductor transistors (such as metal-oxide-semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, switches and other applications. Traditional MOS transistors adopt a planar structure. As the technology of semiconductor integrated circuits develops over time, MOS transistors adopt a stacked structure to achieve miniaturization of the transistors. In the design of the stacked structure, several source lines are usually formed on a substrate, then a gate structure is formed on the source lines, several channel structures are formed in the gate structure, the channel structures are connected to the source lines, and corresponding drain structures are formed on each channel structure. One drain structure is connected to the source line through one channel structure, so that the driving ability of the semiconductor device is limited, affecting the electrical performance of the semiconductor device. Summary of the Utility Model

[0003] The purpose of the utility model is to provide a semiconductor device to improve the electrical performance of the semiconductor device.

[0004] To achieve the above purpose, the utility model provides a semiconductor device, including:

[0005] A substrate;

[0006] Several source lines, located on the substrate, extending along a first direction and arranged at intervals from each other along a second direction;

[0007] Several source pads, each source pad being located on a corresponding source line and extending along the second direction between adjacent source lines;

[0008] Several unit structures, arranged along the first direction and the second direction on the source pads and connected to the source pads, and at least two unit structures that are offset from each other in the first direction are located on the same source pad;

[0009] A gate structure, extending along the second direction and connecting the unit structures located on the same source pad;

[0010] Several drain structures, respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad.

[0011] Optionally, both ends of the source pad along the first direction are located on the source line, and both ends of the source pad along the second direction extend between adjacent source lines.

[0012] Optionally, the shape of the source pad includes a rhombus or a rectangle.

[0013] Optionally, a plurality of the source pads are arranged in an array, and two adjacent columns of the source pads are staggered along the second direction.

[0014] Optionally, four of the unit structures are located on one of the source pads and are respectively located at four ends of the source pad.

[0015] Optionally, the gate structure includes an annular end.

[0016] Optionally, the gate structure includes a first portion and a second portion located on two sides of the unit structure along the first direction, and the first portion and the second portion are connected by the annular end.

[0017] Optionally, a gate dielectric layer and a barrier layer are provided between the gate structure and the unit structure, and a first isolation material layer is filled between a plurality of the gate structures.

[0018] In the semiconductor device provided by the present invention, it includes: a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure, and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals from each other along a second direction; each source pad is located on a corresponding source line and extends along the second direction and is located between adjacent source lines; the plurality of unit structures are arranged along the first direction and the second direction and are located on the source pads and are connected to the source pads, and at least two unit structures that are displaced from each other in the first direction are located on the same source pad; the gate structure extends along the second direction and connects the unit structures located on the same source pad; the plurality of drain structures are respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad. In the present invention, by providing source pads on the source lines, the source pads extend along the second direction and are located between adjacent source lines, the plurality of unit structures are arranged along the first direction and the second direction and are located on the source pads and are connected to the source pads, and at least two unit structures that are displaced from each other in the first direction are located on the same source pad, the gate structure connects the unit structures located on the same source pad, and each drain structure is connected to the unit structure connected to the corresponding source pad, it is realized that each drain structure is connected to the corresponding source pad through a plurality of unit structures, which can increase the driving current of the semiconductor device, thereby improving the electrical performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a top view of a semiconductor device provided by an embodiment of the present invention.

[0020] Figure 2 and Figure 3Schematic cross-sectional view of a semiconductor device provided by an embodiment of the present invention.

[0021] Figures 4 to 45 Schematic diagram of corresponding steps of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0022] Among them, the reference numerals are:

[0023] 10 - Substrate; 20 - Source line; 20a - Source pad; 31 - Second isolation material layer; 32 - First isolation material layer; 33 - Third isolation material layer; 34 - Fourth isolation material layer; 41 - Isolation oxide layer; 42 - Protective layer; 43 - Gate dielectric layer; 50 - Etch stop layer; 61 - First sacrificial layer; 62 - Through hole; 63 - Unit structure; 64 - Second sacrificial layer; 70 - Barrier layer; 71 - First opening; 72 - Second opening; 80 - Gate material layer; 82 - Gate structure; 90 - Drain structure; 100 - Sidewall. Detailed implementation manners

[0024] To make the objectives, advantages and features of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present invention. In addition, the structures shown in the accompanying drawings are often a part of the actual structure. In particular, the accompanying drawings need to show different emphases, and sometimes different scales are used.

[0025] As used in the present invention, the singular forms "a", "an" and "the" include plural objects, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0026] Figure 1 Top view of the semiconductor device provided for this embodiment, Figure 2 and Figure 3 Schematic cross-sectional view of the semiconductor device provided for this embodiment, Figure 2 is Figure 1 Cross-sectional view along the section line A1A2 in Figure 3 is Figure 1 Cross-sectional view along the section line B1B2 in Figure 1To show the source line and the gate structure, some structures are omitted, and the drain structure is set to be transparent. Please refer to Figures 1 to 3 , this embodiment provides a semiconductor device, including: a substrate 10, a plurality of source lines 20, a plurality of source pads 20a, a plurality of unit structures 63, a gate structure 82, and a plurality of drain structures 90. The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully depleted silicon-on-insulator substrate, etc., without limitation. In this embodiment, a dielectric layer (not shown in the figure) is further formed on the substrate 10, and an electrical connector is formed in the dielectric layer, and the electrical connector penetrates the dielectric layer and is electrically connected to the substrate 10 and the source line 20.

[0027] A plurality of source lines 20 are located on the substrate 10 (specifically on the dielectric layer), and the plurality of source lines 20 extend along a first direction D1 and are arranged at intervals along a second direction D2. A second isolation material layer 31 is filled between adjacent source lines 20. In this embodiment, the source line 20 may include a first source blocking layer, a source metal layer, a second source blocking layer, and a source semiconductor layer (not shown separately in the figure) stacked in sequence from bottom to top. The materials of the first source blocking layer and the second source blocking layer may respectively include TiN, the material of the source metal layer may include W, and the material of the source semiconductor layer may include polysilicon; the material of the second isolation material layer 31 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon carbonitrides, without limitation to the above materials.

[0028] Each source pad 20a is located on the corresponding source line 20 and extends along the second direction D2 and is located between adjacent source lines 20. In this embodiment, the shape of the source pad 20a includes a rhombus or a rectangle ( Figure 1 the source pad in Figure 1 is blocked by the gate structure 82 and the drain structure 90,

[0029] A plurality of unit structures 63 are arranged along a first direction D1 and a second direction D2 and are located on the source pad 20a and connected to the source pad 20a, and at least two unit structures 63 that are misaligned with each other in the first direction D1 are located on the same source pad 20a. In this embodiment, four unit structures 63 are located on one source pad 20a, and the four unit structures 63 are respectively located at the four ends of the source pad 20a (two ends along the first direction D1 and two ends along the second direction D2, that is, at the four included angles of the rhombus). The plurality of unit structures 63 are also arranged in an array (specifically, a staggered array distribution), and adjacent two columns of unit structures 63 are staggered along the second direction D2. In this embodiment, the material of the unit structure 63 may include polysilicon (with doped ions), and may also include one or a combination of metal silicide materials, ferroelectric materials, high-k dielectric materials, and indium gallium zinc oxide (IGZO), and is not limited to the above materials.

[0030] The gate structure 82 extends along the second direction D2 and is connected to the unit structures 63 located on the same source pad 20a; in this embodiment, the gate structure 82 includes an annular end 82a ( Figure 1 as shown by the rectangular virtual frame), the gate structure 82 includes a first portion 82b and a second portion 82c located on both sides of the unit structure 63 along the first direction D1 (the left side of the unit structure 63 in the figure may be the first portion 82b, and the right side of the unit structure 63 in the figure may be the second portion 82c), and the first portion 82b and the second portion 82c are connected by the annular end 82a. In this embodiment, the gate structure 82 may be a metal stack, such as TiN, W, and is not limited to the above materials.

[0031] Further, there are a gate dielectric layer 43 and a barrier layer 70 between the gate structure 82 and the unit structure 63. The gate dielectric layer 43 and the barrier layer 70 are sequentially arranged along the sidewall of the unit structure 63, and a part of the gate structure 82 is located on the gate dielectric layer 43 and the barrier layer 70. Furthermore, an etch stop layer 50 is further included. The etch stop layer 50 covers the isolation oxide layer 41 and a part of the source pad 20a. The gate dielectric layer 43 and the barrier layer 70 are located on the etch stop layer 50, and a part of the gate structure 82 is located on the etch stop layer 50. In this embodiment, the material of the gate dielectric layer 43 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. The barrier layer 70 may include titanium nitride, and the material of the etch stop layer 50 may include silicon carbide, and is not limited to the above materials.

[0032] Further, a first isolation material layer 32 and a third isolation material layer 33 are further included. The first isolation material layer 32 is filled between adjacent gate structures 82; the top of the gate structure 82 is lower than the top of the cell structure 63, and the second isolation material layer 33 is located on the gate structure 82, and the tops of the cell structure 63, the first isolation material layer 32, and the second isolation material layer 33 are flush. In this embodiment, the materials of the first isolation material layer 32 and the third isolation material layer 33 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon carbonitride oxides, and are not limited to the above materials.

[0033] A plurality of drain structures 90 are respectively located above the corresponding source pads 20a, and each drain structure 90 is connected to the cell structure 63 connected to the corresponding source pad 20a. In this embodiment, each drain structure 90 is connected to the corresponding source pad 20a through four cell structures 63. In this embodiment, the drain structure 90 includes a drain barrier layer and a drain metal layer (not shown in the figure) stacked in sequence from bottom to top. The material of the drain barrier layer may include TiN, and the material of the drain metal layer may include W, and is not limited to the above materials.

[0034] Further, a sidewall 100 and a fourth isolation material layer 34 are further included. The sidewall 100 covers the side surface of the drain structure 90; the fourth isolation material layer 34 is filled between adjacent drain structures 90; the materials of the sidewall 100 and the fourth isolation material layer 34 are different. The material of the sidewall 100 may include silicon nitride, and the material of the fourth isolation material layer 34 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon carbonitride oxides, and is not limited to the above materials.

[0035] In this embodiment, by providing the source pad 20a on the source line 20, the source pad 20a extends along the second direction D2 and is located between adjacent source lines 20. A plurality of cell structures 63 are arranged along the first direction D1 and the second direction D2 on the source pad 20a and are connected to the source pad 20a, and at least two cell structures 63 that are misaligned with each other in the first direction D1 are located on the same source pad 20a. The gate structure 82 is connected to the cell structures 63 located on the same source pad 20a, and each drain structure 90 is connected to the cell structure 63 connected to the corresponding source pad 20a, so that each drain structure 90 is connected to the corresponding source pad 20a through a plurality of cell structures 63, which can improve the drive current of the semiconductor device and thus improve the electrical performance of the semiconductor device.

[0036] This embodiment further provides a method for manufacturing a semiconductor device for manufacturing the above semiconductor device, including:

[0037] Step S1: Provide a substrate;

[0038] Step S2: Form a plurality of source lines on the substrate, extending along a first direction and spaced apart from each other along a second direction;

[0039] Step S3: Form a plurality of source pads, each source pad being located on a corresponding source line and extending along the second direction between adjacent source lines;

[0040] Step S4: Form a plurality of unit structures, arranged along the first direction and the second direction on the source pads and connected to the source pads, and at least two unit structures that are misaligned with each other in the first direction are located on the same source pad;

[0041] Step S5: Form a gate structure extending along the second direction and connecting the unit structures located on the same source pad;

[0042] Step S6: Form a plurality of drain structures respectively above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad.

[0043] Figures 4 to 45 Schematic diagrams of the corresponding steps of the manufacturing method of the semiconductor device provided in this embodiment. The following will be combined with Figures 4 to 45 to describe in detail the manufacturing method of the semiconductor device provided in this embodiment.

[0044] Please refer to Figures 4 to 6 , Figure 5 is Figure 4 a schematic cross-sectional view along the section line A1A2 in Figure 6 is Figure 4 a schematic cross-sectional view along the section line B1B2 in . Perform step S1: Provide a substrate 10. The substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully depleted silicon-on-insulator substrate, etc., without limitation. In this embodiment, a dielectric layer (not shown in the figure) is further formed on the substrate 10, and an electrical connector is formed in the dielectric layer, and the electrical connector penetrates the dielectric layer and is electrically connected to the substrate 10 and the source line 20.

[0045] Please refer to Figures 4 to 6 , perform step S2: Form a plurality of source lines 20 on the substrate 10. The plurality of source lines 20 extend along a first direction D1 and are arranged at intervals from each other along a second direction D2. A second isolation material layer 31 is filled between adjacent source lines 20. The materials of the source line 20 and the second isolation material layer 31 are as described above.

[0046] Please refer to Figures 4 to 6, perform step S3: Form a plurality of source pads 20a, each source pad 20a being located on a corresponding source line 20 and extending along the second direction D2 between adjacent source lines 20. The two end portions of the source pad 20a along the first direction D1 are located on the source line 20, and the two end portions of the source pad 20a along the second direction D2 both extend between adjacent source lines 20. The plurality of source pads 20a are arranged in an array (specifically, in a staggered array distribution), and two adjacent columns of source pads 20a are staggered along the second direction D2. The material of the source pad 20a is as described above.

[0047] Perform step S4: The steps of forming the unit structure include:

[0048] Please refer to Figures 7 to 9 , Figure 8 is Figure 7 the schematic cross-sectional view along the section line A1A2 in Figure 9 is Figure 7 the schematic cross-sectional view along the section line B1B2 in Figure 7 In

[0049] Please refer to Figures 10 to 12 , Figure 11 is Figure 10 the schematic cross-sectional view along the section line A1A2 in Figure 12 is Figure 10 the schematic cross-sectional view along the section line B1B2 in. Etch the first sacrificial layer 61 and the etch stop layer 50 to form a plurality of through holes 62, and the bottom of the through holes 62 exposes the source pad 20a (exposing at least a part of the top surface of the source pad 20a).

[0050] Please refer to Figures 13 to 15 , Figure 14 is Figure 13 the schematic cross-sectional view along the section line A1A2 in Figure 15 is Figure 13Schematic cross-sectional view along the section line B1B2. The forming unit structure 63 fills the via hole 62. A plurality of unit structures 63 are arranged along the first direction D1 and the second direction D2 and are located on the source pad 20a and connected to the source pad 20a. At least two unit structures 63 that are misaligned with each other in the first direction D1 are located on the same source pad 20a. In this embodiment, four unit structures 63 are located on one source pad 20a, and the four unit structures 63 are respectively located at the four ends of the source pad 20a. A plurality of unit structures 63 are also arranged in an array (specifically, a staggered array distribution), and adjacent two columns of unit structures 63 are staggered along the second direction D2; the material of the unit structure 63 is as described above.

[0051] Further, please refer to Figures 16 to 18 , Figure 17 is Figure 16 schematic cross-sectional view along the section line A1A2 in Figure 18 is Figure 16 schematic cross-sectional view along the section line B1B2 in

[0052] Further, please refer to Figures 19 to 21 , Figure 20 is Figure 19 schematic cross-sectional view along the section line A1A2 in Figure 21 is Figure 19 schematic cross-sectional view along the section line B1B2 in Figure 19 Some process layers are omitted in

[0053] Execute step S5: The steps of forming the gate structure include:

[0054] Please refer to Figures 22 to 24 , Figure 23 is Figure 22 schematic cross-sectional view along the section line A1A2 in Figure 24 is Figure 22 schematic cross-sectional view along the section line B1B2 in Figure 22The transparency of the second sacrificial layer 62 is set, and some process layers are omitted. The second sacrificial layer 62 is formed by a self-alignment process to at least cover the surface of the unit structure 63. Before forming the second sacrificial layer 62, a gate dielectric layer 43 and a barrier layer 70 are sequentially formed to cover the surface of the unit structure 63, and the gate dielectric layer 43, the barrier layer 70, and the second sacrificial layer 62 extend to cover the surface of the exposed etch stop layer 50 of the adjacent unit structure 63; the materials of the gate dielectric layer 43 and the barrier layer 70 are as described above, and the material of the second sacrificial layer 62 may include silicon nitride.

[0055] Please refer to Figures 25 to 27 , Figure 26 is Figure 25 the schematic cross-sectional view along the section line A1A2 in Figure 27 is Figure 25 the schematic cross-sectional view along the section line B1B2 in Figure 22 Some process layers are omitted in . Part of the gate dielectric layer 43, the barrier layer 70, and the second sacrificial layer 62 are etched to expose the etch stop layer 50 and the protective layer 42. After etching, the remaining gate dielectric layer 43, the barrier layer 70, and the second sacrificial layer 62 are disposed along the sidewalls of the unit structure 63.

[0056] Please refer to Figures 28 to 30 , Figure 29 is Figure 28 the schematic cross-sectional view along the section line A1A2 in Figure 30 is Figure 28 the schematic cross-sectional view along the section line B1B2 in . A first isolation material layer 32 is formed to fill between adjacent unit structures 63. Due to the presence of the protective layer 42, the top of the first isolation material layer 32 is flush with the top of the protective layer 42, and the material of the first isolation material layer 32 is as described above.

[0057] Please refer to Figures 31 to 33 , Figure 32 is Figure 31 the schematic cross-sectional view along the section line A1A2 in Figure 33 is Figure 31 the schematic cross-sectional view along the section line B1B2 in Figure 31 Some process layers are omitted in . The first isolation material layer 32 is etched to form a plurality of first openings 71 penetrating through the first isolation material layer 32, and the first openings 71 are located on both sides of the second sacrificial layer 62.

[0058] Please refer to Figures 34 to 36 , Figure 35 is Figure 34 the schematic cross-sectional view along the section line A1A2 in Figure 36 is Figure 34 the schematic cross-sectional view along the section line B1B2 in Figure 31Some process layers are omitted. The second sacrificial layer 62 is removed to form a second opening 72 in the area where the second sacrificial layer 62 is located, and the first opening 71 and the second opening 72 communicate with each other.

[0059] Please refer to Figures 37 to 39 , Figure 38 as Figure 37 the schematic cross-sectional view along the section line A1A2 in Figure 39 and Figure 37 the schematic cross-sectional view along the section line B1B2 in . A gate material layer 80 is formed to fill the first opening 71 and the second opening 72, and the top of the gate material layer 80 is flush with the top of the first isolation material layer 32.

[0060] Please refer to Figures 40 to 42 , Figure 41 as Figure 40 the schematic cross-sectional view along the section line A1A2 in Figure 42 and Figure 40 the schematic cross-sectional view along the section line B1B2 in . The gate material layer is etched so that the top of the gate material layer is lower than the top of the cell structure 63, and the remaining gate material layer serves as the gate structure 82. The gate structure 82 extends along the second direction D2 and connects to the cell structures 63 located on the same source pad 20a; the material of the gate structure 82 is as described above. Further, a third isolation material layer 33 is formed to cover the gate structure 82, the first isolation oxide layer 32, and the protection layer 42, and the material of the third isolation material layer 33 is as described above.

[0061] Please refer to Figures 43 to 45 , Figure 44 as Figure 43 the schematic cross-sectional view along the section line A1A2 in Figure 45 and Figure 43 the schematic cross-sectional view along the section line B1B2 in . Part of the third isolation material layer 33, part of the first isolation oxide layer 32, and the protection layer 42 are etched away to expose the top of the cell structure 63, and after etching, the tops of the third isolation material layer 33, the first isolation oxide layer 32, and the cell structure 63 are flush.

[0062] Please refer to Figures 1 to 3 , perform step S6: form a plurality of drain structures 90 respectively above the corresponding source pads 20a, and each drain structure 90 is connected to the cell structure 63 connected to the corresponding source pad 20a. In this embodiment, each drain structure 90 is connected to the corresponding source pad 20a through four cell structures 63, and the material of the drain structure 90 is as described above.

[0063] Furthermore, it further includes forming sidewalls 100 to cover the sides of the drain structures 90, and forming a fourth isolation material layer 34 to fill between adjacent drain structures 90; the materials of the sidewalls 100 and the fourth isolation material layer 34 are as described above.

[0064] In summary, in the semiconductor device provided by the present utility model, it includes: a substrate, a plurality of source lines, a plurality of source pads, a plurality of unit structures, a gate structure, and a plurality of drain structures. Among them, the plurality of source lines are located on the substrate, extend along a first direction and are arranged at intervals from each other along a second direction; each source pad is located on a corresponding source line and extends along the second direction between adjacent source lines; the plurality of unit structures are arranged along the first direction and the second direction on the source pads and are connected to the source pads, and at least two unit structures that are misaligned with each other in the first direction are located on the same source pad; the gate structure extends along the second direction and connects the unit structures located on the same source pad; the plurality of drain structures are respectively located above the corresponding source pads, and each drain structure is connected to the unit structure connected to the corresponding source pad. In the present utility model, by providing source pads on the source lines, the source pads extend along the second direction between adjacent source lines, the plurality of unit structures are arranged along the first direction and the second direction on the source pads and are connected to the source pads, and at least two unit structures that are misaligned with each other in the first direction are located on the same source pad, the gate structure connects the unit structures located on the same source pad, and each drain structure is connected to the unit structure connected to the corresponding source pad, it is realized that each drain structure is connected to the corresponding source pad through a plurality of unit structures, which can improve the drive current of the semiconductor device, thereby improving the electrical performance of the semiconductor device.

[0065] The above is only the preferred embodiment of the present utility model and does not impose any limiting effect on the present utility model. Any person skilled in the art, within the scope of the technical solution of the present utility model, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present utility model, all of which belong to the content within the scope of the technical solution of the present utility model and still fall within the protection scope of the present utility model.

Claims

1. A semiconductor device, characterized in that: include: substrate; A plurality of source lines are located on the substrate, extending along a first direction and arranged at intervals from each other along a second direction; A plurality of source pads, each of the source pads is located on a corresponding source line and extends along the second direction and is located between adjacent source lines; A plurality of unit structures are arranged on the source pad along the first direction and the second direction and connected to the source pad, and at least two of the unit structures that are offset from each other in the first direction are located on the same source pad; A gate structure extending along the second direction and connecting the unit structures located on the same source pad; A plurality of drain structures are respectively located above the corresponding source pads, and each of the drain structures is connected to the unit structure connected to the corresponding source pad.

2. The semiconductor device according to claim 1, wherein Both ends of the source pad along the first direction are located on the source line, and both ends of the source pad along the second direction extend between adjacent source lines.

3. The semiconductor device according to claim 2, wherein: The source pad has a rhombus or a rectangle shape.

4. The semiconductor device according to claim 1, wherein A plurality of the source pads are arranged in an array, and the source pads in two adjacent rows are staggered along the second direction.

5. The semiconductor device according to claim 2, wherein: The four unit structures are located on one source pad and are respectively located at four ends of the source pad.

6. The semiconductor device according to claim 1, wherein: The gate structure includes a ring-shaped end.

7. The semiconductor device according to claim 6, wherein: The gate structure includes a first portion and a second portion located at two sides of the unit structure along the first direction, and the first portion and the second portion are connected through the annular end.

8. The semiconductor device according to claim 1, wherein A gate dielectric layer and a barrier layer are provided between the gate structure and the unit structure, and a first isolation material layer is filled between a plurality of the gate structures.

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