Low-capacitance bidirectional ESD protection device

Abstract

The utility model discloses a low-capacitance bidirectional ESD (Electro-Static Discharge) protection device, which comprises a P-type material serving as a substrate; the two N-type diffusion regions are symmetrically arranged on the front surface of the P-type material; the N + doped region and the P + doped region are arranged in the N-type diffusion region; the P-type doped region is positioned between the two N-type diffusion regions; the insulating dielectric layer is positioned above the N + doped region and the P + doped region; and the surface metal layer is positioned above the N + doped region, the P + doped region and the insulating dielectric layer. According to the utility model, through structural improvement, the capacitance cj of the device can be effectively reduced under the condition that the same discharge capability is ensured. By adopting the W-type cell arrangement layout, the normalized cell size can be reduced, the area adopted by the same current discharge capability is smaller, the device cost is effectively reduced, the surface cell length can be effectively increased, the discharge current density in unit area is improved, and the requirements of extremely low capacitance, high reliability and the like required by high-speed transmission can be met.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuit protection devices, and more specifically, to a bidirectional ESD protection device with low capacitance. Background Art

[0002] Electrostatic discharge (ESD) phenomenon is the main cause of the failure of integrated circuit products. Integrated circuit products are extremely vulnerable to electrostatic pulses during their production, manufacturing, assembly, and use processes, resulting in damage to the internal structure of the products and reduced reliability. Therefore, researching high-performance and high-reliability ESD protection devices is of great significance for improving the yield and reliability of integrated circuits. The design of ESD protection devices usually needs to consider three basic parameters: voltage, capacitance, and discharge capacity. In ultra-high-speed interface protection, other requirements such as extremely low capacitance and high reliability need to be achieved while ensuring the discharge capacity.

[0003] Nowadays, the era of the combination of artificial intelligence and the Internet of Things has begun, and smart homes are playing an increasingly important role in life. With the continuous development of technology, the chips required for the Internet of Things are further developed towards higher integration and lower power consumption, which also requires the line width of its manufacturing process to be further reduced. The strict requirements such as thin line width and ultra-low power consumption also make the chips more vulnerable and sensitive when suffering from the electrostatic discharge effect, resulting in more and more strict requirements for ESD protection devices.

[0004] Devices commonly used for ESD protection include diodes, BJTs (bipolar junction transistors), SCRs (silicon controlled rectifiers), etc. The BJT structure obtains a shallow snapback characteristic due to the introduction of the injection modulation effect. The SCR structure realizes a deep snapback characteristic through the positive feedback mechanism of PNPN. Therefore, in terms of the residual voltage parameter, the SCR structure is the lowest, the BJT structure is the second, and the diode structure is the highest. Since the deep snapback voltage of the SCR is about 1.5V, which is significantly lower than common power supply voltages such as 3.3V and 5V, the SCR structure will generate latch-up in some applications and cannot return to the blocking state after the ESD pulse discharge, limiting the application scenarios of SCR structure devices. In ultra-high-speed interface applications, due to the reduction of the working voltage, the demand for ESD products with 1.0V, 1.2V, 1.8V, 2.5V, and 3.3V has increased rapidly, and the corresponding SCR structure ESD protection devices are also increasingly applied to ultra-high-speed interfaces such as USB3.0, USB4.0, and Thunderbolt. For the SCR structure ESD protection device applied in high-speed data interfaces, a lateral SCR structure is generally adopted. This is because the lateral SCR can conveniently adjust parameters such as the structure and junction depth, and can achieve better performance.

[0005] However, there are no other better means to improve the structure to obtain lower capacitance and stronger reliability, and it is impossible to meet the requirements of extremely low capacitance and high reliability for high-speed transmission. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the purpose of the present utility model is to provide a bidirectional ESD protection device with low capacitance to solve one or more of the above problems.

[0007] To achieve the above purpose, the present utility model provides the following technical solutions:

[0008] A bidirectional ESD protection device with low capacitance includes

[0009] P-type material, which serves as a substrate;

[0010] Two N-type diffusion regions, which are symmetrically arranged on the front surface of the P-type material;

[0011] N+-doped region and P+-doped region, which are arranged in the N-type diffusion region;

[0012] P-type doped region, which is arranged on the front surface of the P-type material and is located between the two N-type diffusion regions;

[0013] Insulating dielectric layer, which is arranged on the front surface of the P-type material and is located above the N+-doped region and the P+-doped region;

[0014] Surface metal layer, which is arranged on the front surface of the N-type diffusion region and is located above the N+-doped region, the P+-doped region, and the insulating dielectric layer.

[0015] Further, the N+-doped region is arranged on the outside, and the P+-doped region is arranged on the inside.

[0016] Further, a shallow isolation groove is provided between the insulating dielectric layer and the P-type doped region, and the shallow isolation groove is located between the two N-type diffusion regions.

[0017] Further, the shallow isolation groove overlaps with both the N+-doped region and the P+-doped region.

[0018] Further, the cross-section of the P+-doped region is one of a rhombus, a square, and a circle.

[0019] Further, the overall protection device has a W-shaped cell arrangement structure.

[0020] In summary, the utility model has the following beneficial effects: Through structural improvement, the device capacitance is positively correlated with the area of the N-type diffusion region. The total area of the P+ doping region decreases and its area cannot be infinitely reduced, which will affect the ESD discharge ability. On the premise of ensuring the same discharge ability, the device self-capacitance cj can be effectively reduced. By adopting the W-type cell arrangement layout, the normalized cell size can be reduced, and the area used for the same current discharge ability is smaller, effectively reducing the device cost. It can also effectively increase the surface cell length, improve the discharge current density per unit area, better protect the device, with lower capacitance and better reliability, and can meet the requirements of extremely low capacitance and high reliability for high-speed transmission. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 It is a layout structure schematic diagram of an implementation manner provided by the utility model;

[0022] Figure 2 is Figure 1 a schematic diagram of the structure of the AA' section in

[0023] Figure 3 is Figure 1 a schematic diagram of the structure of the BB' section in

[0024] Figure 4 It is an I-V characteristic curve and an equivalent circuit diagram of an implementation manner provided by the utility model;

[0025] Figure 5 It is a schematic diagram of the structure of the existing unidirectional SCR type ESD protection device provided by the utility model.

[0026] In the figure: 101, P-type material; 102, N-type diffusion region; 103, N+ doping region; 104, P+ doping region; 105, P-type doping region; 106, shallow isolation groove; 107, insulating dielectric layer; 108, surface metal layer; 1101, P-type single crystal material; 1102, N diffusion region; 1103, N+ diffusion region; 1104, P+ diffusion region; 1105, surface passivation layer; 1106, cathode metal layer; 1107, anode metal layer. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] Example:

[0028] The following will Figures 1-5 further describe the utility model in detail with reference to the attached drawings.

[0029] A low-capacitance bidirectional ESD protection device, the whole device is a W-type cell arrangement structure, as Figures 1-3As shown in the figure, it includes a P-type material 101 as a substrate, with a crystal orientation of 100. After implantation and diffusion on the front side of the P-type material 101, two symmetric N-type diffusion regions 102 are formed. Two highly doped regions, namely an N+ doped region 103 and a P+ doped region 104, are formed by high-energy particle implantation within the N-type diffusion region 102. Among them, the N+ doped region 103 is located on the outer side inside the N-type diffusion region 102, and the P+ doped region 104 is located on the inner side inside the N-type diffusion region 102. A P-type doped region 105 serving as a trigger region is formed by multiple high-energy implantations on the front side of the P-type material 101, and the P-type doped region 105 is located between the two N-type diffusion regions 102. An insulating dielectric layer 107 is formed on the front side of the P-type material 101, and the insulating dielectric layer 107 is located above the N-type diffusion region 102, the N+ doped region 103, and the P+ doped region 104. Two symmetric surface metal layers 108 are provided on the front side of the N-type diffusion region 102, and are located above the N+ doped region 103, the P+ doped region 104, and the insulating dielectric layer 107. A shallow isolation groove 106 is provided between the insulating dielectric layer 107 and the P-type doped region 105. The shallow isolation groove 106 is located between the two N-type diffusion regions 102 and below the surface metal layer 108, and the shallow isolation groove 106 overlaps with both the N+ doped region 103 and the P+ doped region 104.

[0030] The dielectric layer in the shallow isolation groove 106 and the insulating dielectric layer 107 can be insulating dielectrics such as silicon dioxide, USG, TEOS, PSG, BPSG, or other high-K or low-K dielectrics. For the proportion and arrangement shape of the entire cross-section, the purpose of reducing the cj capacitance can be achieved, and the cross-sectional shape of the P+ doped region 104 can be a rhombus, a square, a circle, or other shapes.

[0031] As Figure 4 shown in the figure, when the two surface metal layers 108 on the front side are in a symmetric structure, with the left surface metal layer 108 at a high voltage and the right surface metal layer 108 at a low potential, the overall characteristics show the deep snapback characteristics of an SCR. When the left surface metal layer 108 is at a low potential and the right surface metal layer 108 is at a low potential, the overall characteristics also show the deep snapback characteristics of an SCR. The voltage is determined by the PN formed by the P-type doped region 105 and the N-type diffusion region. When the voltage reaches the breakdown voltage of this PN, the rapidly increasing current flows through the NPN region composed of the N+ doped region 103 - N-type diffusion region 102 - P-type material 101 - N-type diffusion region 102 - N+ doped region 103, and rapidly increases under the current amplification effect of the triode, causing the SCR to turn on.

[0032] The structure of the existing unidirectional SCR protection device is as Figure 5As shown, an N diffusion region 1102, an N+ diffusion region 1103, and a P+ diffusion region 1104 are formed on a P-type single crystal material 1101. The surface passivation layer 1105 plays a role in dielectric isolation. The cathode metal layer 1106 and the anode metal layer 1107 serve as the cathode and anode during protection respectively. This protection device itself has a lateral PNPN structure with a two-way short-circuit current extraction. There are base region series resistances on both sides of the four-layer structure of the PNPN. When the cathode metal layer 1106 is connected to a high potential and the anode metal layer 1107 is connected to a low potential, after the device is turned on, the current passes through the P+ diffusion region 1104, the N diffusion region 1102, the P-type single crystal material 1101, and the N+ diffusion region 1103 in the circuit, showing a deep reverse conduction characteristic. When the cathode metal layer 1106 is connected to a low potential and the anode metal layer 1107 is connected to a high potential, first, the diode composed of the P+ diffusion region 1104, the P-type single crystal material 1101, the N diffusion region 1102, and the N+ diffusion region 1103 conducts forward.

[0033] In view of the deficiencies of the existing structure, this application uses a layout of the traditional lateral SCR structure to achieve a two-way function with a single lateral device, which can greatly reduce the area required for the device and improve the current discharge capacity per unit area. Through the design of the position area of the transmitter active region in the layout, the AA’ and BB’ cross-sectional structures are combined with the W-type cell arrangement structure in proportion, further reducing the area of the N-type diffusion region 102 in some active regions, thereby reducing the junction capacitance of the device. Finally, under the condition of greatly reducing the chip area, a higher current discharge capacity is obtained, and the capacitance is reduced to a certain extent.

[0034] The two-way structure in this application does not distinguish between the forward and reverse directions, and the two directions are completely symmetrical. When a voltage is applied to one side of the five-layer PNPNP structure with short circuits on both sides, the voltage is first applied to the central NPN structure, and the turn-on current of the PNPN is provided by the NPN. Since the NPN has no base region short-circuit structure, the NPN will turn on quickly at a relatively small current. When the SCR is applied to a working voltage not higher than 3.3V, it can be beneficial to the rapid discharge of current, thereby achieving the purpose of timely protecting the system.

[0035] It should be noted that this specific embodiment is only an explanation of the present invention, and it is not a limitation of the present invention. Those skilled in the art can make modifications to this embodiment without creative contributions according to needs after reading this specification, but as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. Low capacitance bidirectional ESD protection device, characterized by: include P-type material (101), which serves as a substrate; Two N-type diffusion regions (102) are symmetrically arranged on the front side of the P-type material (101); An N+ doping region (103) and a P+ doping region (104), which are arranged in the N-type diffusion region (102); A P-type doped region (105) disposed on the front side of the P-type material (101) and located between the two N-type diffusion regions (102); An insulating dielectric layer (107) is provided on the front side of the P-type material (101) and is located above the N+ doped region (103) and the P+ doped region (104); A surface metal layer (108) is provided on the front side of the N-type diffusion region (102) and is located above the N+ doping region (103), the P+ doping region (104), and the insulating dielectric layer (107).

2. The low capacitance bidirectional ESD protection device according to claim 1, characterized in that: The N+ doping region (103) is arranged outside, and the P+ doping region (104) is arranged inside.

3. The low capacitance bidirectional ESD protection device according to claim 1, characterized in that: A shallow isolation trench (106) is provided between the insulating dielectric layer (107) and the P-type doping region (105), and the shallow isolation trench (106) is located between the two N-type diffusion regions (102).

4. The low capacitance bidirectional ESD protection device according to claim 3, characterized in that: The shallow isolation trench (106) overlaps with the N+ doping region (103) and the P+ doping region (104).

5. The low capacitance bidirectional ESD protection device according to claim 1, characterized in that: The cross section of the P+ doped region (104) is one of a diamond, a square and a circle.

6. The low capacitance bidirectional ESD protection device according to claim 1, characterized in that: The protection device as a whole is a W-shaped cell arrangement structure.

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