Semiconductor device

Abstract

Various embodiments of the utility model relate to a semiconductor device, the semiconductor device comprises a plurality of photodiode doped regions formed in a substrate and a deep trench isolation (DTI) structure formed in the substrate, the DTI structure separates the photodiode doped regions, and the DTI structure comprises a first filling material defining an air gap therein. The first filling material comprises a top, a side wall and a bottom. The semiconductor device also includes a first isolation layer surrounding and contacting the top, sidewalls, and bottom of the first fill material.

Description

Technical Field

[0001] An embodiment of the present utility model relates to a semiconductor device. Background Art

[0002] Integrated circuits (ICs) with image sensors are widely used in modern electronic devices. In recent years, complementary metal oxide semiconductor (CMOS) image sensors have begun to be widely used due to their low power consumption, small size, fast data processing speed, and low manufacturing cost. Deep trench isolation (DTI) structures are used to provide electrical and / or optical isolation between high-voltage devices and image sensors. As the image pixel size and the pitch between adjacent image pixels continue to shrink, it is challenging to gap-fill the material layer defectlessly in the DTI structure. Summary of the Utility Model

[0003] One aspect of the present utility model provides a semiconductor device. The semiconductor device includes a plurality of photodiode doping regions formed in a substrate and a deep trench isolation (DTI) structure formed in the substrate, wherein the DTI structure separates the plurality of photodiode doping regions, and the DTI structure includes a first filling material in which an air gap is defined, and the first filling material includes a top, sidewalls, and a bottom. The DTI structure further includes a first isolation layer that surrounds the top, sidewalls, and bottom of the first filling material, and the first isolation layer is in contact with the top, sidewalls, and bottom of the first filling material.

[0004] Another aspect of the present utility model provides a semiconductor device. The semiconductor device includes a deep trench isolation (DTI) structure extending to a certain depth into a semiconductor substrate, wherein the DTI structure separates photodiode doping regions, and the DTI structure includes a filling material in which an air gap is defined and a high-K dielectric layer surrounding the sidewalls and the bottom of the filling material. The semiconductor device further includes an isolation structure that includes a first isolation layer and a second isolation layer, the first isolation layer is disposed between the high-K dielectric layer and the sidewalls and the bottom of the filling material, and the first isolation layer is in contact with the high-K dielectric layer and the sidewalls and the bottom of the filling material. The second isolation layer is disposed on the first isolation layer, and a portion of the second isolation layer extends from the top of the filling material and is in contact with the top of the filling material.

[0005] Another aspect of the present utility model provides a method for forming a semiconductor device. The method includes forming a plurality of photodiode doping regions in and on a front side of a substrate. The method further includes forming deep isolation trenches from a back side of the substrate, wherein the deep isolation trenches separate the plurality of photodiode doping regions. The method further includes depositing a hole accumulation layer on sidewalls of the deep isolation trenches. The method further includes depositing a first isolation layer on the hole accumulation layer, wherein the first isolation layer has a first thickness. The method further includes depositing a first filling material on the first isolation layer in the deep isolation trenches, wherein the first filling material surrounds air gaps. The method further includes depositing a second isolation layer on exposed surfaces of the first isolation layer and the first filling material, wherein a second thickness of the second isolation layer is greater than the first thickness.

[0006] To make the above features and advantages of the present utility model more obvious and understandable, specific embodiments are hereinafter given and described in detail in conjunction with the accompanying drawings as follows. Description of the Drawings

[0007] Figure 1 is a flowchart of a method for manufacturing a semiconductor device including a DTI structure according to an embodiment of the present disclosure

[0008] Figures 2 to 14 Schematically illustrates a semiconductor device Figure 1 at various manufacturing stages according to the method of.

[0009] Figure 8A Illustrates an enlarged view of a portion of a semiconductor device Figure 8 according to some embodiments of.

[0010] Figure 10A Illustrates an enlarged view of a portion of a semiconductor device Figure 10 according to some embodiments of.

[0011] Figure 11A Illustrates an enlarged view of a portion of a semiconductor device Figure 11 according to some embodiments of.

[0012] Figure 12A Illustrates an enlarged view of a portion of a semiconductor device Figure 12 according to some embodiments of. Detailed Description of the Embodiments

[0013] The present utility model content provides many different embodiments or examples for implementing different components of the provided target object. Specific examples of components and arrangements are set forth below to simplify the present utility model. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming the first component on or over the second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component may not be in direct contact. Additionally, the present disclosure may reuse reference numerals and / or letters in various examples. Such reuse is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0014] In addition, for ease of illustration, spatially relative terms such as "beneath", "below", "lower", "above", "over", "top", "upper", etc. may be used herein to describe the relationship of one component or part shown in the figures to another component or part. In addition to the orientation depicted in the figures, the spatially relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and likewise, the spatially relative descriptive terms used herein may be interpreted accordingly.

[0015] According to various embodiments, a deep trench isolation (DTI) structure in a semiconductor substrate and a method of forming the same are provided. Intermediate stages of forming the DTI structure are illustrated according to some embodiments. The DTI structure can be used in a backside illumination (BSI) complementary metal-oxide-semiconductor (CMOS) image sensor, a front side illumination (FSI) CMOS image sensor, a logic device, and any suitable device using deep trench isolation. In an image sensing device, the DTI structure can be formed on the front side of a semiconductor substrate of a transistor having pixel components or on the back side of the semiconductor substrate. The backside DTI structure is fabricated after a metallization process. The various embodiments of the present disclosure are suitable for gap filling a high aspect ratio (e.g., 1:3 to 1:10) backside DTI structure having a narrow top critical dimension (CD) and a bow-shaped profile. Details of variations of the embodiments will be discussed below.

[0016] Figure 1FIG. 1000 is a flow chart of a method 1000 for manufacturing a semiconductor device 100 including a BDTI structure in accordance with an embodiment of the present disclosure. Figures 2 to 14 FIG. 1 schematically illustrates the semiconductor device 100 at various manufacturing stages in accordance with the method 1000. It should be understood that additional steps may be provided before, during, and / or after the method 1000, and some of the described steps may be replaced, eliminated, and / or moved for additional embodiments of the method 1000.

[0017] At operation 1002 of the method 1000, a substrate 102' is provided for the image sensing die 134, as Figure 2 shown. The substrate 102' may include an elemental semiconductor such as germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; an alloy semiconductor including silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP); or a combination thereof. Other substrates may also be used, such as a multi-layer substrate or a gradient substrate. The substrate 102' may include any type of semiconductor body (e.g., a semiconductor wafer or one or more dies on a wafer) and any other type of semiconductor and / or an epitaxial layer formed on the semiconductor and / or an epitaxial layer otherwise associated with the semiconductor. For example, a pixel array deep p-type well 131 may be formed on the carrier substrate 102. The carrier substrate 102 may be a highly doped p-type base layer or consist of a highly doped p-type base layer. A pixel array deep n-type well 130 may be formed on the pixel array deep p-type well 131. The pixel array deep n-type well 130 and the pixel array deep p-type well 131 may be formed by an implantation process. In some embodiments, a photodiode doping layer 128 is formed as an upper portion of the substrate 102'. The photodiode doping layer 128 may be formed by a p-type epitaxial process. In some embodiments, a plurality of shallow trench isolation (STI) structures 117 are formed at the boundary from the front side 122 of the image sensing die 134 to a position within the photodiode doping layer 128 and / or between adjacent pixel regions 103a, 103b. One or more STI structures 117 may be formed by selectively etching the front side 122 of the image sensing die 134 to form a shallow trench and then forming an oxide within the shallow trench.

[0018] After forming the STI structure 117, a doping material is implanted into the photodiode doping layer 128 to form a plurality of photodiode doping regions 104. Although not shown, each photodiode doping region 104 corresponds to a pixel component and serves as a light sensing region in the pixel component. The photodiode doping regions 104 can be formed by implanting an n-type doping material into the pixel regions 103a and 103b, respectively. The photodiode doping layer 128 can be selectively implanted according to a patterned mask layer (not shown), and the patterned mask layer can be any suitable photoresist. In some embodiments, the plurality of photodiode doping regions 104 can include an n-type dopant having a concentration in the range between about 1E15 atoms / cm 3 and about 1E20 atoms / cm 3 .

[0019] At operation 1004 of method 1000, a transfer gate 132 is formed over the front side 122 of the image sensing die 134, as Figure 3 shown. The transfer gate 132 can be formed by depositing a gate dielectric layer and a gate electrode layer over the substrate 102'. The gate dielectric layer and the gate electrode layer are then patterned to form the gate dielectric layer 133 and the gate electrode layer 134. In some embodiments, an implantation process is performed within the front side 122 of the image sensing die 134 to form a floating diffusion well 136 along one side of the transfer gate 132 or along opposite sides of a pair of transfer gates 132.

[0020] After that, a metallization stack 108 is formed over the front side 122 of the image sensing die 134. The metallization stack 108 can be formed by forming an ILD layer 106 over the front side 122 of the image sensing die 134, and the ILD layer 106 includes one or more ILD materials. The ILD layer 106 is then etched to form vias and / or trenches. The vias and / or trenches are then filled with a conductive material to form a plurality of metal interconnect vias 110 and metal lines 112. The ILD layer 106 can include a low-k material, such as SiO x , SiO x C y H z , SiOCN, SiON, or SiO x C y , where x, y, and z are integers or non-integers, and the ILD layer 106 can be deposited by any suitable deposition technique (such as CVD, PECVD, PVD, etc.). A plurality of metal interconnect layers can be formed using a deposition process and / or an electroplating process (such as electroplating, electroless plating, etc.). The plurality of metal interconnect layers can include, for example, tungsten, copper, and aluminum copper.

[0021] At operation 1006 of method 1000, the image sensing die 134 can then be bonded to one or more other dies, asFigure 4 as shown. For example, the image sensing die 134 can be bonded to the logic die 140, which can include logic devices 142 disposed on a logic substrate 141. The logic die 140 can also include a metallization stack 144 disposed within an ILD layer 146 that covers the logic devices 142. The image sensing die 134 and the logic die 140 can be bonded face-to-face, face-to-back, or back-to-back. As an example, Figure 4 a bonding structure in which a pair of intermediate bonding dielectric layers 138, 148 (dielectric-to-dielectric bonding) and bonding pads 150, 152 (metal-to-metal bonding) are disposed between the image sensing die 134 and the logic die 140 and bond the metallization stacks 108, 144 through fusion or eutectic bonding structures respectively. For example, an annealing process can be performed after the hybrid bonding process, and the annealing process can be carried out at a temperature range between about 250 degrees Celsius and about 450 degrees Celsius for about 0.5 hours to about 4 hours.

[0022] At operation 1008 of method 1000, a thinning process is performed on the back side 124 (opposite to the front side 122) of the image sensing die 134, as Figure 5 shown. The thinning process may partially or completely remove the carrier substrate 102 ( Figure 4 ). The thinning or removal of the carrier substrate 102 allows radiation to pass through the back side 124 of the image sensing die 134 and reach the photodiode doping region 104. In some embodiments, the image sensing die 134 is further thinned to expose a portion of the photodiode doping region 104 such that radiation can more easily reach the photodiode. The substrate 102' can be thinned by etching the back side of the image sensing die 134. As an alternative, the substrate 102' can be thinned by mechanically grinding the back side 124 of the image sensing die 134. In some embodiments, the substrate 102' can be ground to a first thickness first, and then a wet etching process can be applied to further reduce the thickness of the substrate 102' from the first thickness to a second thickness. After the thinning process, radiation can easily pass through the back side 124 of the image sensing die 134 and reach the photodiode doping region 104.

[0023] At operation 1010 of method 1000, the substrate 102' is selectively etched to form deep isolation trenches 135 in the back side 124 of the image sensing die 134, as Figure 6As shown. The deep isolation trench 135 laterally separates the photodiode doping regions 104. When viewed from the top, the deep isolation trenches 135 form a grid and surround a plurality of photodiode doping regions 104. In some embodiments, the substrate 102' can be etched by forming a mask layer on the back side of the image sensing die 134 and then performing an anisotropic etching process. Then, the substrate 102' is exposed to an etchant in the regions not covered by the mask layer. The etchant removes a portion of the substrate 102' to form deep isolation trenches 135 that extend into the substrate 102' (e.g., into the photodiode doping layer 128). In some alternative embodiments, some of the deep isolation trenches 135 can extend through the thickness of the substrate 102' to provide complete coverage of the photodiode doping regions 104. The mask layer can include photoresist or nitride (e.g., SiN) patterned using a lithography process. In various embodiments, the etchant can include a dry etchant having an etching chemistry (including fluorine-containing substances (e.g., CF4, CHF3, C4F8, etc.)) or a wet etchant (e.g., hydrofluoric acid (HF) or tetramethylammonium hydroxide (TMAH)). In the case of using a dry etching process, the plasma can be formed by inductively coupled plasma (ICP), transformer coupled plasma (TCP), electron cyclotron resonance (ECR), reactive ion etch (RIE), etc. Each deep isolation trench 135 can have a depth range of between about 1.5 μm and about 5 μm (measured from the back side 124 of the image sensing die 134) and a lateral dimension in the range of about 0.1 μm to about 1 μm. If the depth of the deep isolation trench 135 is less than about 1.5 μm, the deep isolation trench 135 may not properly isolate the photodiode doping regions 104. On the other hand, if the depth of the deep isolation trench 135 is greater than about 5 μm, the deep isolation trench 135 may damage the STI structure 117 and / or the floating diffusion well 136.

[0024] The profile of the deep isolation trench 135 can be achieved by changing the bias power applied to the semiconductor device 100, the thickness / type of the mask layer, the gas type, the chamber pressure, etc. In various embodiments, an anisotropic etching process is performed such that the deep isolation trench 135 has a first dimension D1 at or near the opening of the deep isolation trench 135, a second dimension D2 at the turning point 137 far from the opening, and a third dimension D3 at the bottom of the deep isolation trench 135. In some embodiments, the second dimension D2 is greater than the first dimension D1, and the first dimension D1 is greater than the third dimension D3. In some embodiments, the first dimension D1 is greater than the second dimension D2, and the second dimension D2 is greater than the third dimension D3. The resulting deep isolation trench 135 may have a narrow top critical dimension (CD) and a bow-tip (or undercut) profile at the upper portion of the deep isolation trench 135, and a tapered profile at the lower portion of the deep isolation trench 135.

[0025] In Figure 6 In one exemplary embodiment shown, the diameter of the upper portion of the sidewall 135uw (e.g., the portion above the turning point 137) gradually increases in a direction away from the backside 124, and the diameter of the lower portion of the sidewall 135lw (e.g., the portion below the turning point 137) gradually decreases in a direction away from the backside 124. The angle "α" between the sidewall 135uw and the sidewall 135lw can be greater than about 140 degrees, such as from about 160 degrees to about 175 degrees. In some embodiments, an anisotropic etching process is performed such that the sidewalls 135uw, 135lw of the deep isolation trench 135 are straight and perpendicular, i.e., the sidewalls 135uw, 135lw are substantially perpendicular to the backside 124 (i.e., there is no turning point). In some embodiments, the deep isolation trench 135 may also be slightly tapered, so that the sidewalls 135uw, 135lw of the deep isolation trench 135 are slightly inclined with respect to the backside 124.

[0026] At operation 1012 of method 1000, a hole accumulation layer 154 is formed on the exposed surface of the semiconductor device 100, as Figure 7As shown. In one embodiment, the hole-accumulation layer 154 is deposited on the sidewalls 135uw, 135lw and the bottom 135b of the deep isolation trench 135. The hole-accumulation layer 154 has a material with a relatively high bandgap (e.g., about 5.5 eV or greater). The hole-accumulation layer 154 may include, but is not limited to, aluminum oxide (Al2O3), hafnium oxide (HfO2), magnesium oxide (MgO), calcium oxide (CaO), zirconium oxide (ZrO2), yttrium oxide (Y2O3), zirconium silicon oxide (ZrSiO4), hafnium silicon oxide (HfSiO4), combinations thereof, etc., and may be deposited using a conformal deposition method, such as atomic layer deposition (ALD), plasma-enhanced atomic layer deposition (PEALD), chemical vapor deposition (CVD), or similar deposition methods. In some embodiments, the hole-accumulation layer 154 may have a thickness in the range between about 50 angstroms and about 200 angstroms. In some embodiments, the hole-accumulation layer 154 is a multi-layer structure using two or more layers of the materials discussed herein. In such a case, an adhesion layer, such as an oxide layer, may be formed between these layers.

[0027] Using a material with a relatively high bandgap allows the hole-accumulation layer 154 to cause hole accumulation within the deep isolation trench 135, thereby providing improved electrical isolation between the photodiode doping regions 104. The hole-accumulation layer 154 may also act as a passivation layer to reduce pixel degradation that may occur due to damage to the substrate 102' caused by etching the deep isolation trench 135. In some embodiments, the hole-accumulation layer 154 is formed of a high-K material, which may advantageously have optical reflection characteristics to provide optical isolation between the photodiode doping regions 104.

[0028] At operation 1014 of method 1000, a first isolation layer 156 is deposited on the hole-accumulation layer 154, as Figure 8 shown. The first isolation layer 156 is configured to enhance the electrical isolation between the photodiode doping regions 104. The material of the first isolation layer 156 is selected to increase the absorption of radiation from the photodiode doping regions 104, thereby preventing unnecessary optical reflection back to the photodiode doping regions 104. Suitable materials for the first isolation layer 156 may include, but are not limited to, tantalum oxide (Ta2O5), titanium oxide (TiO2), lutetium oxide (Lu2O3), lanthanum oxide (La2O3), hafnium aluminum oxide (HfAlO), any suitable high-K material, etc., or a composite layer including more than one layer of these layers. As another option, the first isolation layer 156 may use the material for the hole-accumulation layer 154. In this case, the first isolation layer 156 and the hole-accumulation layer 154 may use materials with different chemical properties. Any suitable deposition technique may be used to deposit the first isolation layer 156, such as physical vapor deposition (PVD), ALD, etc. In one embodiment, the first isolation layer 156 is Ta2O5 deposited by PVD.

[0029] The first isolation layer 156 is a continuous layer having a thickness varying in the range of from about 1 μm to about 120 μm. In various embodiments, the first isolation layer 156 is deposited such that the first isolation layer 156 outside the deep isolation trench 135 has a first thickness T1, and the first isolation layer 156 inside the deep isolation trench 135 has a thickness that gradually decreases in a direction away from the opening 135o of the deep isolation trench 135, as Figure 8A shown. That is, the first isolation layer 156 inside the deep isolation trench 135 has a second thickness T2 near the opening 135o, a third thickness T3 less than the second thickness T2 at or near the turning point 137, a fourth thickness T4 less than the third thickness T3 near the bottom of the deep isolation trench 135, and a fifth thickness T5 less than the fourth thickness T4 at the bottom of the deep isolation trench 135. After depositing the first isolation layer 156, the deep isolation trench 135 has a dimension D4 at the opening 135o, a dimension D5 at and / or near the turning point 137, and a dimension D6 at the bottom of the deep isolation trench 135, where the dimension D5 is greater than the dimension D4, and the dimension D4 is greater than the dimension D6.

[0030] In some embodiments, the first thickness T1 may be substantially the same as the second thickness T2. In some embodiments, the first thickness T1 may be slightly less than the second thickness T2.

[0031] If the thickness of the first isolation layer 156 is less than about 1 μm, the first isolation layer 156 may not provide sufficient electrical isolation between the photodiode doping regions 104. A thickness greater than about 120 μm may prematurely pinch off the opening 135o and not provide additional benefits. In some embodiments, the ratio of the thickness of the first isolation layer 156 to the thickness of the hole accumulation layer 154 is in the range between 0.01 and 1.0.

[0032] At operation 1016 of method 1000, a first fill material 158 is deposited on the first isolation layer 156 and fills the deep isolation trench 135 ( Figure 8 ), as Figure 9As shown. Due to the profile of the deep isolation trench 135, an air gap or slit 157 is formed within the first fill material 158 in the deep isolation trench 135 after the deposition of the first fill material 158. The air gap or slit 157 may have a height that is about 65% to about 90% of the height of the deep isolation trench 135. The height of the top of the air gap or slit 157 is lower than the dorsal side 124 of the substrate 102'. In some embodiments, the first fill material 158 may be a dielectric material. By way of example, the first fill material 158 may be an oxide, such as silicon oxide. The first fill material 158 may be deposited using any suitable process, such as CVD or ALD. In some embodiments, silicon oxide is formed by CVD using a suitable precursor (such as silane (SiH4) or tetraethyl orthosilicate or Si(OC2H5)4 (TEOS)). After deposition, the first fill material 158 may overfill the deep isolation trench 135. The first fill material 158 may be deposited to a thickness of about 2000 angstroms or more, such as about 2500 angstroms to about 4000 angstroms.

[0033] At operation 1018 of method 1000, an etching process, such as wet etching, dry etching, or a combination thereof, is performed on the semiconductor device 100 until a portion of the first isolation layer 156 is exposed, as Figure 10 shown. The first isolation layer 156 acts as an etch stop layer to prevent damage to the via accumulation layer 154 and the substrate 102'. The first fill material 158 forms most of the backside deep trench isolation (BDTI) structure 159. In some cases, the first fill material 158, the first isolation layer 156, and the via accumulation layer 154 in the deep isolation trench 135 are together considered the BDTI structure 159. The BDTI structure 159 forms a BDTI grid around the plurality of photodiode doping regions 104. Each photodiode doping region 104 corresponds to a pixel component and acts as a light sensing region in the pixel component. The BDTI structure 159 provides optical and electrical isolation for the plurality of photodiode doping regions 104 and thus separates individual pixel components.

[0034] In some embodiments, the portion of the first fill material 158 at or near the opening 135o may be recessed after the etching process, as Figure 10A shown. In this case, the height of the top 158t of the first fill material 158 may be at a distance D7 below the top 156t of the first isolation layer 156. The top 158t of the first fill material 158 may be at the same height as the dorsal side 124 of the substrate 102'. In some embodiments, the top 158t of the first fill material 158 is at substantially the same height as the top 154t of the via accumulation layer 154. In some embodiments, the top 158t of the first fill material 158 is at substantially the same height as the top 156t of the first isolation layer 156. As will be described below with reference to Figure 13More specifically, the top of the first fill material 158 at the central region of the wafer can be at a first height, and the top of the first fill material 158 at the edge region of the wafer can be at a second height higher than the first height.

[0035] At operation 1020 of method 1000, a second isolation layer 160 is deposited on the exposed surfaces of the first isolation layer 156 and the first fill material 158, as Figure 11 shown. The second isolation layer 160 can include the same material as the first isolation layer 156, and can be deposited using the same deposition techniques as discussed above with respect to Figure 8 . In some embodiments, the second isolation layer 160 and the first isolation layer 156 include materials that are chemically different from each other. The second isolation layer 160 can be deposited such that the combined thickness T6 of the first isolation layer 156 and the second isolation layer 160 is greater than the thickness T2 of the first isolation layer 156 inside the deep isolation trench 135 ( Figure 8A ) and / or near the opening 135o ( Figure 8A ). In some embodiments, the combined thickness T6 is at least twice the thickness T1 of the first isolation layer 156. For example, the second isolation layer 160 can have a thickness of about 350 angstroms to about 500 angstroms. Figure 11A FIG. shows an enlarged view of a portion of the semiconductor device 100 according to some embodiments. In various embodiments, the ratio (T2:T6) of the thickness T2 to the combined thickness T6 is about 1:3 to about 1:5. Although not shown, it should be understood that the thickness of the first isolation layer 156 in the deep isolation trench 135 gradually changes along the direction away from the opening 135o of the deep isolation trench 135, as discussed above in Figure 8A .

[0036] In some embodiments, the combined thickness T6 of the first isolation layer 156 and the second isolation layer 160 is substantially the same as the thickness T2 of the first isolation layer 156 inside the deep isolation trench 135 ( Figure 8A ) and / or near the opening 135o ( Figure 8A ).

[0037] At operation 1022 of method 1000, a second fill material 162 is deposited on the second isolation layer 160, as Figure 12As shown. The second fill material 162 is configured to increase the absorption of radiation by the photodiode doped region 104 by providing low-reflectivity radiation from the substrate 102'. The second fill material 162 can be deposited to have a first thickness of from about 1500 angstroms to about 3000 angstroms. After depositing the second fill material 162, a planarization process, such as a CMP process, is performed so that the thickness of the second fill material 162 is reduced from the first thickness to a second thickness. The second fill material 162 can include the same material as the first fill material 158 and can be deposited using the same deposition techniques as the first fill material 158. In some embodiments, the second fill material 162 can include a high-K dielectric material and a silicon oxide layer. Although the critical dimension of the deep isolation trench 135 is small, using a two-step deposited isolation material (i.e., the first isolation layer 156 and the second isolation layer 160) is advantageous for gap filling the high aspect ratio deep isolation trench 135. This is because the thinner layer of the first isolation layer 156 allows the first isolation layer 156 to be deposited in the deep isolation trench 135 without prematurely pinching off the opening 135o of the deep isolation trench 135, while the thicker layer of the second isolation layer 160 deposited after forming the first fill material 158 in the deep isolation trench 135 ensures that the formed isolation material has the desired thickness and is defect-free. When the gap filling ability is improved, smaller air gaps or seams are formed, so there are fewer defects generated after the thermal or CMP process.

[0038] Figure 12A FIG. shows an enlarged view of a portion of a semiconductor device 100 according to some embodiments. The sidewalls 158s, bottom 158b, and top 158t of the first fill material 158 of the BDTI structure 159 are surrounded by and in contact with the first isolation layer 156. In one embodiment, a portion of the second isolation layer 160 can have a recess 161 above the BDTI structure 159. The recess 161 can be due to the height difference between the top 158t of the first fill material 158 and the top 156t of the first isolation layer 156 (i.e., Figure 10Aformed by the distance D7 shown in [figure]. The air gap or slit 157 may have a height D8, and the height D8 is about 55% to about 90% (e.g., about 75% to 85%) of the height D9 of the deep isolation trench 135. In some embodiments, the top 158t of the first filling material 158 in the deep isolation trench 135 (which is the interface defined by the second isolation layer 160 and the first filling material 158) has a width W1. The interface is located at a height above the air gap or slit 157 and radially spans the entire width of the air gap or slit 157. The first isolation layer 156 and the second isolation layer 160 (collectively referred to as the isolation shield 163) above the BDTI structure 159 extend above the first filling material 158 and the air gap or slit 157 and span the first filling material 158 and the air gap or slit 157. In particular, the thickness T6 of the isolation shield 163 is greater than the thickness of the first isolation layer 156 within the deep isolation trench 135 (e.g., T2, T3, T4, and T5).

[0039] Figure 13 FIG. is a schematic diagram of a wafer 200 showing an exemplary arrangement of semiconductor devices according to some embodiments. The wafer 200 can be fabricated to form a plurality of semiconductor devices, such as the semiconductor device 100. The wafer 200 may have a central region 282 and an edge region 284 surrounding the central region 282. The semiconductor devices formed in the central region 282 and the edge region 284 are substantially the same as Figure 12 the semiconductor device 100, except that: (1) the top 158ta of the BDTI structure 159a in the central region 282 is substantially at the same height as the back side 124 of the substrate 102', while the top 158tb of the BDTI structure 159b in the edge region 284 is at a higher height than the back side 124 of the substrate 102'; (2) the air gap or slit 157a of the BDTI structure 159a in the central region 282 has a first height D10, while the air gap or slit 157b of the BDTI structure 159b in the edge region 284 has a second height D11 greater than the first height D10. In some embodiments, the first height D10 is about 55% to about 75% of the height D9 of the deep isolation trench 135, and the second height D11 is about 75% to about 90% of the height D9 of the deep isolation trench 135. The deep isolation trench 135 in the central region 282 may have a width W3 measured at the opening of the deep isolation trench 135 (e.g., as shown in Figure 8A 135o), and the deep isolation trench 135 in the edge region 284 may have a width W4 measured at the opening of the deep isolation trench 135, where the width W3 and the width W4 are substantially the same.

[0040] In some embodiments, the air gap or slit 157a in the central region 282 has a width W5, and the air gap or slit 157b in the edge region 284 has a width W6 that is less than the width W5. In either case, the air gaps or slits 157a, 157b are enclosed within the first filling material 158. The tops of the air gaps or slits 157a, 157b do not extend beyond the back side 124 of the semiconductor device 200. In some alternative embodiments, the tops 158ta, 158tb of the first filling material layer 158 in the deep isolation trenches 135 may be at substantially the same height as the back side 124 of the substrate 102'.

[0041] At operation 1024 of method 1000, a plurality of color filters 166 are formed over the second filling material 162, as Figure 14 shown. The color filters 166 are each configured to transmit incident radiation or incident light of a specific wavelength. For example, a first color filter (e.g., a red color filter) may transmit light having a wavelength within a first range, while a second color filter may transmit light having a wavelength within a second range that is different from the first range. In some embodiments, the plurality of color filters 166 are arranged within a grid structure that covers the plurality of photodiode doping regions 104. In some embodiments, an isolation structure 168 may be formed between adjacent color filters 166 to prevent radiation transmitted through one or more color filters 166 from being projected onto the photodiode doping regions 104 below the adjacent color filters 166.

[0042] At operation 1026 of method 1000, a plurality of microlenses 170 are arranged over the plurality of color filters 166, as Figure 14 shown. Each of the microlenses 170 is laterally aligned with a color filter 166 and substantially covers the pixel regions 103a, 103b. The plurality of microlenses 170 may have a flat bottom surface adjacent to the plurality of color filters 166 and a curved upper surface. The curved upper surface is configured to focus incident radiation or incident light (e.g., light towards the underlying pixel regions 103a, 103b). The plurality of microlenses 170 may be formed by depositing microlens material over the plurality of color filters 166 using a suitable process (e.g., spin coating or deposition process). In some embodiments, a microlens template having a curved upper surface is patterned over the microlens material. The microlens template may include a photoresist material, such as for a negative photoresist. For a negative photoresist, more exposure occurs at the bottom of the curvature and less exposure occurs at the top of the curvature. The microlens template is then developed and baked to form a circle. Then, the plurality of microlenses 170 are formed by selectively etching the microlens material according to the microlens template.

[0043] As Figure 14As shown, the semiconductor device 100 is an imaging sensing device that uses the photodiode doping regions 104 as light sensing regions, and the photodiode doping regions 104 are separated from each other by the BDTI structure 159. The BDTI structure 159 acts as an optical isolator to prevent incident radiation or incident light from entering adjacent photodiode doping regions 104. When receiving incident radiation or incident light, the photodiode doping regions 104 emit electrons due to the photoelectric effect. During the operation of the image sensing die 134, the incident radiation or incident light is focused by the microlens 170 onto the underlying pixel regions 103a, 103b. When incident radiation or incident light with sufficient energy irradiates the photodiode doping regions 104, electron-hole pairs are generated, thereby generating a photocurrent or charge. The transfer gate 132 controls the charge transfer from the photodiode doping regions 104 to the floating diffusion well 136. If the charge level in the floating diffusion well 136 is high enough, a source follower transistor (not shown) is activated, and the charge is selectively output according to the operation of a column selection transistor (not shown) for addressing. A reset transistor (not shown) can be used to reset the photodiode doping regions 104 between exposure periods.

[0044] Various embodiments or examples described herein provide several advantages over the prior art. By using a two-step deposited isolation material (i.e., the first isolation layer 156 and the second isolation layer 160), even when the critical dimension of the deep isolation trench 135 is small, the gap filling of the high aspect ratio deep isolation trench 135 can be improved. The thinner layer of the first isolation layer 156 allows the first isolation layer 156 to be deposited in the deep isolation trench 135 without prematurely pinching off the opening 135o of the deep isolation trench 135, while the thicker layer of the second isolation layer 160 deposited after the first filling material 158 is formed in the deep isolation trench 135 ensures that the isolation material is formed with a desired thickness. When the gap filling ability is improved, air gaps or seams are enclosed within the first filling material 158 in the BDTI structure and do not extend above the BDTI structure. Therefore, air gaps or seams do not cause defects after the thermal or CMP process. Using a two-step deposited isolation material also eliminates defects caused by film stress, which may otherwise appear at the interface between the back side of the semiconductor substrate and the isolation material. Therefore, the yield of the semiconductor device is improved.

[0045] Some embodiments of the present disclosure provide a structure that includes a plurality of photodiode doping regions formed in a semiconductor substrate and a deep trench isolation (DTI) structure formed in the semiconductor substrate, wherein the DTI structure separates individual pixel components, and the DTI structure includes a first filling material that defines an air gap therein. The first filling material includes a top, sidewalls, and a bottom. The structure further includes a first isolation layer that surrounds the top, sidewalls, and bottom of the first filling material and is in contact with the top, sidewalls, and bottom of the first filling material.

[0046] In some embodiments, the structure further includes a second isolation layer disposed above and in contact with the first isolation layer. In some embodiments, the first isolation layer and the second isolation layer comprise the same material. In some embodiments, the structure further includes a second fill material disposed on top of the second isolation layer, wherein the second fill material comprises the same material as the first fill material. In some embodiments, the top of the first fill material and the second isolation layer define a first interface, and the first interface is configured to span the entire width of the air gap. In some embodiments, the first interface has a first width, and the air gap has a second width that is less than the first width. In some embodiments, the structure further includes: a high-k dielectric layer disposed between the first isolation layer and the substrate and in contact with the first isolation layer and the substrate. In some embodiments, the high-k dielectric layer extends between the second isolation layer and the back surface of the substrate, and the high-k dielectric layer is in contact with the second isolation layer and the back surface of the substrate. In some embodiments, the top of the first fill material is at substantially the same height as the back surface of the substrate. In some embodiments, the top of the first fill material is at the same height as a second interface defined by the high-k dielectric layer and the second isolation layer.

[0047] Some embodiments of the present disclosure provide a structure. The structure includes a deep trench isolation (DTI) structure extending to a certain depth into a semiconductor substrate, wherein the DTI structure separates individual pixel components, and the DTI structure includes a fill material defining an air gap therein and a high-k dielectric layer surrounding the sidewalls and bottom of the fill material. The structure further includes an isolation structure including a first isolation layer and a second isolation layer, the first isolation layer being disposed between the high-k dielectric layer and the sidewalls and bottom of the fill material and in contact with the high-k dielectric layer and the sidewalls and bottom of the fill material, and the second isolation layer being disposed on the first isolation layer, wherein a portion of the second isolation layer extends from the top of the fill material and is in contact with the top of the fill material.

[0048] In some embodiments, the second isolation layer extends across the entire width of the fill material. In some embodiments, the first isolation layer and the second isolation layer are formed of the same material. In some embodiments, the first isolation layer has a first thickness, and the second isolation layer has a second thickness different from the first thickness. In some embodiments, the first thickness decreases in a direction away from the top of the fill material. In some embodiments, the deep trench isolation structure has a first dimension, a second dimension greater than the first dimension, and a third dimension less than the first dimension. In some embodiments, the air gap has a first height, and the deep trench isolation structure has a second height greater than the first height.

[0049] Some embodiments of the present disclosure provide a method of forming an image sensor. The method includes forming a plurality of photodiode doping regions in and on a front side of a semiconductor substrate, forming deep isolation trenches from a back side of the substrate, wherein the deep isolation trenches separate the plurality of photodiode doping regions. The method further includes depositing a hole accumulation layer on sidewalls of the deep isolation trenches, depositing a first isolation layer on the hole accumulation layer, wherein the first isolation layer has a first thickness. The method further includes depositing a first filling material on the first isolation layer in the deep isolation trenches, wherein the first filling material surrounds air gaps. The method further includes depositing a second isolation layer on exposed surfaces of the first isolation layer and the first filling material, wherein the second isolation layer has a second thickness greater than the first thickness.

[0050] In some embodiments, the method further includes: after depositing the first filling material, removing a portion of the first filling material until the first isolation layer is exposed. In some embodiments, the method further includes: depositing a second filling material on the second isolation layer, wherein the first filling material and the second filling material comprise the same material.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that: include: a plurality of photodiode doped regions formed in the substrate; as well as A deep trench isolation structure is formed in the substrate, wherein the deep trench isolation structure separates the plurality of photodiode doping regions, and the deep trench isolation structure comprises: A first filling material, wherein an air gap is defined in the first filling material, and the first filling material includes a top, a sidewall, and a bottom; as well as The first isolation layer surrounds and contacts the top, the sidewall and the bottom of the first filling material.

2. The semiconductor device according to claim 1, wherein: Also includes: The second isolation layer is disposed above the first isolation layer and contacts the first isolation layer.

3. The semiconductor device according to claim 2, wherein: The first isolation layer and the second isolation layer include the same material.

4. The semiconductor device according to claim 2, wherein: Also includes: A second filling material is disposed on the second isolation layer, wherein the second filling material comprises the same material as the first filling material.

5. The semiconductor device according to claim 2, wherein: The top of the first filling material and the second isolation layer define a first interface, and the first interface is arranged to span across the entire width of the air gap.

6. A semiconductor device, characterized in that: include: A deep trench isolation structure extending to a certain depth in the substrate, wherein the deep trench isolation structure separates the photodiode doping regions, and the deep trench isolation structure comprises: a filler material defining an air gap therein; and A high-K dielectric layer surrounding the sidewalls and bottom of the filling material; and Isolation structure, including: a first isolation layer disposed between the high-K dielectric layer and the sidewalls and the bottom of the filling material, and in contact with the high-K dielectric layer and the sidewalls and the bottom of the filling material; and The second isolation layer is disposed on the first isolation layer, and a portion of the second isolation layer extends from the top of the filling material and contacts the top of the filling material.

7. The semiconductor device according to claim 6, wherein: The second isolation layer extends across the entire width of the fill material.

8. The semiconductor device according to claim 6, wherein: The first isolation layer has a first thickness, and the second isolation layer has a second thickness different from the first thickness.

9. The semiconductor device according to claim 8, wherein: The first thickness decreases in a direction away from the top of the filling material.

10. The semiconductor device according to claim 6, wherein: The air gap has a first height, and the deep trench isolation structure has a second height greater than the first height.

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