Equipment mainboard

Abstract

The embodiment of the utility model provides an equipment mainboard, which at least comprises a first control board and a second control board, and the first control board and the second control board are connected through a golden finger; wherein the first control panel at least comprises a first processing module, a second processing module, a first basic input / output module, a second basic input / output module and a first digital integrated circuit module, the first processing module is connected with the second processing module, and the first processing module and the second processing module are respectively connected with the first digital integrated circuit module; the first processing module is connected with the first basic input and output module, and the second processing module is connected with the second basic input and output module; the second control board at least comprises a second digital integrated circuit module and a power management module, and the second digital integrated circuit module is connected with the power management module. Diversity can be configured, various spare parts can be freely selected for adaptation, flexibility is high, and practicability is high.

Description

Technical Field

[0001] This application relates to the field of computer technology, and more particularly, to a device motherboard. Background Art

[0002] With the continuous development of computers, higher requirements are placed on the performance, specifications, and stability of computers. In particular, the demand for critical chips in computers is also increasing, and the demand volume is relatively large. However, sometimes these critical chips cannot be obtained in a timely manner, which affects the production progress of the motherboard. How to be unaffected by critical chips and provide a motherboard that meets requirements according to user needs is an urgent problem to be solved currently. Summary of the Utility Model

[0003] The purpose of the embodiments of this application is to provide a device motherboard to achieve the technical effect of selecting a chip that meets the conditions according to user needs and generating a computer motherboard without being restricted by chip manufacturers.

[0004] In the first aspect of the embodiments of this application, a device motherboard is provided. The device motherboard at least includes a first control board and a second control board, and the first control board and the second control board are connected by a gold finger; wherein,

[0005] The first control board at least includes a first processing module, a second processing module, a first basic input / output module, a second basic input / output module, and a first digital integrated circuit module. The first processing module and the second processing module are connected, the first processing module and the second processing module are respectively connected to the first digital integrated circuit module, the first processing module is connected to the first basic input / output module, and the second processing module is connected to the second basic input / output module;

[0006] The second control board at least includes a second digital integrated circuit module and a power management module, and the second digital integrated circuit module is connected to the power management module.

[0007] In the above implementation process, the main board of the device includes at least a first control board and a second control board, and the first control board and the second control board are connected by a gold finger; wherein, the first control board includes at least a first processing module, a second processing module, a first basic input / output module, a second basic input / output module and a first digital integrated circuit module, the first processing module and the second processing module are connected, the first processing module and the second processing module are respectively connected to the first digital integrated circuit module, the first processing module is connected to the first basic input / output module, and the second processing module is connected to the second basic input / output module; the second control board includes at least a second digital integrated circuit module and a power management module, and the second digital integrated circuit module is connected to the power management module. In the embodiments of the present application, diversity can be configured, and a variety of spare parts can be freely selected for adaptation, with high flexibility and high practicality.

[0008] Optionally, the first control board further includes a PCIE to SATA module and a PCIE to USB module;

[0009] The first PCIE interface of the first processing module is connected to the PCIE to SATA module; the second PCIE interface of the first processing module is connected to the PCIE to USB module.

[0010] Optionally, the PCIE to SATA module includes at least an 88SE9230 chip, and the PCIE to USB module includes at least an UPD720201 chip.

[0011] In some embodiments of the present application, the PCIE is converted into SATA and USB for conversion. Compared with the previous scheme of converting the bridge chip into SATA and USB interfaces, the circuit design is simplified and the cost is reduced.

[0012] Optionally, the first processing module further includes an SPI1 interface and a QSPI0 interface, and the SPI1 interface is used to burn TPM / TPCM;

[0013] The QSPI0 interface is used to burn the main BIOS; the second processing module further includes a QSPI1 interface, and the QSPI1 interface is used to burn the backup BIOS.

[0014] In some embodiments of the present application, the general SPI interface is only used as a general SPI master, used to initiate and control the transmission, and generate a clock, and the QSPI interface controls the QSPI interface to be compatible with SPI, used to connect the external storage firmware Flash, which is the only interface for the processor to load the off-chip firmware.

[0015] Optionally, the first processing module further includes a first serial interface, and the first serial interface includes at least an I 2 C interface or an I 3 C interface;

[0016] The second processing module further includes a second serial interface, and the second serial interface includes at least an I 2 C interface or an I 3 C interface, wherein the I 3 C interface is used to connect a dual in-line memory module.

[0017] In some embodiments of the present application, the first processing module and the second processing module communicate through I3C to read DIMM information and perform data transmission.

[0018] Optionally, the first processing module and the second processing module are connected through a C2C and PCIE link high-speed direct connection interface.

[0019] Optionally, the TACH pin of the second digital integrated circuit module is connected to the power management module.

[0020] Optionally, the first processing module further includes a UART interface, and is connected to the power management module through the UART interface.

[0021] Optionally, the first processing module further includes a PCIe interface, and the PCIe interface is used to connect an external device.

[0022] In some embodiments of the present application, it is compatible with the PCI Express 5.0 standard and backward compatible. It supports lane reversal and lane polarity reversal, and can connect external devices according to requirements.

[0023] Optionally, both the first processing module and the second processing are Feiteng S5000C chips.

[0024] In some embodiments of the present application, the S5000C domestic chip is more stable and has higher performance than existing chips. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as limiting the scope. For those of ordinary skill in the art, without creative efforts, other relevant drawings can also be obtained based on these drawings.

[0026] Figure 1 It is a structural block diagram of a device motherboard provided by an embodiment of the present application;

[0027] Figure 2 Schematic diagram of another device motherboard provided by an embodiment of the present application;

[0028] Figure 3 Schematic diagram of yet another device motherboard provided by an embodiment of the present application. Detailed implementation manners

[0029] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application.

[0030] It should be noted that similar reference numerals and letters denote similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. At the same time, in the description of the present application, the terms "first", "second", etc. are only used for distinguishing descriptions and cannot be construed as indicating or implying relative importance.

[0031] Please refer to Figure 1 , Figure 1 , which is a structural block diagram of a device motherboard provided by an embodiment of the present application. The device motherboard at least includes: a first control board 10 and a second control board 20, and the first control board 10 and the second control board 20 are connected by a gold finger, where:

[0032] The first control board at least includes a first processing module 101, a second processing module 102, a first basic input / output module 103 (BIOS), a second basic input / output module 104 (BIOS), and a first digital integrated circuit module 105 (CPLD). Among them, the first processing module 101 and the second processing module 102 are connected, the first processing module 101 and the second processing module 102 are respectively connected to the first digital integrated circuit module 105, the first processing module 101 is connected to the first basic input / output module 103, and the second processing module 102 is connected to the second basic input / output module 104;

[0033] The second control board 20 at least includes a second digital integrated circuit module 106 and a power management module 107, and the second digital integrated circuit module 106 is connected to the power management module 107.

[0034] In the above implementation process, the device motherboard can have diverse configurations, and various spare parts can be freely selected for adaptation, with high flexibility and high practicality.

[0035] Figure 2 and Figure 3 is a schematic diagram of another device motherboard provided by an embodiment of the present application. As shown in Figure 2 and Figure 3 shown, Figure 2 and Figure 3Connected by the gold fingers, the main board of the device includes: 2 CPU (Central Processing Unit) processors, 2 BIOS (Basic Input / Output System) modules, 1 CPLD (Complex Programmable Logic Device) module, and 1 BMC (Baseboard Management Controller) module. The BMC module is independent of the main board and comes with its own CPLD module. The CPU uses Feiteng S5000C, which is mainly used for high-performance computing and service management and provides a large-capacity Memory storage interface externally. It also expands the PCIe (peripheral component interconnect express) interface externally for the storage devices of the system.

[0036] Optionally, the first control board 10 further includes a PCIE-to-SATA module and a PCIE-to-USB module;

[0037] The first PCIE interface of the first processing module is connected to the PCIE-to-SATA module; the second PCIE interface of the first processing module is connected to the PCIE-to-USB module.

[0038] Optionally, the PCIE-to-SATA module includes at least the 88SE9230 chip, and the PCIE-to-USB module includes at least the UPD720201 chip.

[0039] Adopting the scheme of converting PCIE into SATA and USB for conversion, compared with the previous scheme of using a bridge chip to convert into SATA (Serial ATA, used for data transmission between the main board and a large number of storage devices such as hard disks and optical disc drives) and USB interfaces, simplifies the circuit design and reduces the cost. It provides an 8-channel DDR5 memory interface externally with a maximum speed of 4400MT / s.

[0040] Since the S5000C does not have its own SATA and USB interfaces, the current circuit adopts the scheme of converting PCIE into SATA and USB for conversion. The UPD720201 is used for converting PCIE to USB3.0 and USB2.0; the 88SE9230 is used for converting PCIE to SATA. The single-board PCIE of the S5000C is converted into a USB interface through the UPD72020, with one USB3.0 built-in, and one USB 3.0 for each of the left and right ears, which is compatible with USB2.0.

[0041] In some embodiments of the present application, a PCIE-to-SATA and USB conversion scheme is adopted. Compared with the previous scheme of using a bridge chip to convert to SATA and USB interfaces, the circuit design is simplified and the cost is reduced.

[0042] Optionally, the first processing module further includes an SPI1 interface and a QSPI0 interface. The SPI1 interface is used for burning TPM / TPCM.

[0043] The QSPI0 interface is used for burning the main BIOS. The second processing module further includes a QSPI1 interface, and the QSPI1 interface is used for burning the standby BIOS.

[0044] S5000C includes 4 general-purpose SPI interfaces, which are only used as general-purpose SPI masters for initiating and controlling transmissions and generating clockers. In the current design, CPU1 only uses 1 group of SPI channels D0_SPI. CPU2 does not use SPI resources.

[0045] S5000C includes 4 QSPI (Quad Serial Peripheral Interface, SPI interface) interfaces. The QSPI interface controls the QSPI interface to be compatible with SPI and is used to connect to the Flash for external storage firmware. It is the only interface for the processor to load off-chip firmware. The SPI (Serial Peripheral Interface) bus system is a high-speed, full-duplex, synchronous communication bus.

[0046] CPU1 and CPU2 use the D0_QSPI channel interface for upgrading related software.

[0047] The SPI1 channel of CPU1 is used for burning TPM / TPCM.

[0048] CPU1 QSPI0 is used for burning BIOS1 (main BIOS).

[0049] CPU2 QSPI0 is used for burning BIOS 0 (standby BIOS). At the same time, BMC SPI1 realizes the function of burning BIOS1 (main BIOS) through the QSPI0SWTICH with CPU1.

[0050] In some embodiments of the present application, the general-purpose SPI interface is only used as a general-purpose SPI master for initiating and controlling transmissions and generating clockers. The QSPI interface controls the QSPI interface to be compatible with SPI and is used to connect to the Flash for external storage firmware. It is the only interface for the processor to load off-chip firmware.

[0051] Optionally, the first processing module further includes a first serial interface, and the first serial interface at least includes I 2C interface or I 3 C interface;

[0052] The second processing module further includes a second serial interface, and the second serial interface includes at least an I2C interface or an I3C interface. Among them, the I3C interface is used to connect a dual in-line memory module.

[0053] Specifically, I2C (Inter-Integrated Circuit) is a serial synchronous communication bus, including a data line SDA and a clock line SCL. I2C is used to connect a microcontroller and its peripheral devices, and has the advantages of fewer interface lines, simple control mode, and higher communication rate. I3C is an upgraded protocol of I2C, with a higher rate, improving the disadvantage that I2C requires additional interrupts and making the signal transmission system more concise. Each DIE of the chip integrates a group of I3C interfaces and 5 groups of I2C interfaces.

[0054] After power-on and startup, when the CPU initializes the memory, it will read the SPD information of the DIMM strip through the CPU D0_I3C_XXX to initialize the memory. The I3C interface of the CPU is of the 1.1V IO level type. If the externally connected device is not compatible with the 1.1V level, a dedicated level conversion chip is required for level conversion.

[0055] CPU1 and CPU2 each have a group of I3C channels in groups D0-D3, which communicate with the I3C of the DIMM (Dual-Inline-Memory-Modules, Chinese name is dual in-line memory module) to read DIMM information.

[0056] There are 3 groups of CPU interconnections between CPU1 and CPU2. BMC E2000S provides 12 I2C / SMBUS interfaces, supporting up to the High Speed mode at most. The I2C interface can work in the Master or Slave mode, and the CPUs communicate through PCIE5.0.

[0057] The first processing module and the second processing module each integrate 8 DDR interfaces, and their main features include:

[0058] The interface is compatible with RDIMM / UDIMM of the DDR4 standard and DIMM of the DDR5 standard. The DIMM types of the same chip need to be consistent, and mixed insertion is not supported.

[0059] In some embodiments of the present application, the first processing module and the second processing module use I3C communication to read DIMM information and perform data transmission.

[0060] Optionally, the first processing module and the second processing module are connected through a C2C and PCIE link high-speed direct connection interface.

[0061] Specifically, the device motherboard integrates two CPUs that work together to provide good computing performance and system management capabilities for the system. Each CPU can provide an 8-channel DDR5 memory interface externally; a single CPU can provide 4 Gen5.0x16 channels, 4 Gen5.0 X8 channels, and 4 Gen3.0 X1 channels, providing high-performance service expansion capabilities for the system. The CPUs are interconnected through high-speed direct connection interfaces of C2C and PCIE links. The high-speed direct connection interfaces are used for interaction between multiple CPUs in the system. Each Die integrates 2 X16 C2C interfaces, which are split into 4 direct connection interfaces, and each direct connection interface has 8 physical paths. Among them, a total of four direct connection interfaces, namely D0_C2C0, D1_C2C0, D2_C2C0, and D3_C2C0, are used for Socket interconnection, and the remaining interconnection interfaces are for internal use of the CPU.

[0062] Optionally, the TACH pin of the second digital integrated circuit module is connected to the power management module.

[0063] Specifically, the 1U motherboard uses 7 FANs, and the 2U uses 6 FANs;

[0064] PWM signal: provided by the CPLD or transmitted by the BMC module through the CPLD module;

[0065] TACH signal: directly transmitted from the FAN to the BMC module;

[0066] PRSNT and ID signals: transmitted from the FAN to the CPLD module, and the BMC module reads the registers through the LBUS to obtain them.

[0067] Optionally, the first processing module further includes a UART interface, which is connected to the power management module through the UART interface.

[0068] UART1 is the default information input / output interface of the CPU. It can be used to read CPU-related information through SOL to the BMC at D0_UART1_RXD for UART1 data reception.

[0069] S5000C-64 includes 16 UART interfaces.

[0070] (Universal Asynchronous Receiver / Transmitter, a general asynchronous receiving and transmitting device) controller, with 12 three-wire interfaces (4SCP + 8AP), providing only input and output, and 4 full-function interfaces. The UART interface level of the Tengyun S5000C-64 is the 1.8V CMOS level standard. If the peripherals used are not compatible with the 1.8V CMOS level, level conversion is required; by default, UART1 is the system debugging serial port for system printing information.

[0071] The device motherboard also includes a JTAG interface, that is, a CPLD debugging interface. The master and slave CPLDs each have a debugging interface. The BMC outputs a VGA (Video Graphics Array) to the motherboard through the SWITCH and then to the left ear cable through the connector.

[0072] Optionally, the first processing module further includes a PCIe interface for connecting external devices.

[0073] The first processing module and the second processing module respectively integrate 4 x16 PCle interfaces (DO_PCIE, D1_PCIE, D2_PCIE, D3_PCIE), and 4 x1-width PCIe interfaces. x1 supports the PCI Express 3.0 standard and is downward compatible. x16 supports the PCI Express 5.0 standard and is downward compatible. x16 can be split and configured into x8x8 / x8x4x4 / x4x4x4x4 modes. Lane inversion is supported in each split mode. The hot plug function is supported, and the hot plug pins can be configured to implement the function.

[0074] In some embodiments of the present application, it is compatible with the PCI Express 5.0 standard and is downward compatible. Lane inversion and lane polarity inversion are supported, and external devices can be connected according to requirements.

[0075] Optionally, both the first processing module and the second processing are Feiteng S5000C chips.

[0076] In some embodiments of the present application, the S5000C domestic chip is more stable and has higher performance than the existing chips.

[0077] The device motherboard provided by the embodiments of this application supports the interconnection of two processors. The physical channels cannot be split and can operate in a reduced lane mode. The signals support AC and DC coupling modes; it is compatible with the PCI Express 5.0 standard and backward compatible. It supports lane reversal and lane polarity reversal. It has a 100 MHz external reference clock; the data channels integrate adaptive CTLE and DFE, support on-chip automatic termination, and require a dedicated pin to externally connect a 200 Ω precision reference resistor. It supports the loopback test function and the BIST function.

[0078] The embodiments of this application adopt the domestic S5000C chip, which is more stable and has higher performance than the S2500 chip; the motherboard has a high domestic content rate and high security and controllability; the device motherboard contains 2 BIOS modules, with master-slave cooperation, making it more reliable; it has a variety of configurations and can freely select a variety of spare parts for adaptation, with high flexibility and high practicality; the S5000C chip has a maximum rate of 4400 MT / s in DDR5 mode, while the S2500 chip supports a maximum rate of 3200 MT / s in DDR4 mode; the BMC is an independent motherboard that can be adapted to different motherboards, with higher versatility, and can also reduce the degree of motherboard heterogeneity and reduce costs.

[0079] In several embodiments provided in this application, it should be understood that the disclosed devices and methods can also be implemented in other ways. The device embodiments described above are only illustrative. For example, the flowcharts and block diagrams in the accompanying drawings show the possible architectures, functions, and operations of devices, methods, and computer program products according to multiple embodiments of this application. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the module, program segment, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks can actually be executed substantially in parallel, and they can sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram and / or flowchart, and the combination of blocks in the block diagram and / or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or actions, or can be implemented by a combination of dedicated hardware and computer instructions.

[0080] In addition, the functional modules in each embodiment of this application can be integrated together to form an independent part, or each module can exist alone, or two or more modules can be integrated to form an independent part.

[0081] When the above-mentioned functions are implemented in the form of software function modules and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of this technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a server, or a network device, etc.) to execute all or part of the steps of the methods described in various embodiments of this application. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs.

[0082] The above are only the embodiments of this application and are not used to limit the protection scope of this application. For those skilled in the art, this application can have various changes and modifications. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of this application shall be included in the protection scope of this application. It should be noted that similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings.

[0083] As mentioned above, these are only the specific implementation manners of this application, but the protection scope of this application is not limited thereto. Any person skilled in the art can easily think of changes or replacements within the technical scope disclosed in this application, and all should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

[0084] It should be noted that in this text, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. Without further limitations, an element defined by the statement "including a..." does not exclude the existence of additional identical elements in the process, method, article or device including the said element.

Claims

1. A device main board, characterized in that, The device main board includes at least a first control board and a second control board, and the first control board and the second control board are connected by a gold finger; wherein, The first control board includes at least a first processing module, a second processing module, a first basic input / output module, a second basic input / output module, and a first digital integrated circuit module. The first processing module and the second processing module are connected, the first processing module and the second processing module are respectively connected to the first digital integrated circuit module, the first processing module is connected to the first basic input / output module, and the second processing module is connected to the second basic input / output module; The second control board includes at least a second digital integrated circuit module and a power management module, and the second digital integrated circuit module is connected to the power management module.

2. The device main board according to claim 1, characterized in that, The first control board further includes a PCIE-to-SATA module and a PCIE-to-USB module; The first PCIE interface of the first processing module is connected to the PCIE-to-SATA module; the second PCIE interface of the first processing module is connected to the PCIE-to-USB module.

3. The device motherboard according to claim 2, characterized in that, The PCIE-to-SATA module includes at least an 88SE9230 chip, and the PCIE-to-USB module includes at least an UPD720201 chip.

4. The device main board according to claim 1, characterized in that, The first processing module further includes an SPI1 interface and a QSPI0 interface, and the SPI1 interface is used for burning TPM / TPCM; The QSPI0 interface is used for burning the main BIOS; the second processing module further includes a QSPI1 interface, and the QSPI1 interface is used for burning the backup BIOS.

5. The device main board according to claim 4, characterized in that, The first processing module further includes a first serial interface, and the first serial interface includes at least an I 2 C interface or an I 3 C interface; The second processing module further includes a second serial interface, and the second serial interface includes at least an I 2 C interface or an I 3 C interface, wherein the I 3 C interface is used to connect a dual in-line memory module.

6. The device main board according to claim 4, characterized in that, The first processing module and the second processing module are connected through a C2C and PCIE link high-speed direct connection interface.

7. The device main board according to claim 1, wherein The TACH pin of the second digital integrated circuit module is connected to the power management module.

8. The device main board according to claim 1, wherein, The first processing module further includes a UART interface, and is connected to the power management module through the UART interface.

9. The device main board according to claim 1, characterized in that, The first processing module further includes a PCIe interface, and the PCIe interface is used for connecting external devices.

10. The device main board according to claim 1, characterized in that, Both the first processing module and the second processing module are Feiteng S5000C chips.

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