Series-parallel address allocation and activation circuit, battery module and system

Abstract

The utility model discloses a series-parallel connection address distribution and activation circuit, a battery module and a system. The circuit is applied to a BMS circuit and comprises a first optocoupler, a second optocoupler, a first diode, a second diode and an activation circuit. An input positive electrode of the first optocoupler is connected with the MCU, an input address distributes an output signal, and an input negative electrode is grounded; the output anode is connected with a system working power supply; the output negative electrode is grounded through a resistor and is connected with the address allocation output port; the input anode of the second optocoupler is connected with the address allocation input port, and the input cathode of the second optocoupler is grounded; an output positive electrode of the awakening circuit is connected with the activation circuit through the first diode, outputs an awakening signal, is connected with the MCU through the second diode, and outputs an address allocation input signal; the activation circuit is connected with the power supply circuit, and when the wake-up signal is at a low level, the power supply circuit is started, and the BMS is activated.

Description

Technical Field

[0001] The utility model relates to the field of BMS, and particularly to an address allocation and activation circuit, a battery module and a system. Background Art

[0002] Nowadays, many lithium battery modules need to be used in series and parallel. If only relying on electrical series connection, many fault protections and states cannot be unified. Therefore, serial and parallel communication is required to ensure the unity of each battery state. A prerequisite for realizing serial and parallel communication is how to make each battery present an orderly arrangement so that the host can know which slave battery it is. In this case, a serial and parallel address allocation system is needed to allocate addresses to each battery module. The current address allocation connection method is to connect each battery module in a chain or a ring through address allocation lines, and then allocate addresses to each slave according to the connection order.

[0003] To perform address allocation, each battery module needs to be activated. At this time, if the battery module is in a sleep state, it needs to be activated manually, which affects the deployment efficiency of the battery module. Summary of the Utility Model

[0004] The utility model aims to provide a serial and parallel address allocation and activation circuit, a lithium battery module and a system to solve at least one of the above technical problems. The technical solutions are as follows:

[0005] A serial and parallel address allocation and activation circuit is applied to a BMS circuit and includes a first optocoupler, a second optocoupler, a first diode, a second diode and an activation circuit;

[0006] For the first optocoupler, its input positive electrode is connected to the MCU to input an address allocation output signal; its input negative electrode is grounded; its output positive electrode is connected to the system working power supply; its output negative electrode is grounded through a resistor and is connected to the address allocation output port;

[0007] For the second optocoupler, its input positive electrode is connected to the address allocation input port, and its input negative electrode is grounded; its output positive electrode is connected to the cathodes of the first diode and the second diode. The anode of the first diode is connected to the activation circuit to output a wake-up signal; the anode of the second diode is connected to the MCU to output an address allocation input signal;

[0008] The activation circuit is connected to the power supply circuit of the BMS circuit. When the wake-up signal is at a low level, the power supply circuit is started and the BMS is activated.

[0009] Further, the power supply circuit includes a power management chip enabled by a high level; the activation circuit includes a PMOS transistor; the PMOS transistor:

[0010] Its source electrode is directly connected to the positive electrode of the power supply or through a first resistor.

[0011] A second resistor is provided between its source electrode and gate electrode.

[0012] Its gate electrode outputs the wake-up signal through a third resistor.

[0013] Its drain electrode is grounded successively through a fourth resistor and a fifth resistor; the middle node of the third resistor and the fourth resistor is connected to the enable terminal of the power management chip.

[0014] Further, a voltage stabilizing diode is also provided between the source electrode and gate electrode of the PMOS transistor, and its gate electrode is connected to the anode of the voltage stabilizing diode.

[0015] Further, a capacitor is also connected in parallel with the fifth resistor.

[0016] Further, a first current-limiting resistor is also connected in series on the input loop of the first optocoupler; a second current-limiting resistor is also connected in series on the input loop of the second optocoupler.

[0017] A battery module, the BMS circuit of which includes the series-parallel address allocation and activation circuit described in any one of the above technical solutions.

[0018] A series-parallel address allocation and activation system, including the battery module described above, the battery module is divided into a host and a slave; the address allocation output port of the host and the address allocation input port of the battery module of the first slave are connected by a cable; the address allocation output port of each slave and the address allocation input port of the next slave are connected by a cable; the address allocation output port of the last slave and the address allocation input port of the host are connected by a cable.

[0019] The present utility model achieves the following technical effects:

[0020] This circuit associates address allocation and system activation, and automatically activates the battery module while performing the address allocation of the battery module, simplifies the manual operation during the address allocation of the battery module, and improves the deployment efficiency of the battery module. Description of the Drawings

[0021] Figure 1 It is a schematic diagram of the address allocation link of the battery module;

[0022] Figure 2 It is a circuit diagram of the series-parallel address allocation and activation circuit of the present utility model;

[0023] Figure 3 It is a schematic diagram of the address allocation link of the battery module of the present utility model. Detailed Embodiments

[0024] To further illustrate each embodiment, the present utility model provides accompanying drawings. These drawings are part of the disclosure of the present utility model, mainly used to illustrate the embodiments, and can be combined with the relevant descriptions in the specification to explain the operating principle of the embodiments. With reference to these contents, those of ordinary skill in the art should be able to understand other possible implementation manners and the advantages of the present utility model.

[0025] The present utility model will be further described below in conjunction with the accompanying drawings and specific implementation manners.

[0026] As Figure 1 and Figure 2 shown, the present utility model provides an embodiment of a series-parallel address allocation and activation circuit for a BMS, which consists of optocouplers OP1, OP2, diodes D1, D2, and an activation circuit, etc.

[0027] Among them, the positive input of optocoupler OP1 is connected to the MCU, and the input address allocation output signal ADD_OUT is output; the negative input is grounded through resistor R1; the positive output of optocoupler OP1 is connected to the power supply +5T, the negative output is grounded through resistor R2, and is also connected to the address allocation output port ADDRESS_NEXT.

[0028] The positive input of optocoupler OP2 is connected to the address allocation input port ADDRESS_IN, and the negative input is grounded through resistor R3; the positive output of optocoupler OP2 is connected to the cathodes of diodes D1 and D2. The anode of diode D1 is connected to the activation circuit to output the wake-up signal SWIN; the anode of diode D2 is connected to the MCU to output the address allocation input signal ADD_IN.

[0029] The power supply +5T is the working power supply for functional units such as the MCU, which can be called the system working power supply, and the voltage is 5V. In actual applications, the voltage of the power supply +5T can also be 3.3V.

[0030] In this embodiment, the activation circuit consists of resistors R4, R5, R6, R7, R8, diode D5, zener diode ZD1, switching transistor PM1, etc. The activation circuit is connected to the control terminal of the power management chip U1, and can start or turn off the output of the power management chip U1.

[0031] In this embodiment, the power management chip U1 is provided with pins such as a power input pin VIN, a control pin / SHDN, a power output pin SW, a feedback input pin FB, and a ground pin GND. The control pin / SHDN indicates shutdown at low level. When the control pin / SHDN is at low level, the power management chip U1 has no output; when the control pin / SHDN is at high level, the power management chip U1 has output. For the complete circuit of the power management chip U1, its reference circuit settings can be obtained according to its model, which will not be elaborated here.

[0032] In the activation circuit, the switching transistor PM1 is a PMOS transistor. Its source S is connected to the battery power supply IN+ (the power supply IN+ draws power from the battery) through the resistor R6 and is connected to the gate G of the switching transistor PM1 through the resistor R4. The gate G is connected to the wake-up signal SWIN through the resistor R5 and the diode D5. Its drain D is grounded through the resistors R7 and R8. The resistors R7 and R8 form a voltage division circuit, and its voltage division output terminal is connected to the / SHDN pin of the power management chip U1. When / SHDN is at a high level, the power management chip U1 starts to enter the working state, outputs power from the SW pin, supplies power to the subsequent circuit, and activates the BMS.

[0033] The working principle of the battery module being activated through address assignment:

[0034] When the address assignment input port ADDRESS-IN is at a low level, the output of the optocoupler OP2 is in an off state. The voltage of the wake-up signal SWIN is equal to the voltage of the power supply IN+ minus the voltage drop of the diode D5. Therefore, the voltage of the wake-up signal SWIN is much higher than the withstand voltage of the MCU pin. Based on the reverse cut-off characteristics of the diodes D1 and D2, it can prevent SWIN from flowing into the MCU pin from ADD-IN. The gate-source voltage Vgs of the switching transistor PM1 is 0V, the switching transistor PM1 is not conducting, the enable pin / SHDN of the power management chip U1 has no level, U1 does not output, and the battery module remains in the sleep state.

[0035] When the address assignment input port ADDRESS-IN changes from a low level to a high level, the output of the optocoupler OP2 conducts, SWIN is pulled low. Due to the voltage division of the resistors R4 and R5, Vgs is less than 0V, and the switching transistor PM1 conducts (the larger the absolute value of Vgs, the smaller the on-resistance of the switching transistor PM1). The voltage of the power supply IN+ is applied to the voltage division circuit composed of R7 and R8, pulling the enable pin / SHDN of the power management chip U1 to a high level. The power management chip U1 starts to output, and the BMS is activated.

[0036] The zener diode ZD1 is an optional configuration to provide overvoltage protection for Vgs of the switching transistor PM1.

[0037] The resistor R6 is an optional setting, which can reduce the voltage value of the gate G of the switching transistor PM1 to the ground.

[0038] The diode D5 is an optional setting, which can draw a branch from the wake-up signal SWIN to activate other functions without affecting the activation of the BMS.

[0039] Based on the above circuit, the address assignment and activation of the battery module are achieved in the following way:

[0040] 1. First, establish a series-parallel address assignment and activation system:

[0041] Connect the power ports of each battery module in series or in parallel;

[0042] Select one of the battery modules as the host and the other battery modules as slaves: Connect the address assignment output port ADDRESS_NEXT of the host and the address assignment input port ADDRESS_IN of the first slave through a cable; Connect the address assignment output port ADDRESS_NEXT of each slave and the address assignment input port ADDRESS_IN of the next slave through a cable; Connect the address assignment output port ADDRESS_NEXT of the last slave and the address assignment input port ADDRESS_IN of the host through a cable. As Figure 3 shown.

[0043] 2. Address Assignment

[0044] (1) The host initiates address assignment: When the host receives a signal to start address assignment, the ADD-OUT port of the MCU of the host BMS will output a high level, the optocoupler OP1 will output a conduction, and the level of the power supply +5T will be poured into the address assignment output port ADDRESS-NEXT through the output terminal of OP1, completing the work of the host to send address assignment to the first slave.

[0045] (2) The 1st slave accepts address assignment: The high-level signal output from the address assignment output port ADDRESS-NEXT of the host is poured into the address assignment input port ADDRESS-IN of the slave through the address assignment line. The high level makes the light-emitting diode at the input terminal of the optocoupler OP2 of the slave forward-biased, and the output terminal of OP2 conducts. ADD-IN is the IO port of the MCU, configured as a high-input. When the output terminal of OP2 conducts, the level of ADD-IN changes from high level to low level. The MCU immediately collects the low level and performs address assignment, and will report it to the host through the CAN communication method. Since it has received the address assignment instruction and is the first slave, it is designated as the 1st slave by the host.

[0046] (3) The 1st slave initiates address assignment: When the 1st slave determines that it has completed address numbering, the ADD-OUT port of the MCU on the slave will give a high level, making the optocoupler OP1 output a conduction, and the level of the power supply +5T will be poured into the ADDRESS-NEXT port through the output terminal of OP1, completing the work of the slave to send address assignment to the next slave.

[0047] (4) The 2nd slave accepts address assignment: The 2nd slave repeats the operation in step (2);

[0048] (5) The 2nd slave initiates address assignment: The 2nd slave repeats the operation in step (3);

[0049] (6) The host accepts address assignment: After step 5 is completed, the ADDRESS-NEXT port of slave 2 outputs a high level, which is fed into the ADDRESS-IN port of the host. Eventually, the MCU of the host will collect that the input port ADD-IN changes from high level to low level. Thus, the address assignment completes a large loop, and the host considers that this address assignment is completed.

[0050] In summary, the present utility model has the following technical effects:

[0051] This circuit associates address assignment with system activation. While performing the address assignment of the battery module, it automatically activates the battery module, simplifies the manual operation during the address assignment of the battery module, and improves the deployment efficiency of the battery module.

[0052] Although the present utility model is specifically shown and described in combination with the preferred implementation embodiments, those skilled in the art should understand that various changes can be made to the present utility model in terms of form and details without departing from the spirit and scope of the present utility model defined by the appended claims, and all of them are within the protection scope of the present utility model.

Claims

1. A series-parallel address allocation and activation circuit, applied to a BMS circuit, characterized in that: It includes a first optocoupler, a second optocoupler, a first diode, a second diode, and an activation circuit; For the first optocoupler, its input positive electrode is connected to the MCU, and the input address assigns an output signal; Its input negative electrode is grounded; its output positive electrode is connected to the system operating power supply; Its output negative electrode is grounded through a resistor and is connected to the address assignment output port; For the second optocoupler, its input positive electrode is connected to the address assignment input port, and its input negative electrode is grounded; its output positive electrode is connected to the cathodes of the first diode and the second diode. The anode of the first diode is connected to the activation circuit to output a wake-up signal; the anode of the second diode is connected to the MCU to output an address assignment input signal; The activation circuit is connected to the power supply circuit of the BMS circuit. When the wake-up signal is at a low level, the power supply circuit is started and the BMS is activated.

2. The series-parallel address allocation and activation circuit according to claim 1, characterized in that: The voltage of the system operating power supply is 5V or 3.3V.

3. The series-parallel address allocation and activation circuit according to claim 1, wherein: The power supply circuit includes a power management chip enabled by a high level; the activation circuit includes a PMOS transistor; for the PMOS transistor: Its source electrode is directly or connected to the power supply positive electrode through a first resistor; A second resistor is provided between its source electrode and gate electrode; Its gate electrode outputs the wake-up signal through a third resistor; Its drain electrode is grounded successively through a fourth resistor and a fifth resistor; the middle node between the third resistor and the fourth resistor is connected to the enable terminal of the power management chip.

4. The series-parallel address allocation and activation circuit according to claim 3, characterized in that: A zener diode is also provided between the source electrode and gate electrode of the PMOS transistor, and its gate electrode is connected to the anode of the zener diode.

5. The series-parallel address allocation and activation circuit according to claim 3, wherein: A capacitor is also connected in parallel to the fifth resistor.

6. The series-parallel address allocation and activation circuit according to claim 1, wherein: A first current-limiting resistor is also connected in series in the input loop of the first optocoupler; a second current-limiting resistor is also connected in series in the input loop of the second optocoupler.

7. A battery module, characterized in that: The BMS circuit thereof includes a series-parallel address assignment and activation circuit as described in any one of claims 1 to 6.

8. A series-parallel address allocation and activation system, characterized in that: It includes a battery module as described in claim 7. The battery module is divided into a host and a slave; the address assignment output port of the host is connected to the address assignment input port of the battery module of the first slave through a cable; the address assignment output port of each slave is connected to the address assignment input port of the next slave through a cable; the address assignment output port of the last slave is connected to the address assignment input port of the host through a cable.

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