Driving circuit and chip

Abstract

The utility model provides a driving circuit and a chip, the driving circuit comprises a voltage adjusting unit, a current mirror, a buffer circuit and a driving unit, and the driving circuit outputs stable current through the current mirror to maintain modulation voltage output by the current mirror. The voltage difference between the modulation voltage and the voltage output by the first switching tube is maintained, and the modulation voltage is maintained and generated through the current mirror and does not need to be provided by accessing an external capacitor, so that the driving circuit can save pins for accessing the capacitor, and the driving circuit can be used for driving the LED light source based on the negative feedback adjustment principle of the current mirror. And the current mirror and the buffer circuit are matched to output stable current to maintain the second voltage output by the buffer circuit, so that a second driving signal for driving the first switching tube is ensured not to be out of control.

Description

Technical Field

[0001] The utility model relates to the technical field of integrated circuits, and particularly relates to a driving circuit and an electronic device. Background Art

[0002] In the field of switching power supply chips, there are still some problems in the design of driving circuits (such as DC-DC circuits or motor drives, etc.) for driving switching transistors. For example, it is necessary to design redundant pins to externally connect capacitors, and thus rely on the externally connected capacitors to provide the required floating voltage to supply power to the driving circuit. This introduces unstable factors to the driving circuit. For example, when the capacitor cannot continuously provide the floating voltage, the driving signal output by the driving circuit to the switching transistor may get out of control, resulting in the switching transistor turning off, and the chip cannot output a normal voltage at the output terminal. Summary of the Utility Model

[0003] The purpose of the utility model is to provide a driving circuit and a chip, which can save the pin design of externally connected capacitors of the chip, improve the stability of the driving circuit, and ensure that the signal for driving the switching transistor will not get out of control.

[0004] To solve the above technical problems, based on one aspect of the utility model, the utility model provides a driving circuit for driving a first switching transistor. One end of the first switching transistor is connected to a power supply voltage, and the other end of the first switching transistor is connected to a load. The driving circuit is characterized in that it includes:

[0005] A voltage adjustment unit, the input end of which is connected to the power supply voltage;

[0006] A current mirror, which has a reference current branch and an output current branch. One end of the reference current branch and one end of the output current branch are both connected to the output end of the voltage adjustment unit;

[0007] A buffer circuit, the first end of which is connected to the output end of the voltage adjustment unit, the second end of which is connected to the other end of the reference current branch, and the third end of which is connected to the other end of the output current branch;

[0008] A driving unit, which is used to output a second driving signal to the first switching transistor. After receiving a first driving signal, the driving unit is connected to the fourth end of the buffer circuit, so that the second driving signal is inverted, and the inverted second driving signal turns on the first switching transistor.

[0009] Optionally, the voltage adjustment unit includes a charge pump.

[0010] Optionally, the voltage adjustment unit is configured to adjust the power supply voltage to a first voltage. The current mirror outputs a modulation voltage based on the first voltage. The buffer circuit outputs a second voltage based on the first voltage and the modulation voltage. After receiving the second voltage, the driving unit flips the second driving signal.

[0011] Optionally, the voltage value of the flipped second driving signal is equal to the second voltage.

[0012] Optionally, the current mirror includes a third switching transistor and a fourth switching transistor. One end of the third switching transistor and one end of the fourth switching transistor are both connected to the output end of the voltage adjustment unit. The other end of the third switching transistor is connected to the third terminal of the buffer circuit. The other end of the fourth switching transistor, the driving end of the fourth switching transistor, and the second terminal of the buffer circuit are connected together. The driving ends of the third switching transistor and the fourth switching transistor are connected.

[0013] Optionally, both the third switching transistor and the fourth switching transistor are LDPMOS transistors.

[0014] Optionally, the buffer circuit includes a fifth switching transistor and a sixth switching transistor. One end of the fifth switching transistor is connected to the other end of the reference current branch. One end of the sixth switching transistor is connected to the output end of the voltage adjustment unit. The driving ends of the sixth switching transistor and the fifth switching transistor are connected and serve as the third terminal of the buffer circuit. The other end of the fifth switching transistor and the other end of the sixth switching transistor are connected and serve as the fourth terminal of the buffer circuit.

[0015] Optionally, both the fifth switching transistor and the sixth switching transistor are LDNMOS transistors.

[0016] Optionally, the driving unit includes a first inverter and a second inverter. The input end of the first inverter receives the first driving signal. The output end of the first inverter is connected to the input end of the second inverter. The output end of the second inverter is connected to the driving end of the first switching transistor. The second inverter is also used to connect to the fourth terminal of the buffer circuit.

[0017] Optionally, the second inverter includes a seventh switching transistor and an eighth switching transistor. The driving ends of the seventh switching transistor and the eighth switching transistor are commonly connected to the output end of the first inverter. One end of the seventh switching transistor is connected to the fourth terminal of the buffer circuit. The other end of the seventh switching transistor and one end of the eighth switching transistor are commonly connected to the driving end of the first switching transistor. The other end of the eighth switching transistor is connected to the other end of the first switching transistor.

[0018] Based on another aspect of the present utility model, the present utility model further provides a chip, which includes a first switching transistor and the driving circuit as described above. One end of the first switching transistor is used to connect to a power supply voltage, the other end of the first switching transistor is used to connect to a load, and the driving end of the first switching transistor is connected to the driving unit of the driving circuit.

[0019] Optionally, the first switching transistor is an LDNMOS transistor.

[0020] To sum up, in the driving circuit and the chip provided by the present utility model, the driving circuit includes a voltage adjustment unit, a current mirror, a buffer circuit, and a driving unit. The driving circuit of the present utility model maintains the modulation voltage output by the current mirror by outputting a stable current through the current mirror, thereby maintaining the voltage difference between the modulation voltage and the voltage output by the first switching transistor. Moreover, the modulation voltage is maintained and generated by the current mirror and does not need to connect an external capacitor to provide it, so that the driving circuit of the utility model can save the pins for connecting the capacitor. And based on the negative feedback adjustment principle of the current mirror, it can be known that the current mirror and the buffer circuit cooperate to output a stable current to maintain the second voltage output by the buffer circuit, thereby ensuring that the second driving signal for driving the first switching transistor will not get out of control.

[0021] It should be noted that since the chip includes the driving circuit, it also has the beneficial technical effects brought by the driving circuit, which will not be repeated here. Description of the Drawings

[0022] Those of ordinary skill in the art should understand that the provided drawings are used to better understand the present utility model and do not constitute any limitation to the scope of the present utility model. Among them:

[0023] Figure 1 is a schematic diagram of a driving circuit of a switching transistor in the related art;

[0024] Figure 2 is a schematic diagram of a chip according to an embodiment of the present utility model;

[0025] Figure 3 is a schematic diagram of a driving circuit according to an embodiment of the present utility model.

[0026] In the drawings:

[0027] 100 - First driving module; 200 - Freewheeling circuit; 300 - Load; 400 - Second driving module;

[0028] 10 - Voltage adjustment unit; 20 - Current mirror; 30 - Buffer circuit; 40 - Driving unit; 41 - First inverter; 42 - Second inverter;

[0029] M1 - The first switching transistor; M2 - The second switching transistor; M3 - The third switching transistor; M4 - The fourth switching transistor; M5 - The fifth switching transistor; M6 - The sixth switching transistor; M7 - The seventh switching transistor; M8 - The eighth switching transistor. Detailed implementation manners

[0030] To make the objectives, advantages and features of the present utility model clearer, the following further describes the present utility model in detail with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in a very simplified form and not drawn to scale, and are only used to conveniently and clearly assist in explaining the objectives of the embodiments of the present utility model. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different emphases and sometimes use different scales.

[0031] As used in the present utility model, the singular forms "a", "an" and "the" include plural objects. The term "or" is usually used in the sense of including "and / or". The term "several" is usually used in the sense of including "at least one". The term "at least two" is usually used in the sense of including "two or more". In addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first", "second", "third" may explicitly or implicitly include one or at least two of such features. "One end" and "the other end" and "proximal end" and "distal end" usually refer to two corresponding parts, which not only include the endpoints. The terms "mounted", "connected", "coupled" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and may be the internal communication of two elements or the interaction relationship between two elements. In addition, as used in the present utility model, when an element is disposed on another element, it usually only means that there is a connection, coupling, cooperation or transmission relationship between the two elements, and the two elements may be directly or indirectly connected, coupled, cooperated or transmitted through an intermediate element, and cannot be understood as indicating or implying the spatial position relationship between the two elements, that is, an element may be inside, outside, above, below or on one side of another element, etc. in any orientation, unless otherwise explicitly specified in the content. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific situations.

[0032] Figure 1 is a schematic diagram of a driving circuit of a switching transistor in the related art. Refer to Figure 1, the drive circuit includes an inverter INV, a PMOS transistor Q1, and an NMOS transistor Q2. An external capacitor C provides a floating voltage VDDH to the inverter INV and the inverter formed by the PMOS transistor Q1 and the NMOS transistor Q2. An external signal IN is input to the inverter INV. The inverter formed by the PMOS transistor Q1 and the NMOS transistor Q2 is used to output a signal GH to the first switching transistor M1. The input terminal of the first switching transistor M1 is connected to the power supply voltage VP. The output terminal of the first switching transistor Q1 is grounded through the second switching transistor Q2, and a circuit output terminal VOUT is led out between the first switching transistor Q1 and the second switching transistor Q2. In this way, the first switching transistor can be driven to conduct according to the input signal IN.

[0033] Referring to Figure 1 For example, the chip needs to design extra pins to externally connect the capacitor C, so as to rely on the capacitor C to provide the required floating voltage VDDH to supply power to the drive circuit. In this way, unstable factors are introduced to the drive circuit. For example, when the capacitor C cannot continuously provide the floating voltage VDDH, the signal GH may get out of control, resulting in the first switching transistor M1 being cut off and unable to output a normal voltage at the output terminal VOUT.

[0034] In view of this, an embodiment of the present invention provides a drive circuit and a chip, aiming to save the pin design of the external capacitor C of the chip, improve the stability of the drive circuit, and ensure that the signal for driving the first switching transistor will not get out of control.

[0035] Figure 2 is a schematic diagram of a chip according to an embodiment of the present invention. Referring to Figure 2 , an embodiment of the present invention schematically provides a chip. The chip can be, for example, a power chip. The chip includes a first drive module 100, a second drive module 400, a first switching transistor M1, and a second switching transistor M2. One end of the first switching transistor M1 is connected to the power supply voltage VP. The other end of the first switching transistor M1 and one end of the second switching transistor M2 are connected and used as the output terminal VOUT of the chip. The output terminal VOUT is connected to the peripheral circuit of the chip and the load 300, such as the freewheeling circuit 200. The other end of the second switching transistor M2 is grounded. The drive terminal of the first switching transistor M1 is connected to the first drive module 100. The first drive module 100 is used to drive the first switching transistor M1 to conduct or cut off. The drive terminal of the second switching transistor M2 is connected to the second drive module 400. The second drive module 400 drives the second switching transistor M2 to conduct or cut off. The second drive module 400 can include, for example, a buffer structure configured based on MOS transistors. And, the first switching transistor M1 and the second switching transistor M2 conduct and cut off alternately.

[0036] For the chip described above, when the first switching transistor M1 is turned on, the chip outputs the power supply voltage VP to the freewheeling circuit 200 and the load 300, thereby supplying power to the load 300 and enabling the freewheeling circuit 200 to store energy. When the second switching transistor M2 is turned on, the second switching transistor M2 and the freewheeling circuit 200 form a freewheeling loop, enabling the freewheeling circuit 200 to release energy to the load 300 and continue to supply power to the load 300. The freewheeling circuit 200 includes components such as capacitors, inductors, freewheeling diodes, etc.

[0037] Preferably, both the first switching transistor M1 and the second switching transistor M2 are LDNMOS transistors. By way of example, the drain of the first switching transistor M1 is connected to the power supply voltage VP, the source of the first switching transistor M1 and the drain of the second switching transistor M2 are connected and used as the output terminal VOUT, the source of the second switching transistor M2 is grounded, the gate of the first switching transistor M1 is connected to the first driving module 100, and the gate of the second switching transistor M2 is connected to the second driving module 400. Those skilled in the art can understand that LDMOS (Laterally Diffused Metal Oxide Semiconductor) refers to laterally diffused metal oxide, which is more voltage-resistant than ordinary MOS transistors. Of course, in some other embodiments, the first switching transistor M1 and the second switching transistor M2 can also be ordinary NMOS transistors.

[0038] Figure 3It is a schematic diagram of a driving circuit according to an embodiment of the present utility model. Further, in this embodiment, the driving circuit in the first driving module 100 is used to drive the first switching transistor M1 to conduct or cut off. Exemplarily, the driving circuit includes a voltage adjustment unit 10, a current mirror 20, a buffer circuit 30, and a driving unit 40. Those skilled in the art can understand that a current mirror usually includes two branches, namely a reference current branch and an output current branch. The reference current branch acts as a reference current source, and the output current branch acts as an output mirror current. The input end of the voltage adjustment unit 10 is connected to the power supply voltage VP. One end of the reference current branch, one end of the output current branch, and the first end of the buffer circuit 30 are all connected to the output end of the voltage adjustment unit 40. The second end of the buffer circuit 30 is connected to the other end of the reference current branch, the third end of the buffer circuit 30 is connected to the other end of the output current branch, and the fourth end of the buffer circuit 30 is used to be connected to the driving unit 40. The voltage adjustment unit 10 adjusts the power supply voltage VP to the first voltage VPP and then outputs it to the current mirror 20 and the buffer circuit 30. In an embodiment, the voltage adjustment unit 10 performs a boosting process on the power supply voltage VP and then outputs the first voltage VPP. The boosting value can be, for example, 5V. The voltage adjustment unit 10 can be, for example, a charge pump or a DCDC boosting circuit. The first voltage VPP serves as the operating voltage of the current mirror 20 and the buffer circuit 30, enabling the current mirror 20 to output a modulation voltage VDDH based on the first voltage VPP and output the modulation voltage VDDH to the third end of the buffer circuit 30. Furthermore, the buffer circuit 30 outputs a second voltage VC based on the first voltage VPP and the modulation voltage VDDH. Those skilled in the art can understand that the second voltage VC here is equal to the difference between the modulation voltage VDDH and the conduction voltage of the reference current branch of the buffer circuit 30. After receiving a first driving signal IN, the driving unit 40 is connected to the fourth end of the buffer circuit 30, thereby receiving the second voltage VC. And after receiving the second voltage VC, the driving unit 40 flips (phase inversion) the second driving signal GH output to the first switching transistor M1. The flipped second driving signal GH turns on the first switching transistor M1. When the driving unit 40 does not receive the first driving signal IN, the connection between the driving unit 40 and the buffer circuit 30 is disconnected. The driving unit 40 does not receive the second voltage VC, the second driving signal GH is not flipped, and the first switching transistor M1 is cut off. In an embodiment, the voltage value of the flipped second driving signal GH is equal to the second voltage VC. It should be noted that based on the process parameter design, the voltage difference between the modulation voltage VDDH and the voltage at the output terminal VOUT can be equal to the boosting value of the voltage adjustment unit 10 for the power supply voltage VP, for example, both are 5V. It should be noted that the first driving signal IN here can come from outside the chip or be generated inside the chip.

[0039] As can be understood by those skilled in the art, the working principle of the current mirror is based on the concept of negative feedback. When a current passes through the reference current branch, the output current branch will automatically adjust the driving voltage of the internal transistor (switching transistor) to output the same current as the reference current branch in real time. This negative feedback regulation mechanism enables the current mirror to generate a very stable output current, that is, the current output by the output current branch can ensure the stability of the modulation voltage VDDH, and further enables the buffer circuit to output a stable second voltage VC based on the first voltage VPP and the modulation voltage VDHH. Moreover, the buffer circuit 30 provides a buffering effect between the modulation voltage VDHH and the second voltage VC, avoiding large fluctuations in the generation of the second voltage VC, and thus ensuring the stability of the second driving signal GH for driving the first switching transistor M1.

[0040] In an embodiment, the driving unit 40 can receive a high-level signal and a low-level signal, and can use one of the high-level signal and the low-level signal as the first driving signal IN. For example, taking the high-level signal as the first driving signal IN, when the high-level signal is input, the driving unit 40 and the buffer circuit 30 are connected, and when the low-level signal is input, the driving unit 40 and the buffer circuit 30 are disconnected.

[0041] Compared with the driving circuit in the related art (i.e., Figure 1 the circuit shown in), the driving circuit of the present invention maintains the modulation voltage VDDH by outputting a stable current through the current mirror 20, thereby maintaining the voltage difference between the modulation voltage VDDH and the voltage output by the first switching transistor M1. Moreover, the modulation voltage VDDH is maintained and generated by the current mirror, and there is no need to design extra pins on the chip to access an external capacitor to obtain the voltage, which can save the pins of the chip for external capacitors. Only the pins for accessing the power supply voltage VP, the pins configured for the chip output VOUT, and the pins for inputting the first driving signal IN need to be designed. And based on the negative feedback adjustment principle of the current mirror, it can be known that the current mirror 20 and the buffer circuit 30 cooperate to output a stable current to maintain the second voltage VC, thereby ensuring that the signal (GH) for driving the first switching transistor M1 will not get out of control, and ensuring that the rising speed of the voltage difference between the modulation voltage VDDH and the second voltage VC is the same as the rising speed of the voltage difference between the modulation voltage VDDH and the output VOUT.

[0042] As an example, the current mirror 20 includes a third switching transistor M3 and a fourth switching transistor M4. One end of the third switching transistor M3 and one end of the fourth switching transistor M4 are both connected to the output end of the voltage adjustment unit 10 to obtain the first voltage VPP. The other end of the third switching transistor M3 is connected to the third end of the buffer circuit 30. The other end of the fourth switching transistor M4, the driving end of the fourth switching transistor M4, and the second end of the buffer circuit 30 are connected together. The driving ends of the third switching transistor M3 and the fourth switching transistor M4 are connected. In this way, the branch where the third switching transistor M3 is located serves as the output current branch of the current mirror 20, the fourth switching transistor M4 serves as the reference current branch of the current mirror 20, and the other end of the third switching transistor M3 outputs the modulation voltage VDDH to the buffer circuit 30.

[0043] Preferably, both the third switching transistor M3 and the fourth switching transistor M4 are LDPMOS transistors. Exemplarily, the sources of the third switching transistor M3 and the fourth switching transistor M4 are both connected to the output end of the voltage adjustment unit 10. The gates of the third switching transistor M3, the fourth switching transistor M4, and the drain of the fourth switching transistor M4 are connected together. The drain of the fourth switching transistor M4 is further connected to the second end of the buffer circuit 30, and the drain of the third switching transistor M3 is connected to the third end of the buffer circuit 30. In some other embodiments, both the third switching transistor M3 and the fourth switching transistor M4 can also be ordinary PMOS transistors.

[0044] As an example, the buffer circuit 30 includes a fifth switching transistor M5 and a sixth switching transistor M6. One end of the fifth switching transistor M5 is connected to the other end of the reference current branch of the current mirror 20 (for example, it can be connected to the drain of the fourth switching transistor M4). One end of the sixth switching transistor M6 is connected to the output end of the voltage adjustment unit 10 to obtain the first voltage VPP. The driving ends of the sixth switching transistor M6 and the fifth switching transistor M5 are connected and serve as the third end of the buffer circuit, which is connected to the output current branch of the current mirror 20 (for example, it can be connected to the drain of the third switching transistor M3). The other ends of the fifth switching transistor M5 and the sixth switching transistor M6 are connected and serve as the fourth end of the buffer circuit 30 to generate the second voltage VC. It can be seen from this that the second voltage VC is equal to the difference between the modulation voltage VDDH and the on-voltage of the fifth switching transistor M5.

[0045] Preferably, both the fifth switching transistor M5 and the sixth switching transistor M6 are LDNMOS transistors. The drain of the fifth switching transistor M5 serves as the second end of the buffer circuit 30, the drain of the sixth switching transistor serves as the first end of the buffer circuit 30, the gates of the fifth switching transistor M5 and the sixth switching transistor M6 are connected as the third end of the buffer circuit 30, and the sources of the fifth switching transistor M5 and the sixth switching transistor M6 are connected as the fourth end of the buffer circuit 30. In other embodiments, both the fifth switching transistor M5 and the sixth switching transistor M6 can also be ordinary NMOS transistors.

[0046] Regarding the structural configuration of the driving unit 40, the driving unit 40 includes a first inverter 41 and a second inverter 42. The input terminal of the first inverter 41 receives a first driving signal IN. The output terminal of the first inverter 41 is connected to the input terminal of the second inverter 42. The output terminal of the second inverter 42 is connected to the driving terminal of the first switching transistor M1. The second inverter 42 is further configured to be connected to the fourth terminal of the buffer circuit 30. For example, it can be connected to the fifth switching transistor M5 and the sixth switching transistor M6.

[0047] As an example, the second inverter 42 includes a seventh switching transistor M7 and an eighth switching transistor M8. The driving terminals of the seventh switching transistor M7 and the eighth switching transistor M8 are commonly connected to the output terminal of the first inverter 41. One end of the seventh switching transistor M7 is connected to the fourth terminal of the buffer circuit 30. The other end of the seventh switching transistor M7 and one end of the eighth switching transistor M8 are commonly connected to the driving terminal of the first switching transistor M1. The other end of the eighth switching transistor M8 is connected to the output terminal of the first switching transistor M1. Thus, when the first inverter 41 receives the first driving signal IN, the first inverter 41 outputs an inverted first driving signal IN to turn on the seventh switching transistor M7 and turn off the eighth switching transistor M8. In this way, the second voltage VC is transmitted to the driving terminal of the first switching transistor M1 through the seventh switching transistor M7, and the second voltage VC is used as the inverted second driving signal VC. When the first inverter 41 does not receive the first driving signal IN, the signal output by the first inverter 41 turns off the seventh switching transistor M7 and turns on the eighth switching transistor M8.

[0048] In an embodiment, the seventh switching transistor M7 is a PMOS transistor, and the eighth switching transistor M8 is an NMOS transistor. The source of the seventh switching transistor M7 is connected to the fourth terminal of the buffer circuit 30 (for example, it can be connected to the fifth switching transistor M5 and the sixth switching transistor M6). The drains of the seventh switching transistor M7 and the eighth switching transistor M8 are connected and commonly connected to the driving terminal of the first switching transistor M1. The source of the eighth switching transistor M8 is connected to the other end of the first switching transistor M1 (that is, connected to the output terminal VOUT of the chip). The gates of the seventh switching transistor M7 and the eighth switching transistor M8 are both connected to the output terminal of the first inverter 41.

[0049] It should be noted that the structure of the first inverter 41 can be configured by referring to the structure of the second inverter 42.

[0050] Although the present utility model is disclosed above in preferred embodiments, the above embodiments are not intended to limit the present utility model. For any person skilled in the art, without departing from the scope of the technical solution of the present utility model, many possible variations and modifications can be made to the technical solution of the present utility model by using the technical content disclosed above, or it can be modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical essence of the present utility model without departing from the content of the technical solution of the present utility model still fall within the scope of protection of the technical solution of the present utility model.

Claims

1. A driving circuit for driving a first switching transistor, one end of the first switching transistor is connected to a power supply voltage, and the other end of the first switching transistor is connected to a load, characterized in that, The driving circuit includes: A voltage adjustment unit, the input end of which is connected to the power supply voltage; A current mirror, which has a reference current branch and an output current branch, and one ends of both the reference current branch and the output current branch are connected to the output end of the voltage adjustment unit; A buffer circuit, the first end of which is connected to the output end of the voltage adjustment unit, the second end of which is connected to the other end of the reference current branch, and the third end of which is connected to the other end of the output current branch; A driving unit, which is used to output a second driving signal to the first switching transistor. After receiving the first driving signal, the driving unit is connected to the fourth end of the buffer circuit, so that the second driving signal is inverted, and the inverted second driving signal turns on the first switching transistor.

2. The drive circuit according to claim 1, characterized in that The voltage adjustment unit includes a charge pump.

3. The drive circuit according to claim 1, characterized in that, The voltage adjustment unit is used to adjust the power supply voltage to a first voltage. The current mirror outputs a modulation voltage based on the first voltage. The buffer circuit outputs a second voltage based on the first voltage and the modulation voltage. After receiving the second voltage, the driving unit inverts the second driving signal.

4. The driving circuit according to claim 3, characterized in that the voltage value of the inverted second driving signal is equal to the second voltage.

5. The drive circuit according to claim 1, wherein The current mirror includes a third switching transistor and a fourth switching transistor. One ends of both the third switching transistor and the fourth switching transistor are connected to the output end of the voltage adjustment unit. The other end of the third switching transistor is connected to the third end of the buffer circuit. The other end of the fourth switching transistor, the driving end of the fourth switching transistor, and the second end of the buffer circuit are connected. The driving ends of the third switching transistor and the fourth switching transistor are connected.

6. The drive circuit according to claim 5, characterized in that, Both the third switching transistor and the fourth switching transistor are LDPMOS transistors.

7. The drive circuit according to claim 1, characterized in that The buffer circuit includes a fifth switching transistor and a sixth switching transistor. One end of the fifth switching transistor is connected to the other end of the reference current branch. One end of the sixth switching transistor is connected to the output end of the voltage adjustment unit. The driving ends of the sixth switching transistor and the fifth switching transistor are connected and used as the third end of the buffer circuit. The other ends of the fifth switching transistor and the sixth switching transistor are connected and used as the fourth end of the buffer circuit.

8. The drive circuit according to claim 7, wherein Both the fifth switching transistor and the sixth switching transistor are LDNMOS transistors.

9. The drive circuit according to claim 1, wherein The driving unit includes a first inverter and a second inverter. The input end of the first inverter receives the first driving signal. The output end of the first inverter is connected to the input end of the second inverter. The output end of the second inverter is connected to the driving end of the first switching transistor. The second inverter is also used to connect to the fourth end of the buffer circuit.

10. The drive circuit according to claim 9, wherein, The second inverter includes a seventh switching transistor and an eighth switching transistor. The driving ends of the seventh switching transistor and the eighth switching transistor are commonly connected to the output end of the first inverter. One end of the seventh switching transistor is connected to the fourth end of the buffer circuit. The other end of the seventh switching transistor and one end of the eighth switching transistor are commonly connected to the driving end of the first switching transistor. The other end of the eighth switching transistor is connected to the other end of the first switching transistor.

11. A chip, characterized in that, It includes a first switching transistor and the driving circuit according to any one of claims 1-10. One end of the first switching transistor is used to access a power supply voltage, the other end of the first switching transistor is used to access a load, and the driving end of the first switching transistor is connected to the driving unit of the driving circuit.

12. The chip according to claim 11, characterized in that, The first switching transistor is an LDNMOS transistor.

Images