Chip packaging structure
By optimizing the window shape of the solder resist layer, the problem of poor bottom filling of non-filter chips in traditional chip packages is solved, and the reliability and filling quality of the product are improved.
Patent Information
- Application Number
- CN202422133255.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-29
- Publication Date
- 2025-07-04
- Estimated Expiration
- 2034-08-29
AI Technical Summary
In traditional chip packaging, the cost of the whole surface coating is high and leads to poor filling of the non-filter chip bottom, especially bubble wrap at the edges or corners, affecting product reliability.
Optimize the shape of the window opening of the solder resist layer so that its edges and corners show a gradual trend, reduce the flow rate unevenness of the plastic sealing material in the middle and edges of the window opening, and reduce the friction resistance of the plastic sealing material at the optimized edges and corners of the window opening, thereby improving the problem of poor filling.
It improves the reliability of the chip packaging structure, reduces the possibility that the corners of the cavity below the non-filter chip are wrapped in bubbles, and improves the filling quality of the product.
Smart Images
Figure CN223067077U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of chip packaging, and particularly relates to a chip packaging structure. Background Art
[0002] The filter elements on the filter chip need to work in a cavity environment. In the traditional technology, a film is often used to ensure the formation of a sealed cavity between the filter chip and the substrate. However, only covering the filter chip with a film will make the process more complicated, so the method of covering the whole surface with a film is mostly adopted. However, the cost of covering the whole surface with a film is high, and the film covering will cause the problem of poor filling at the bottom of the non-filter chips in the form of flip-chip in the traditional BDMP module. These filling defects are often concentrated at the edges or corners of the non-filter chips, thus causing potential reliability hazards to the product. Summary of the Utility Model
[0003] The purpose of the utility model is to provide a chip packaging structure, which can reduce the filling defect caused by the air bubbles wrapping the corners of the cavity under the non-filter chip due to the uneven flow rate of the encapsulation material in the middle and at the edges of the opening during the encapsulation process by optimizing the shape of the opening in the solder mask layer, that is, it is beneficial to improve the reliability of the product.
[0004] To achieve the above purpose, the utility model provides a chip packaging structure, which specifically may include:
[0005] A substrate, including a non-filter chip bearing area;
[0006] A plurality of pads, which are arranged on the non-filter chip bearing area in a mutually separated manner;
[0007] A solder mask layer, which is located on the non-filter chip bearing area and is provided with an opening exposing a part of the surface of the substrate and the pads. The opening has a plurality of first corners, and the distance from any one of the first corners to any one of the pads shows a gradual change trend from one end point to the other end point.
[0008] In some optional examples, the opening has four of the first corners, and the cross-sectional shape of the opening in the direction parallel to the surface of the substrate is an irregular polygon structure formed by connecting the four long sides and the four first corners end to end.
[0009] In some optional examples, the contour of the first corner is an arc-shaped or stepped shape that is concave towards the pad.
[0010] In some optional examples, the contour of the first corner is an arc-shaped or stepped shape that is convex away from the pad.
[0011] In some optional examples, the contour of the first corner is a hypotenuse shape connecting its two end points.
[0012] In some alternative examples, there is an included angle between the first corner with a hypotenuse shape and the long side connected thereto, and the included angle is 10° to 80°.
[0013] In some alternative examples, the chip packaging structure further includes:
[0014] A non-filter chip, located on the non-filter carrier area, and includes a substrate and bumps located on the substrate. The bumps are electrically connected to the pads. There is a cavity below the non-filter chip, and the cavity communicates with the opening window.
[0015] In some alternative examples, the non-filter chip has a plurality of second corners; the orthographic projection of the second corner on the substrate overlaps partially with the orthographic projection of the first corner on the substrate.
[0016] In some alternative examples, a part of the orthographic projection of the second corner on the substrate is located outside the orthographic projection of the first corner on the substrate.
[0017] In some alternative examples, a part of the orthographic projection of the second corner on the substrate is located inside the orthographic projection of the first corner on the substrate.
[0018] In some alternative examples, the chip packaging structure further includes:
[0019] A plastic encapsulation layer, located on the non-filter chip, and fills the cavity and the opening window.
[0020] Compared with the prior art, in the chip packaging structure provided by the present utility model, the opening window (with right-angled corners) of the solder mask layer in the prior art having a regular quadrilateral shape is optimized to an opening window (with non-right-angled corners) in which the first corner shows a gradual change trend from one end point to the other end point. Then, by utilizing the characteristic that the frictional resistance of the plastic encapsulation material at the corner positions of the optimized opening window becomes smaller during the plastic encapsulation process, that is, the flow rate difference of the plastic encapsulation material at the middle position and the corner positions of the opening window becomes smaller, it is realized to reduce the filling defect caused by air bubbles wrapping the corners of the cavity below the non-filter chip due to the uneven flow rate of the plastic encapsulation material in the middle and the edge of the opening window during the plastic encapsulation process, which is beneficial to improving the reliability of the product. BRIEF DESCRIPTION OF THE DRAWINGS
[0021] The drawings are used to provide a further understanding of the present application, and constitute a part of the specification. Together with the following specific embodiments, they are used to explain the present application, but do not constitute a limitation to the present application. In the drawings:
[0022] Figure 1 It is a schematic cross-sectional structure diagram of the substrate structure in the prior art chip packaging structure;
[0023] Figure 2 The top view of the substrate structure in the prior art chip packaging structure shown in Figure 1 ;
[0024] Figure 3a is Figure 2 the schematic structural diagram corresponding to the opening 11 during the initial filling of the encapsulation material in
[0025] Figure 3b is Figure 3a the partial enlarged view of a certain corner of the opening 11 filled with the encapsulation material in
[0026] Figures 4a - 4d then is Figure 2 the schematic structural diagram corresponding to the opening 11 at different time periods during the filling of the encapsulation material in
[0027] Figure 5 an example diagram of the orthographic projection of the optimized opening on the substrate in the chip packaging structure provided in the embodiment of the present invention;
[0028] Figure 6 another example diagram of the orthographic projection of the optimized opening on the substrate in the chip packaging structure provided in the embodiment of the present invention;
[0029] Figure 7 another example diagram of the orthographic projection of the optimized opening on the substrate in the chip packaging structure provided in the embodiment of the present invention;
[0030] Figure 8 is Figure 5 an example diagram of the overlap of the orthographic projection of the non - filter chip and the optimized opening shown in
[0031] Figure 9 on the substrate in the chip packaging structure provided in the embodiment of the present invention; Figure 6 another example diagram of the overlap of the orthographic projection of the non - filter chip and the optimized opening shown in
[0032] Figure 10 is Figure 7 another example diagram of the overlap of the orthographic projection of the non - filter chip and the optimized opening shown in
[0033] Figure 11 is Figure 7 another example diagram of the overlap of the orthographic projection of the non - filter chip and the optimized opening shown in
[0034] Figures 12a - 12d is Figure 7 The structural schematic diagrams corresponding to different time periods during the process of filling the encapsulation material in the window 121 in the middle.
[0035] Among them, the reference numerals are as follows:
[0036] 100 - substrate; 100A - non-filter bearing area, 110 - pad, 120 / 1 - solder mask layer, 121 / 11 - window, 1211 - first corner, 1211a - first endpoint of the first corner, 1211b - second endpoint of the first corner, 130 - non-filter chip and its orthographic projection on the substrate, 131 - second corner, 140 / 2 - encapsulation layer, 13 - orthographic projection of the non-filter chip on the substrate.
[0037] In the drawings, the same components are denoted by the same reference numerals, and the drawings are not drawn to actual scale. Detailed implementation manners
[0038] The following specific embodiments are used to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.
[0039] The terms used in the utility model are only for the purpose of describing specific embodiments and are not intended to limit the utility model. Unless otherwise defined in this application document, the technical terms or scientific terms used in the utility model shall have the ordinary meaning understood by those of ordinary skill in the field to which the utility model belongs. The terms "first", "second" and similar words used in the specification and claims of the utility model do not denote any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "a" or "an" do not denote a quantity limitation, but mean that there is at least one. "Plural" or "several" means two or more. Unless otherwise indicated, words such as "upper / upper layer" and / or "lower / lower layer" are only for convenience of description and are not limited to a position or a spatial orientation. Words such as "comprising" or "including" mean that the elements or structures appearing before "comprising" or "including" cover the elements or structures listed after "comprising" or "including" and their equivalents, and do not exclude other elements or structures. Words such as "connected" or "coupled" are not limited to physical or mechanical connections, and may include electrical connections, whether direct or indirect. The singular forms "a", "the" and "said" used in the specification and appended claims of the utility model are also intended to include the plural forms unless the context clearly dictates otherwise. It should also be understood that the term "and / or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
[0040] For the convenience of unified description, the utility model defines a first direction, a second direction and a third direction hereinafter, and defines directions D1, D2 and D3 in the accompanying drawings of the specification. Among them, the first direction corresponds to D1 in the accompanying drawings of the specification (hereinafter simply referred to as the first direction D1), the first direction D1 is a direction parallel to the surface of the substrate, and the substrate is a base material for forming the chip packaging structure proposed by the utility model; the second direction corresponds to D2 in the accompanying drawings of the specification (hereinafter simply referred to as the second direction D2), the second direction D2 is perpendicular to the first direction D1 and the plane where the second direction D2 and the first direction D1 are located is parallel to the surface of the substrate; the third direction corresponds to D3 in the accompanying drawings of the specification (hereinafter simply referred to as the third direction D3), and the third direction D3 is perpendicular to the plane where the second direction D2 and the first direction D1 are located.
[0041] Please refer to Figures 1 - 2 and Figures 3a - 4d , wherein Figure 1 is a schematic cross-sectional structure diagram of the substrate structure in the prior art chip packaging structure, Figure 2 is Figure 1 a top view of the substrate structure in the prior art chip packaging structure shown inFigure 3a is Figure 2 a schematic structural diagram corresponding to the window 11 during the initial filling of the encapsulation material, Figure 3b is Figure 3a a partial enlarged view of a certain corner of the window 11 filled with the encapsulation material, Figures 4a - 4d then is Figure 2 a schematic structural diagram corresponding to the window 11 at different time periods during the filling process of the encapsulation material.
[0042] As Figure 1 and Figure 2 shown, the orthographic projection of the solder mask layer 1 in the prior art on the substrate at the window 11 in the non-filter chip area is a regular quadrilateral, such as a rectangle, and the range of the window 11 is larger than the orthographic projection 13 of the non-filter chip on the substrate. As Figures 4a - 4b shown, during the subsequent filling process of the encapsulation material, due to the viscous effect of the encapsulation material, when the encapsulation material contacts the edge area (i.e., the corner) of the window 11, it is subjected to a frictional force opposite to the flow direction (such as Figure 3b the flow direction F in Figure 3a and Figure 3b shown), resulting in a difference in the flow rate of the encapsulation material (i.e., the encapsulation layer 2) between the middle area and the edge area (the window corner) of the window 11, that is, the middle area of the window 11 is less resistant and has a faster flow rate, and is filled first, and finally the gas is squeezed into the edge area of the window 11 to form a cavity in the edge area of the window 11, as
[0043] To solve the above problems, the present invention proposes a chip packaging structure to optimize the shape of the window of the solder mask layer, that is, specifically optimize the right-angle corner of the window 11 with a regular quadrilateral shape in the prior art to a window with a gradually changing trend from one end point to the other end point of the first corner (the corner is non-right-angle), so as to utilize the characteristic that the frictional resistance of the encapsulation material at the corner position of the optimized window during the encapsulation process becomes smaller, that is, the difference in the flow rate of the encapsulation material between the middle position and the corner position of the window becomes smaller, to achieve reducing the filling defect caused by the corner of the cavity under the non-filter chip being wrapped by bubbles due to the uneven flow rate of the encapsulation material in the middle and edge of the window during the encapsulation process, that is, it is beneficial to improve the reliability of the product.
[0044] Those of ordinary skill in the art to which this application pertains should easily understand that the main difference between the chip packaging structure provided in the embodiments of the present utility model and the chip packaging structure in the prior art lies in the shape of the opening of the solder mask layer in the non-filter bearing area, while the other parts and components are the same. For example, the chip packaging structure provided in the embodiments of the present utility model also includes: a substrate 100, a non-filter bearing area 100A, a plurality of pads 110, a solder mask layer 120, a non-filter chip 130, and a plastic encapsulation layer 140. And for the sake of simplicity in description, the following description mainly details the differences in the openings of the solder mask layer in the chip packaging structure provided in the embodiments of the present utility model, and will not repeat the same parts. In addition, the same components in the embodiments of this application are labeled with the same reference numerals for easy comparison between the embodiments.
[0045] Generally speaking, a part of the solder mask layer 120 located on the non-filter bearing area 100A is provided with an opening 121 that exposes a part of the surface of the substrate 100 and the pads 110. The opening 121 has a plurality of first corners 1211, and the distance from any of the first corners 1211 to any of the pads 110 shows a gradual change trend from one end point 1211a (hereinafter simply referred to as the first end point 1211a) to the other end point 1211b (hereinafter simply referred to as the second end point 1211b). Among them, the gradual change trend can be that the contour of the first corner 1211 (that is, the contour from its first end point 1211a to the second end point 1211b) is an arc-shaped concave towards the direction of the pad 110, or, is an arc-shaped convex towards the direction away from the pad 110, or, is a hypotenuse-shaped connecting the first end point 1211a to the second end point 1211b to form a hypotenuse.
[0046] The following will introduce in detail the optimized design structure of the opening 121 provided by the present utility model through various examples of the orthographic projection of the optimized opening 121 on the substrate 100.
[0047] Please refer to Figure 5 , Figure 5 which is an example diagram of the orthographic projection of the optimized opening in the chip packaging structure provided in the embodiments of the present utility model on the substrate. As Figure 5 shown, the opening 121 of the solder mask layer 120 located on the non-filter bearing area 100A in this embodiment includes four first corners 1211 and four long sides 1212, and the polygon structure formed by connecting the four long sides 1212 and the four first corners 1211 end to end has an arc-shaped (such as circular) corner, and the arc-shaped boundary formed by connecting the first end point 1211a to the second end point 1211b of the first corner 1211 specifically protrudes towards the direction away from the pad 110.
[0048] Please refer toFigure 6 , Figure 6 This is another example diagram of the orthographic projection of the optimized opening on the substrate in the chip packaging structure provided in the embodiment of the present invention. As Figure 6 shown, the opening 121 of the solder mask layer 120 located on the non-filter bearing area 100A in this embodiment also includes four first corners 1211 and four long sides 1212, and the polygonal structure formed by connecting the four long sides 1212 and the four first corners 1211 end to end is also arc-shaped (such as circular) at the corners. However, the arc-shaped boundary formed by connecting the first end point 1211a to the second end point 1211b of the first corner 1211 in this embodiment is specifically recessed towards the direction of the pad 110.
[0049] Please refer to Figure 7 , Figure 7 This is another example diagram of the orthographic projection of the optimized opening on the substrate in the chip packaging structure provided in the embodiment of the present invention. As Figure 7 shown, the opening 121 of the solder mask layer 120 located on the non-filter bearing area 100A in this embodiment also includes four first corners 1211 and four long sides 1212, and the octagonal structure is formed by connecting the four long sides 1212 and the four first corners 1211 end to end. That is, the first end point 1211a to the second end point 1211b of the first corner 1211 in this embodiment is specifically a slant. Exemplarily, the range of the angle ɑ between the hypotenuse of the first corner 1211 and any connected long side 1212 in this embodiment can be 10° to 80°, that is, the value of ɑ can be 10°, 15°, 20°, 25°, 30°, 40°, 50°, 60°, 70° or 80°, etc.
[0050] Furthermore, each first corner 1211 of the opening 121 of the solder mask layer 120 located on the non-filter bearing area 100A in the embodiment of the present invention is obviously not a right angle. If the orthographic projection of the non-filter chip 130 located on the non-filter bearing area 100A on the substrate 100 is often a regular polygon, such as a rectangle, then the opening 121 and the orthographic projection of the non-filter chip 130 on the substrate 100 will inevitably partially overlap, and their orthographic projections at the opening 121 will also vary with Figures 5 - 7 shown, but not limited thereto. Exemplarily, for Figures 5 - 7 the various formations of the opening 121 shown, if the non-filter chip 130 has multiple second corners 131, then a part of the orthographic projection of the second corner 131 on the substrate 100 can be located outside the orthographic projection of the first corner 1211 on the substrate 100, such as Figures 8 - 10, or, a part of the orthographic projection of the second corner 131 on the substrate 100 may be located inside the orthographic projection of the first corner 1211 on the substrate 100, as Figure 11 shown, but not limited thereto.
[0051] It should be specifically noted that when the opening 121 of the solder mask layer 120 in the embodiment of the present invention is in the shape as Figures 5 - 7 shown above, during the subsequent filling process of the encapsulation material, the frictional force at each of the first corners 1211 (which can also be understood as the edge of the opening) of the opening 121 can be decomposed into components in two directions along the first direction D1 and the second direction D2. Among them, only the component in the second direction D2 causes an obstacle in the flowing direction of the encapsulation material, so that the resistance of the encapsulation material at the first corner 1211 of the opening 121 becomes smaller, thereby reducing the flow rate difference between the middle position and the first corner 1211 position of the opening 121 of the encapsulation material, and further improving the filling property of the encapsulation material, as Figures 12a - 12d shown, where Figures 12a - 12d is Figure 7 the schematic structural diagram corresponding to different time periods during the filling process of the encapsulation material in the opening 121 in
[0052] Obviously, the optimized opening 121 in the embodiment of the present invention can reduce the poor filling caused by the air bubbles wrapping the corners of the cavity under the non-filter chip due to the uneven flow rate of the encapsulation material in the middle and the edge of the opening during the encapsulation process, that is, it is beneficial to improve the reliability of the product.
[0052] In addition, the substrate 100 in the embodiment of the present invention is any suitable substrate material known in the art. For example, it may be a silicon substrate, a silicon-containing substrate (such as SiC, SiGe), or a silicon-on-insulator substrate or a substrate composed of other suitable materials, etc., but not limited thereto. The substrate 100 may further include a filter carrying area (not shown), and the filter carrying area may further be provided with components such as a filter chip (not shown), etc., but not limited thereto. The plurality of pads 110 may be separately disposed on the non-filter carrying area 100A. The solder mask layer 120 may be made of resin, solder mask green paint, dry film, etc., but not limited thereto. The non-filter chip 130 may be located on the non-filter carrying area 100A and includes a substrate and bumps (not shown) located on the substrate. The bumps are electrically connected to the pads 110. There is a cavity under the non-filter chip 130, and the cavity communicates with the opening 121. The encapsulation layer 140 may be located on the non-filter chip 130 and fill the cavity and the opening 121, and its material may include but not be limited to epoxy resin.
[0053] It should be noted that the methods, processes, and materials involved in the present utility model are all prior arts.
[0054] In summary, in the chip packaging structure provided by the present utility model, specifically, the window opening (with right-angled corners) of the solder mask layer in the prior art with a regular quadrilateral shape is optimized to a window opening (with non-right-angled corners) in which the first corner shows a gradual change trend from one endpoint to the other endpoint. Then, by utilizing the characteristic that the frictional resistance of the encapsulation material becomes smaller at the corner positions of the optimized window opening during the encapsulation process, that is, the flow velocity difference of the encapsulation material at the middle position and the corner positions of the window opening becomes smaller, it is possible to reduce the poor filling caused by the corners of the cavity under the non-filter chip being wrapped by air bubbles due to the uneven flow velocity of the encapsulation material in the middle and at the edges of the window opening during the encapsulation process, which is beneficial to improving the reliability of the product.
[0055] The above description is only a description of the preferred embodiments of the present utility model, and does not limit the scope of the present utility model in any way. Any changes and modifications made by those of ordinary skill in the art of the present utility model based on the above disclosure shall fall within the protection scope of the claims.
Claims
1. A chip packaging structure, characterized in that, Comprising: A substrate, including a non-filter bearing area; A plurality of pads, arranged separately on the non-filter bearing area; A solder mask layer, located on the non-filter bearing area, and provided with an opening window exposing a partial surface of the substrate and the pads. The opening window has a plurality of first corners, and the distance from the first corners to any one of the pads shows a gradually changing trend from one end point to the other end point.
2. The chip packaging structure according to claim 1, wherein, The opening window has four of the first corners, and the cross-sectional shape of the opening window in the direction parallel to the surface of the substrate is an irregular polygon structure formed by connecting the four long sides and the four first corners end to end.
3. The chip packaging structure according to claim 2, wherein The contour of the first corner is an arc-shaped concave towards the direction close to the pad.
4. The chip packaging structure according to claim 2, wherein, The contour of the first corner is an arc-shaped convex towards the direction away from the pad.
5. The chip packaging structure according to claim 2, wherein The contour of the first corner is a hypotenuse-shaped connecting its two end points.
6. The chip packaging structure according to claim 5, wherein, There is an included angle between the first corner with a hypotenuse-shaped contour and the long side connected thereto, and the included angle is 10° to 80°.
7. The chip packaging structure according to claim 2, wherein Further comprising: A non-filter chip, located on the non-filter bearing area, and including a substrate and bumps located on the substrate. The bumps are electrically connected to the pads. There is a cavity below the non-filter chip, and the cavity communicates with the opening window.
8. The chip packaging structure according to claim 7, characterized in that, The non-filter chip has a plurality of second corners; the orthographic projection of the second corners on the substrate partially overlaps with the orthographic projection of the first corners on the substrate.
9. The chip package structure as described in claim 8, wherein, A part of the orthographic projection of the second corners on the substrate is located outside the orthographic projection of the first corners on the substrate.
10. The chip package structure according to claim 8, wherein A part of the orthographic projection of the second corners on the substrate is located inside the orthographic projection of the first corners on the substrate.
11. The chip package structure according to claim 7, wherein Further comprising: A plastic encapsulation layer, located on the non-filter chip, and filling the cavity and the opening window.