Zero-delay switching parallel redundant network chip

Abstract

The utility model relates to the technical field of network transmission, in particular to a zero-delay switching parallel redundant network chip, which comprises an electronic circuit board, an FPGA (Field Programmable Gate Array) chip, an indicating lamp, a power supply and a heat dissipation device, the FPGA chip, the indicating lamp, the power supply and the heat dissipation device are fixed on the electronic circuit board; a connecting plug is arranged on the FPGA chip, a jack is formed in the electronic circuit board, the connecting plug is matched with the jack, and electric connecting sheets are arranged in the connecting plug and the jack; and the FPGA chip at least comprises two RGMII (Regularly Gateway Media Independent Interface) interfaces and four 1000BASE-X interfaces. The zero-delay switching parallel redundant network chip can realize dual-redundancy communication, and achieves the technical effect of improving the reliability of the network.

Description

Technical Field

[0001] The utility model relates to the technical field of network transmission, and particularly relates to a zero-delay switching parallel redundant network chip. Background Art

[0002] With the rapid development of network technology and computing technology, the demand for high-performance network devices is increasing day by day. In network devices, network chips play a crucial role, and they are responsible for the processing and forwarding of data packets. However, in the existing network chip technology, there are some significant defects in achieving high reliability and low latency. For example, there is a certain delay in the data packet processing process, especially in the case of high load, this delay may lead to a decrease in data transmission efficiency; at the same time, the current network chips usually lack an effective redundancy mechanism. Once a certain component fails, the stability of the entire system may be affected, resulting in data loss or transmission interruption.

[0003] Therefore, there is an urgent need for a zero-delay switching parallel redundant network chip at present. Summary of the Utility Model

[0004] (I) Technical Problems to be Solved

[0005] In view of the above-mentioned shortcomings and deficiencies of the prior art, the utility model provides a zero-delay switching parallel redundant network chip, which solves the technical problems of low reliability and low data transmission efficiency of the network chips in the prior art.

[0006] (II) Technical Solutions

[0007] In order to achieve the above object, the main technical solutions adopted by the utility model include:

[0008] An embodiment of the utility model provides a zero-delay switching parallel redundant network chip, including:

[0009] An electronic circuit board, an FPGA chip, an indicator light, a power supply, and a heat dissipation device;

[0010] The FPGA chip, the indicator light, the power supply, and the heat dissipation device are fixed on the electronic circuit board;

[0011] A plug connector is arranged on the FPGA chip, a jack is arranged on the electronic circuit board, the plug connector is matched with the jack, and electrical connection pieces are arranged in both the plug connector and the jack.

[0012] Optionally, the FPGA chip includes:

[0013] A network switching element, at least two communication elements, at least two CPU elements, at least two RGMII interfaces, and at least four 1000BASE-X interfaces;

[0014] The RGMII interfaces correspond to the communication components one by one, and each RGMII interface is electrically connected to the corresponding communication component; the communication components correspond to the CPU components one by one, and each communication component is electrically connected to the corresponding CPU component; the at least two CPU components are electrically connected to the network switching component; the network switching component is electrically connected to at least four 1000BASE-X interfaces.

[0015] Optionally, the FPGA chip further includes:

[0016] A DMA accelerator;

[0017] The DMA accelerator is electrically connected to the CPU component.

[0018] Optionally, the network chip further includes:

[0019] A one-key switch power button;

[0020] The one-key switch power button is electrically connected to the power supply.

[0021] Optionally, the network chip further includes:

[0022] A first connector and a second connector;

[0023] One end of the first connector and the second connector is fixedly connected to the FPGA chip, and the other end is fixedly connected to the electronic circuit board;

[0024] The first connector and the second connector are high-speed board-mounted connectors, and the first connector and the second connector have the same size.

[0025] Optionally, the heat dissipation device includes: a micro-scale heat pipe and a heat sink;

[0026] One end of the micro-scale heat pipe is fixed on the FPGA chip, and the other end is fixed on the heat sink; the heat sink is fixed on the electronic circuit board;

[0027] The diameter of the micro-scale heat pipe is 0.5 mm to 1.0 mm.

[0028] Optionally, the heat sink is a PCM heat sink, and the shape of the heat sink is fin-shaped or trapezoidal.

[0029] Optionally, the indicator lights include: at least four connection status indicator lights;

[0030] Each 1000BASE-X interface corresponds to a connection status indicator light; each connection status indicator light is wire-connected to each 1000BASE-X interface.

[0031] Optionally, the power supply is a 3.3V power supply; the power supply is electrically connected to the FPGA chip.

[0032] Optionally, the network chip further includes: a quantum random number generator;

[0033] The quantum random number generator is fixed on the electronic circuit board and is electrically connected to the FPGA chip.

[0034] (III) Advantageous Effects

[0035] The advantageous effects of the present utility model are as follows: For a zero-delay switching parallel redundant network chip of the present utility model, since an FPGA chip with at least two RGMII interfaces and four 1000BASE-X interfaces is provided on the zero-delay switching parallel redundant network chip, compared with the prior art, redundant communication can be realized, and the technical effects of improving the reliability of the network and the data transmission efficiency are achieved. Description of the Drawings

[0036] Figure 1 It is a schematic structural diagram of the zero-delay switching parallel redundant network chip according to an embodiment of the present utility model.

[0037]

Description of the Reference Numerals

[0038] 1: Heat sink; 2: Microscale heat pipe; 3: First connector; 4: Second connector; 5: Power supply; 6: Indicator light; 7: Electronic circuit board; 8: FPGA chip. Detailed Embodiment

[0039] In order to better explain the present utility model for easy understanding, the present utility model will be described in detail below with reference to the drawings through specific embodiments.

[0040] A zero-delay switching parallel redundant network chip proposed by the present utility model is to solve the technical problems of high latency of existing network chips, resulting in low data transmission efficiency and low reliability. The present utility model provides an FPGA chip with at least two RGMII interfaces and four 1000BASE-X interfaces, improving the reliability of the network.

[0041] To better understand the above technical solution, the exemplary embodiments of the present utility model will be described in more detail below with reference to the drawings. Although the exemplary embodiments of the present utility model are shown in the drawings, it should be understood that the present utility model can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more clear and thorough understanding of the present utility model and to fully convey the scope of the present utility model to those skilled in the art.

[0042] Description of the Specific Embodiment

[0043] Embodiment 1

[0044] See Figure 1 , a zero-delay switching parallel redundant network chip according to an embodiment of the present invention includes:

[0045] An electronic circuit board 7, an FPGA chip 8, an indicator light 6, a power supply 5, and a heat dissipation device;

[0046] The FPGA chip 8, the indicator light 6, the power supply 5, and the heat dissipation device are fixed on the electronic circuit board 7;

[0047] There is a plug connector on the FPGA chip 8, and a jack on the electronic circuit board 7. The plug connector matches the jack, and electrical connection pieces are provided in both the plug connector and the jack.

[0048] In this embodiment, the FPGA chip 8 includes:

[0049] A network switching element, at least two communication elements, at least two CPU elements, at least two RGMII interfaces, and at least four 1000BASE-X interfaces;

[0050] The RGMII interfaces correspond to the communication elements one by one, and each RGMII interface is electrically connected to the corresponding communication element; the communication elements correspond to the CPU elements one by one, and each communication element is electrically connected to the corresponding CPU element; at least two CPU elements are electrically connected to the network switching element; the network switching element is electrically connected to at least four 1000BASE-X interfaces.

[0051] In a specific implementation process, the FPGA chip 8 includes at least two RGMII interfaces and four 1000BASE-X interfaces. A PRP (Parallel Redundancy Protocol) protocol processing element is integrated on the CPU element of the FPGA chip 8; PRP is a redundant Ethernet protocol proposed by the industrial Ethernet standard IEC62439-3, aiming to achieve seamless switching of dual network interfaces and zero fault recovery time.

[0052] After receiving a data packet, the PRP protocol processing element will copy the data packet into two copies and respectively encapsulate redundant control tags. The copied data packets are respectively sent to two independent networks through two redundant 1000BASE-X interfaces; after the receiving end receives the two data packets, it calls the redundant processing algorithm, uploads the first-arrived one of the two data packets to the upper network card, and discards the later-arrived data packet.

[0053] With the above settings, when a certain interface fails or the network connected to a certain interface fails, another RGMII interface of the FPGA chip 8 can receive data packets normally, thus having no impact on communication control. Moreover, the switching time during a failure is 0, and there will be no phenomenon of data packet loss.

[0054] In this embodiment, the FPGA chip 8 does not require a complex soldering process and only needs to be plugged and unplugged to complete, thus greatly reducing the maintenance cost and time of the zero-delay switching parallel redundant network chip.

[0055] In this embodiment, the FPGA chip 8 further includes:

[0056] DMA accelerator;

[0057] The DMA accelerator is electrically connected to the CPU component.

[0058] In the specific implementation process, the DMA accelerator is connected to the CPU component through the PCIE bus. It can transfer data from the RGMII to the memory without the intervention of the CPU component, thus significantly reducing the load of the CPU component and allowing the CPU component to focus on executing more complex tasks. At the same time, by using the DMA accelerator for data transfer, the delay caused by CPU scheduling can be reduced, thereby improving the response speed of the entire chip.

[0059] In the specific implementation process, a low-power chip component is also integrated on the FPGA chip 8, and the low-power chip component is connected to the CPU component through the JTAG bus.

[0060] The low-power chip component can enter the sleep mode according to the actual situation, enabling the FPGA chip 8 to operate at an extremely low power consumption, significantly reducing the power consumption of the zero-delay switching parallel redundant network chip, and thus extending the service life of the entire zero-delay switching parallel redundant network chip.

[0061] In this embodiment, the zero-delay switching parallel redundant network chip further includes:

[0062] One-key switch power button;

[0063] The one-key switch power button is electrically connected to the power supply;

[0064] In the specific implementation process, when the one-key switch power button is pressed, the power supply will be directly started, and the entire zero-delay switching parallel redundant network chip will immediately resume power supply, without the need to go through the process of slow power-on reset, improving the overall work efficiency and saving time.

[0065] In this embodiment, the zero-delay switching parallel redundant network chip further includes:

[0066] The first connector 3 and the second connector 4;

[0067] One end of the first connector 3 and the second connector 4 is fixedly connected to the FPGA chip 8, and the other end is fixedly connected to the electronic circuit board 7.

[0068] Among them, the first connector 3 and the second connector 4 are high-speed board-mounted connectors, and the first connector 3 and the second connector 4 have the same size.

[0069] In this embodiment, the first connector 3 and the second connector 4 are used to establish a high-speed data channel between the FPGA chip 8 and the electronic circuit board 7; at the same time, the first connector 3 and the second connector 4 are high-speed board-mounted connectors, which can ensure the rate and stability of data transmission.

[0070] In addition, selecting the first connector 3 and the second connector 4 with the same size helps to maintain the consistency of the design, facilitates the integration with other standard components, and improves the compatibility and interchangeability of the zero-delay switching parallel redundant network chip.

[0071] In this embodiment, the heat dissipation device includes: a microscale heat pipe 2 and a heat sink 1;

[0072] One end of the microscale heat pipe 2 is fixed on the FPGA chip 8, and the other end is fixed on the heat sink 1; the heat sink 1 is fixed on the electronic circuit board 7;

[0073] The diameter of the microscale heat pipe 2 is 0.5 mm to 1.0 mm.

[0074] In a specific implementation process, the heat sink 1 is a PCM heat sink, and the shape of the heat sink 1 is fin-shaped or trapezoidal.

[0075] Setting the shape of the heat sink 1 to be fin-shaped or trapezoidal increases the heat dissipation area, improves the air flow frequency, and further enhances the heat dissipation performance.

[0076] In a specific implementation process, one end of the microscale heat pipe 2 is directly fixed on the FPGA chip 8, and the other end is connected to the PCM heat sink, forming a direct heat conduction path from the FPGA chip 8 to the heat sink 1. The heat sink 1 itself is fixed on the electronic circuit board 7 to ensure the stability and reliability of the entire heat dissipation system.

[0077] The microscale heat pipe 2 contains a working liquid. When one end is heated, the liquid evaporates to form steam, and the steam quickly transfers heat to the other end, and then cools back to the liquid state at the heat sink 1, repeating the cycle to achieve efficient heat energy transfer.

[0078] In this embodiment, the indicator light 6 includes: at least four connection status indicator lights;

[0079] Each 1000BASE-X interface corresponds to a connection status indicator light; each connection status indicator light is electrically connected to each 1000BASE-X interface wire.

[0080] In the actual design, each 1000BASE-X interface corresponds to a connection status indicator light, enabling the operator to timely understand the connection status of each 1000BASE-X interface, which is extremely beneficial for network management and fault troubleshooting.

[0081] In this embodiment, the connection status indicator light uses an LED as the light source, and can intuitively reflect the active status and health status of the interface through the color and brightness of the LED.

[0082] In the specific implementation process, the power supply 5 is a 3.3V power supply; the power supply 5 is electrically connected to the FPGA chip 8.

[0083] In this embodiment, the zero-delay switching parallel redundant network chip further includes: a quantum random number generator;

[0084] The quantum random number generator is fixed on the electronic circuit board 7 and is electrically connected to the FPGA chip 8.

[0085] Due to its true randomness, the quantum random number generator in this embodiment can significantly improve the security of the encryption algorithm and protect the confidentiality and integrity of network data.

[0086] The applicable temperature range of the zero-delay switching parallel redundant network chip in this embodiment is -40°C to +65°C, the size is 50mm × 40mm, and the board thickness is 1.6mm.

[0087] A zero-delay switching parallel redundant network chip in this embodiment uses an FPGA chip 8 with at least two RGMII interfaces and four 1000BASE-X interfaces, which can achieve dual-redundancy communication and improve the reliability of the network; at the same time, it can use its own multi-core design ability to build multiple sub-channels with independent link processing, that is, each sub-channel has its own kernel resources, thereby forming a distributed processing architecture. For large-bandwidth network traffic, a DMA accelerator is used to accelerate the data transmission speed, significantly reducing the power consumption, enhancing the scalability, and improving the real-time performance and stability.

[0088] A zero-delay switching parallel redundant network chip in this embodiment can achieve dual-redundancy communication, achieving the technical effect of improving the reliability of the network.

[0089] In the description of the present utility model, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the present utility model, "a plurality of" means two or more unless otherwise specifically defined.

[0090] In the present utility model, unless otherwise clearly specified and defined, the terms "mounted", "connected", "connected to", "fixed", etc. shall be construed in a broad sense. For example, it may be a fixed connection, a detachable connection, or integrated; it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium; it may be the communication inside two elements or the interaction relationship between two elements. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0091] In the present utility model, unless otherwise clearly specified and defined, when the first feature is "on" or "under" the second feature, it may be that the first and second features are in direct contact, or the first and second features are indirectly in contact through an intermediate medium. Moreover, when the first feature is "above", "over" and "on top of" the second feature, it may be that the first feature is directly above or obliquely above the second feature, or merely indicates that the first feature is at a higher level than the second feature in terms of horizontal height. When the first feature is "under", "beneath" and "underneath" the second feature, it may be that the first feature is directly below or obliquely below the second feature, or merely indicates that the first feature is at a lower level than the second feature in terms of horizontal height.

[0092] In the description of this specification, the descriptions of terms such as "one embodiment", "some embodiments", "embodiment", "example", "specific example" or "some examples" mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present utility model. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without contradiction, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0093] Although the embodiments of the present utility model have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present utility model. Those of ordinary skill in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present utility model.

Claims

1. A zero-delay switching parallel redundant network chip, characterized in that Including: An electronic circuit board (7), an FPGA chip (8), an indicator light (6), a power supply (5), and a heat dissipation device; The FPGA chip (8), the indicator light (6), the power supply (5), and the heat dissipation device are fixed on the electronic circuit board (7); A plug connector is provided on the FPGA chip (8), a jack is provided on the electronic circuit board (7), the plug connector matches the jack, and electrical connection pieces are provided in both the plug connector and the jack.

2. The zero-delay switching parallel redundant network chip according to claim 1, wherein The FPGA chip (8) includes: A network switching element, at least two communication elements, at least two CPU elements, at least two RGMII interfaces, and at least four 1000BASE-X interfaces; The RGMII interfaces correspond to the communication elements one by one, and each RGMII interface is electrically connected to the corresponding communication element; the communication elements correspond to the CPU elements one by one, and each communication element is electrically connected to the corresponding CPU element; the at least two CPU elements are electrically connected to the network switching element; the network switching element is electrically connected to at least four 1000BASE-X interfaces.

3. The zero-delay switching parallel redundant network chip according to claim 2, wherein The FPGA chip (8) further includes: A DMA accelerator; The DMA accelerator is electrically connected to the CPU element.

4. The zero-delay switching parallel redundant network chip according to claim 1, characterized in that, The network chip further includes: A one-key switch power button; The one-key switch power button is electrically connected to the power supply.

5. The zero-latency switching parallel redundant network chip according to claim 1, characterized in that, The network chip further includes: A first connector (3) and a second connector (4); One end of the first connector (3) and the second connector (4) is fixedly connected to the FPGA chip (8), and the other end is fixedly connected to the electronic circuit board (7); The first connector (3) and the second connector (4) are high-speed board-mounted connectors, and the first connector (3) and the second connector (4) have the same size.

6. The zero-delay switching parallel redundant network chip according to claim 1, characterized in that The heat dissipation device includes: a microscale heat pipe (2) and a heat sink (1); One end of the microscale heat pipe (2) is fixed on the FPGA chip (8), and the other end is fixed on the heat sink (1); the heat sink (1) is fixed on the electronic circuit board (7); The diameter of the microscale heat pipe (2) is 0.5 mm to 1.0 mm.

7. The zero-delay switching parallel redundant network chip according to claim 6, characterized in that The heat sink (1) is a PCM heat sink, and the shape of the heat sink (1) is fin-shaped or trapezoidal.

8. The zero-delay switching parallel redundant network chip according to claim 1, characterized in that The indicator light (6) includes: at least four connection status indicator lights; Each 1000BASE-X interface corresponds to a connection status indicator light; each connection status indicator light is electrically connected to each 1000BASE-X interface.

9. The zero-delay switching parallel redundant network chip according to claim 1, characterized in that The power supply (5) is a 3.3V power supply; the power supply (5) is electrically connected to the FPGA chip (8).

10. The zero-delay switching parallel redundant network chip according to claim 1, characterized in that, The network chip further includes: a quantum random number generator; The quantum random number generator is fixed on the electronic circuit board (7) and is electrically connected to the FPGA chip (8).

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