CPU chip and multi-memory slot arrangement structure and mainboard

Abstract

The utility model discloses a CPU chip and multi-memory slot arrangement structure and a mainboard, and relates to the technical field of memory bank system-level testing. The arrangement structure comprises a CPU chip and a plurality of memory slots, and pins of the CPU chip comprise a plurality of memory slot signal groups which are in one-to-one correspondence with the memory slots and are connected with the memory slots; the plurality of memory slots are sequentially arranged along the direction far away from the CPU chip, and the arrangement sequence of the plurality of memory slots from near to far is consistent with the arrangement sequence of the plurality of memory slot signal groups from inside to outside, so that the lengths of all wires from the CPU chip to the plurality of memory slots can be more balanced (i.e., the long wires are shortened, and the wires are shortened; therefore, the performance difference between the far-end memory bank and the near-end memory bank can be balanced, the performance consistency of the memory banks of the memory bank system-level test mainboard is improved, and practical application and popularization are facilitated.

Description

Technical Field

[0001] The utility model belongs to the technical field of system-level testing of memory modules, and particularly relates to an arrangement structure of a CPU chip and multiple memory slots and a motherboard. Background Art

[0002] Currently, on motherboards such as the model 5MRX, the wiring from the CPU (Central Processing Unit) chip to 8 memory slots is designed according to the PCB (Printed Circuit Board) design standard of Intel Corporation: that is, the wiring length from the CPU chip to the most distant memory slot is the longest, and the wiring length to the nearest memory slot is the shortest (of course, the aforementioned PCB design standard also covers many other parameters, such as line spacing, impedance control, lamination, and simulation, etc.).

[0003] In actual measurement, it will be found that the remote memory modules (i.e., the memory modules plugged into the memory slots from the CPU chip to the remote end) and the proximal memory modules (i.e., the memory modules plugged into the memory slots from the CPU chip to the proximal end) divided based on the distance relationship with the CPU chip perform differently in terms of operating frequency (it doesn't mean that the shorter the line, the higher the frequency, and the longer the line, the lower the frequency, because there are effects such as transmission, reflection, and interference), that is, there are performance differences between the remote and proximal memory modules. Therefore, under the condition that other parameters except the wiring length remain unchanged, how to make the aforementioned remote memory modules and proximal memory modules closer to the same frequency in order to improve the performance consistency of the memory modules on the motherboard for system-level testing of memory modules (for the motherboard for system-level testing of memory modules, this consistency is more important than overclocking) is an urgent research topic for those skilled in the art. Summary of the Utility Model

[0004] The purpose of the utility model is to provide an arrangement structure of a CPU chip and multiple memory slots and a motherboard, so as to solve the problem that the wiring from the CPU chip to multiple memory slots designed according to the PCB design standard of Intel Corporation will cause performance differences between the remote and proximal memory modules.

[0005] In order to achieve the above purpose, the utility model adopts the following technical solutions:

[0006] In the first aspect, an arrangement structure of a CPU chip and multiple memory slots is provided, including a CPU chip and multiple memory slots. Among them, the pins of the CPU chip include multiple memory slot signal groups that are in one-to-one correspondence with and connected to the multiple memory slots;

[0007] The multiple memory slots are arranged in sequence in a direction away from the CPU chip, and the arrangement order of the multiple memory slots from near to far is the same as the arrangement order of the multiple memory slot signal groups from inside to outside.

[0008] Based on the above-mentioned utility model content, a new arrangement scheme of a CPU chip and multiple memory slots is provided, that is, it includes a CPU chip and multiple memory slots. Among them, the pins of the CPU chip include multiple memory slot signal groups that correspond to and are connected to the multiple memory slots one by one; the multiple memory slots are arranged in sequence in a direction away from the CPU chip, and the arrangement order of the multiple memory slots from near to far is the same as the arrangement order of the multiple memory slot signal groups from inside to outside. In this way, the lengths of all the traces from the CPU chip to the multiple memory slots can be made more balanced (that is, the long traces are shortened, and the short traces are lengthened), thereby balancing the performance differences of the proximal and distal memory modules, improving the memory performance consistency of the memory module system-level test motherboard, and facilitating practical application and promotion.

[0009] In a possible design, the CPU chip uses ball grid array packaging technology for pin distribution.

[0010] In a possible design, the CPU chip uses an Intel processor chip with the model Sapphire Rapids W-2400 / 3400.

[0011] In a possible design, when the pins of the CPU chip include multiple first memory slot signal groups and multiple second memory slot signal groups that are arranged from inside to outside on the same side of the chip, the arrangement structure includes multiple first memory slots that correspond to and are connected to the multiple first memory slot signal groups one by one and multiple second memory slots that correspond to and are connected to the multiple second memory slot signal groups one by one;

[0012] The multiple first memory slots are arranged in sequence in a first direction away from the CPU chip, and the arrangement order of the multiple first memory slots from near to far is the same as the arrangement order of the multiple first memory slot signal groups from inside to outside;

[0013] The multiple second memory slots are arranged in sequence in a second direction away from the CPU chip, and the arrangement order of the multiple second memory slots from near to far is the same as the arrangement order of the multiple second memory slot signal groups from inside to outside, where the second direction and the first direction are a pair of opposite directions.

[0014] In a possible design, when the CPU chip uses an Intel processor chip of model Sapphire Rapids W-2400 / 3400, the multiple first memory slot signal groups include memory slot signal group D, memory slot signal group C, memory slot signal group B, and memory slot signal group A arranged in sequence from the inside to the outside, and the multiple second memory slot signal groups include memory slot signal group H, memory slot signal group G, memory slot signal group F, and memory slot signal group E arranged in sequence from the inside to the outside;

[0015] The multiple first memory slots include memory slot D corresponding to and connected to the memory slot signal group D, memory slot C corresponding to and connected to the memory slot signal group C, memory slot B corresponding to and connected to the memory slot signal group B, and memory slot A corresponding to and connected to the memory slot signal group A. The memory slot D, the memory slot C, the memory slot B, and the memory slot A are arranged in sequence along the first direction;

[0016] The multiple second memory slots include memory slot H corresponding to and connected to the memory slot signal group H, memory slot G corresponding to and connected to the memory slot signal group G, memory slot F corresponding to and connected to the memory slot signal group F, and memory slot E corresponding to and connected to the memory slot signal group E. The memory slot H, the memory slot G, the memory slot F, and the memory slot E are arranged in sequence along the second direction.

[0017] In a possible design, multiple traces located between the multiple memory slot signal groups and the multiple memory slots have the same parameters other than length.

[0018] In a possible design, the other parameters include line pitch, width, thickness, and / or material.

[0019] In a possible design, the inner traces located between the multiple memory slot signal groups and the multiple memory slots cross the outer traces by combining signal layering and vias. Here, the inner traces refer to the traces whose two ends are respectively and correspondingly connected to the third memory slot signal group and the third memory slot, and the outer traces refer to the traces whose two ends are respectively and correspondingly connected to the fourth memory slot signal group and the fourth memory slot. The third memory slot signal group and the fourth memory slot signal group both belong to the multiple memory slot signal groups, and the third memory slot signal group is closer to the inside than the fourth memory slot signal group. The third memory slot and the fourth memory slot both belong to the multiple memory slots, and the third memory slot is closer to the CPU chip than the fourth memory slot.

[0020] In a possible design, the inner traces between the multiple memory slot signal groups and the multiple memory slots have more serpentine segments than the outer traces, where the inner traces refer to the traces whose two ends are respectively and correspondingly connected to the third memory slot signal group and the third memory slot, the outer traces refer to the traces whose two ends are respectively and correspondingly connected to the fourth memory slot signal group and the fourth memory slot, the third memory slot signal group and the fourth memory slot signal group both belong to the multiple memory slot signal groups and the third memory slot signal group is closer to the inside than the fourth memory slot signal group, and the third memory slot and the fourth memory slot both belong to the multiple memory slots and the third memory slot is closer to the CPU chip than the fourth memory slot.

[0021] In a second aspect, a motherboard is further provided, which includes a printed circuit board and the layout structure as described in the first aspect or any possible design in the first aspect, where the layout structure is located on the printed circuit board.

[0022] Beneficial effects of the above solution:

[0023] (1) The present invention creatively provides a new layout solution for a CPU chip and multiple memory slots, that is, it includes a CPU chip and multiple memory slots, where the pins of the CPU chip include multiple memory slot signal groups that are respectively and correspondingly connected to the multiple memory slots; the multiple memory slots are arranged in sequence along the direction away from the CPU chip, and the arrangement order of the multiple memory slots from near to far is the same as the arrangement order of the multiple memory slot signal groups from inside to outside, so that the lengths of all traces from the CPU chip to the multiple memory slots can be more balanced (that is, the long traces are shortened and the short traces are extended), thereby balancing the performance differences of the near-end and far-end memory modules and improving the memory performance consistency of the memory module system-level test motherboard;

[0024] (2) It can also break the PCB design standard of Intel Corporation and completely reverse the order of the memory slot layout on the motherboard, so that designers do not need to care about the speed and frequency of the best memory module, but improve the performance of the worst memory module, achieving the effect of "filling the short board of the bucket", which is convenient for practical application and promotion. Description of the Drawings

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0026] Figure 1Schematic diagram of the traditional layout structure of the CPU chip and multiple memory slots provided by the prior art.

[0027] Figure 2 Schematic diagram of the new layout structure of the CPU chip and multiple memory slots provided by the embodiments of the present application.

[0028] Figure 3 PCB board design comparison diagram of the traditional and new traces from the memory slot signal group E of the CPU chip to the memory slot E provided by the embodiments of the present application. Among them, Figure 3 (a) in shows the PCB board design diagram of the traditional trace from the memory slot signal group E of the CPU chip to the memory slot E. Figure 3 (b) in shows the PCB board design diagram of the new trace from the memory slot signal group E of the CPU chip to the memory slot E.

[0029] Figure 4 PCB board design comparison diagram of the traditional and new traces from the memory slot signal group H of the CPU chip to the memory slot H provided by the embodiments of the present application. Among them, Figure 4 (a) in shows the PCB board design diagram of the traditional trace from the memory slot signal group H of the CPU chip to the memory slot H. Figure 4 (b) in shows the PCB board design diagram of the new trace from the memory slot signal group H of the CPU chip to the memory slot H.

[0030] Figure 5 S-parameter simulation waveform comparison diagram of the traditional and new traces from the memory slot signal group of the CPU chip to the memory slot provided by the embodiments of the present application.

[0031] Figure 6 Schematic diagram of the structure of the main board provided by the embodiments of the present application. Detailed implementation manners

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the present invention in combination with the drawings and the description of the embodiments or the prior art. Obviously, the following description of the structure of the drawings is only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other embodiments can be obtained based on these embodiments. It should be noted here that the description of these embodiments is used to help understand the present invention, but does not constitute a limitation to the present invention.

[0033] It should be understood that although terms such as first and second may be used herein to describe various objects, these objects should not be limited by these terms. These terms are only used to distinguish one object from another. For example, the first object may be referred to as the second object, and similarly, the second object may be referred to as the first object, without departing from the scope of the exemplary embodiments of the present utility model.

[0034] It should be understood that for the term "and / or" that may appear herein, it is merely a description of the association relationship between associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, B exists alone, or A and B exist simultaneously, etc. There are three such cases; for another example, A, B, and / or C can represent any one of A, B, and C or any combination of them; for the term " / and" that may appear herein, it describes another association relationship between objects, indicating that there can be two relationships. For example, A / and B can represent: A exists alone or A and B exist simultaneously, etc. There are two such cases; in addition, for the character " / " that may appear herein, generally it represents that the associated objects before and after are in an "or" relationship.

[0035] Embodiment 1

[0036] As Figures 2 to 5 shown, the arrangement structure of the CPU chip and multiple memory slots provided in this embodiment includes, but is not limited to, a CPU chip and multiple memory slots, etc. Among them, the pins of the CPU chip include, but are not limited to, multiple memory slot signal groups that correspond to and are connected to the multiple memory slots one by one; the multiple memory slots are arranged in sequence along the direction away from the CPU chip, and the arrangement order of the multiple memory slots from near to far is the same as the arrangement order of the multiple memory slot signal groups from inside to outside.

[0037] As Figure 2 shown, in the specific structure of the arrangement structure, both the CPU chip and the multiple memory slots are conventional configurations of an existing motherboard. Among them, the CPU chip specifically but not limited to uses an Intel processor chip with a model of Sapphire Rapids W-2400 / 3400 (i.e., the Xeon W-2400 or Xeon W-3400 model), and the CPU chip specifically but not limited to uses ball grid array packaging technology for pin distribution; the memory slots are used for plugging memory modules and can be specifically implemented by using existing slot products conventionally. The multiple memory slot signal groups can be a batch (i.e., Figure 2The memory slot signal groups D, C, B, and A in [ ] are in one batch, or the memory slot signal groups H, G, F, and E are in another batch; at this time, the multiple memory slots also have one batch, that is, the memory slot D corresponding to and connected to the memory slot signal group D, the memory slot C corresponding to and connected to the memory slot signal group C, the memory slot B corresponding to and connected to the memory slot signal group B, and the memory slot A corresponding to and connected to the memory slot signal group A are in one batch, or the memory slot H corresponding to and connected to the memory slot signal group H, the memory slot G corresponding to and connected to the memory slot signal group G, the memory slot F corresponding to and connected to the memory slot signal group F, and the memory slot E corresponding to and connected to the memory slot signal group E are in another batch) and are arranged on one side of the CPU chip. There can also be two batches (at this time, the multiple memory slots also have two batches and correspond to them one by one) and are arranged together on the same side of the CPU chip or separately on different sides of the CPU chip. There can also be multiple batches (at this time, the multiple memory slots also have multiple batches and correspond to them one by one) and are separately arranged on different sides of the CPU chip, and so on. Specifically, as Figure 2 shown, when the pins of the CPU chip include multiple first memory slot signal groups and multiple second memory slot signal groups arranged from the inside to the outside on the same side of the chip, the arrangement structure includes multiple first memory slots corresponding to and connected to the multiple first memory slot signal groups one by one and multiple second memory slots corresponding to and connected to the multiple second memory slot signal groups one by one; the multiple first memory slots are arranged in sequence along a first direction away from the CPU chip, and the arrangement order from near to far of the multiple first memory slots is the same as the arrangement order from the inside to the outside of the multiple first memory slot signal groups; the multiple second memory slots are arranged in sequence along a second direction away from the CPU chip, and the arrangement order from near to far of the multiple second memory slots is the same as the arrangement order from the inside to the outside of the multiple second memory slot signal groups, where the second direction and the first direction are a pair of opposite directions.

[0038] such as Figure 2As shown, for example, when the CPU chip uses an Intel processor chip with the model Sapphire Rapids W-2400 / 3400, the multiple first memory slot signal groups include memory slot signal group D, memory slot signal group C, memory slot signal group B, and memory slot signal group A arranged in sequence from inside to outside, and the multiple second memory slot signal groups include memory slot signal group H, memory slot signal group G, memory slot signal group F, and memory slot signal group E arranged in sequence from inside to outside; the multiple first memory slots include memory slot D corresponding to and connected to the memory slot signal group D, memory slot C corresponding to and connected to the memory slot signal group C, memory slot B corresponding to and connected to the memory slot signal group B, and memory slot A corresponding to and connected to the memory slot signal group A, and the memory slot D, the memory slot C, the memory slot B, and the memory slot A are arranged in sequence along the first direction; the multiple second memory slots include memory slot H corresponding to and connected to the memory slot signal group H, memory slot G corresponding to and connected to the memory slot signal group G, memory slot F corresponding to and connected to the memory slot signal group F, and memory slot E corresponding to and connected to the memory slot signal group E, and the memory slot H, the memory slot G, the memory slot F, and the memory slot E are arranged in sequence along the second direction.

[0039] Compared with the traditional arrangement structure of the CPU chip and the multiple memory slots designed according to the PCB design standard of Intel Corporation (i.e., as Figure 1 shown: the wire length from the memory slot signal group E of the CPU chip to the memory slot E is 2090 mil, the wire length from the memory slot signal group F of the CPU chip to the memory slot F is 2781 mil, the wire length from the memory slot signal group G of the CPU chip to the memory slot G is 2894 mil, and the wire length from the memory slot signal group H of the CPU chip to the memory slot H is 4230 mil), through the aforementioned new arrangement structure of this embodiment (i.e., as Figure 2 shown: the wire length from the memory slot signal group E of the CPU chip to the memory slot E is 3680 mil, the wire length from the memory slot signal group F of the CPU chip to the memory slot F is 3409 mil, the wire length from the memory slot signal group G of the CPU chip to the memory slot G is 2807 mil, and the wire length from the memory slot signal group H of the CPU chip to the memory slot H is 2592 mil) design, the difference between the longest wire and the shortest wire from the CPU chip to the multiple memory slots can be reduced from 2140 mil (i.e., Figure 1 the difference between the wire length from the memory slot signal group H of the CPU chip to the memory slot H and the wire length from the memory slot signal group E of the CPU chip to the memory slot E in Figure 2(The difference in the trace lengths from the memory slot signal group E of the CPU chip to memory slot E and from the memory slot signal group H of the CPU chip to memory slot H), so that the trace lengths of all traces from the CPU chip to the multiple memory slots can be more balanced (i.e., the long traces are shortened and the short traces are lengthened), thereby balancing the performance differences between the proximal and distal memory modules and improving the memory performance consistency of the memory module system-level test motherboard.)

[0040] Based on Figure 3 and Figure 4 the partial PCB board design comparison diagrams shown, in this embodiment, S-parameters (also known as scattering parameters, which are important parameters in microwave transmission and are used to describe the frequency-domain characteristics of microwave transmission channels; S-parameters include S11, S12, S21, and S22, representing the input reflection coefficient, reverse transmission coefficient, forward transmission coefficient, and output reflection coefficient, respectively) simulations are also carried out on the traditional traces and the new traces from the memory slot signal group of the CPU chip to the memory slot, and the S-parameter simulation waveform comparison diagrams shown in Figure 5 are obtained. It can be found that the waveform quality of the new traces is improved compared to that of the traditional traces, meeting the design expectations.)

[0041] Specifically, the multiple traces located between the multiple memory slot signal groups and the multiple memory slots have the same other parameters except for the length; for example, the other parameters include but are not limited to wire pitch, width, thickness, and / or material, etc.)

[0042] Preferably, the inner traces located between the multiple memory slot signal groups and the multiple memory slots cross the outer traces by a combination of signal layering and vias, where the inner traces refer to the traces that are respectively and correspondingly connected to the third memory slot signal group and the third memory slot at both ends, the outer traces refer to the traces that are respectively and correspondingly connected to the fourth memory slot signal group and the fourth memory slot at both ends, the third memory slot signal group and the fourth memory slot signal group both belong to the multiple memory slot signal groups and the third memory slot signal group is closer to the inside than the fourth memory slot signal group, and the third memory slot and the fourth memory slot both belong to the multiple memory slots and the third memory slot is closer to the CPU chip than the fourth memory slot. The inner traces and the outer traces are a pair of relative concepts, as shown in Figure 2As shown, for example, if the trace from the memory slot signal group H to the memory slot H is the inner trace, then the trace from the memory slot signal group G to the memory slot G can be the outer trace, the trace from the memory slot signal group F to the memory slot F can also be the outer trace, and the trace from the memory slot signal group E to the memory slot E can still be the outer trace; if the trace from the memory slot signal group F to the memory slot F is the inner trace, then the trace from the memory slot signal group E to the memory slot E is the outer trace. Since the inner trace is generally shorter than the outer trace, by the aforesaid method of combining signal layering and vias (i.e., a common in-board jumper method of a PCB board), the inner trace can be further extended, thereby further balancing the performance differences between the proximal and distal memory modules and improving the memory performance consistency of the memory module system-level test mainboard.

[0043] Preferably, the inner traces between the multiple memory slot signal groups and the multiple memory slots have more serpentine segments than the outer traces, wherein the inner trace refers to the trace whose two ends are respectively and correspondingly connected to the third memory slot signal group and the third memory slot, the outer trace refers to the trace whose two ends are respectively and correspondingly connected to the fourth memory slot signal group and the fourth memory slot, the third memory slot signal group and the fourth memory slot signal group both belong to the multiple memory slot signal groups and the third memory slot signal group is closer to the inside than the fourth memory slot signal group, and the third memory slot and the fourth memory slot both belong to the multiple memory slots and the third memory slot is closer to the CPU chip than the fourth memory slot. Also because the inner trace is generally shorter than the outer trace, through the design of more serpentine segments, the inner trace can also be further extended, thereby further balancing the performance differences between the proximal and distal memory modules and improving the memory performance consistency of the memory module system-level test mainboard.

[0044] In summary, adopting the layout structure provided in this embodiment has the following technical effects:

[0045] (1) This embodiment provides a new layout scheme for a CPU chip and multiple memory slots, that is, it includes a CPU chip and multiple memory slots. Among them, the pins of the CPU chip include multiple memory slot signal groups that are correspondingly connected to the multiple memory slots one by one; the multiple memory slots are arranged in sequence along the direction away from the CPU chip, and the arrangement order of the multiple memory slots from near to far is the same as the arrangement order of the multiple memory slot signal groups from inside to outside, so that the lengths of all traces from the CPU chip to the multiple memory slots can be more balanced (that is, the long traces are shortened and the short traces are extended), thereby balancing the performance differences between the proximal and distal memory modules and improving the memory performance consistency of the memory module system-level test mainboard;

[0046] (2) It can also break the PCB design standard of Intel Corporation, completely reverse the order of the memory slot layout on the motherboard, enabling designers to not care about the speed and frequency of the best memory modules, but rather improve the performance of the worst memory module, achieving the effect of "filling the short board of the bucket", which is convenient for practical application and promotion.

[0047] Embodiment 2

[0048] Based on the arrangement structure described in the foregoing Embodiment 1, this embodiment also provides a new type of motherboard, that is, as Figure 6 shown, the motherboard includes but is not limited to a printed circuit board and the arrangement structure described in Embodiment 1, etc., wherein the arrangement structure is located on the printed circuit board.

[0049] The specific technical details and technical effects of this embodiment can be routinely derived based on the foregoing Embodiment 1, and will not be elaborated herein.

[0050] Finally, it should be noted that the above are only the preferred embodiments of the present utility model and are not used to limit the protection scope of the present utility model. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present utility model shall be included in the protection scope of the present utility model.

Claims

1. An arrangement structure of a CPU chip and multiple memory slots, characterized in that, It includes a CPU chip and multiple memory slots. Among them, the pins of the CPU chip include multiple memory slot signal groups that correspond to and are connected to the multiple memory slots one by one. The multiple memory slots are arranged in sequence in a direction away from the CPU chip, and the arrangement order of the multiple memory slots from near to far is the same as the arrangement order of the multiple memory slot signal groups from inside to outside.

2. The arrangement structure according to claim 1, wherein, The CPU chip uses ball grid array packaging technology for pin distribution.

3. The arrangement structure according to claim 1, wherein, The CPU chip uses an Intel processor chip with the model SapphireRapids W-2400 / 3400.

4. The arrangement structure according to claim 1, wherein When the pins of the CPU chip include multiple first memory slot signal groups and multiple second memory slot signal groups that are arranged from inside to outside on the same side of the chip, the arrangement structure includes multiple first memory slots that correspond to and are connected to the multiple first memory slot signal groups one by one and multiple second memory slots that correspond to and are connected to the multiple second memory slot signal groups one by one. The multiple first memory slots are arranged in sequence in a first direction away from the CPU chip, and the arrangement order of the multiple first memory slots from near to far is the same as the arrangement order of the multiple first memory slot signal groups from inside to outside. The multiple second memory slots are arranged in sequence in a second direction away from the CPU chip, and the arrangement order of the multiple second memory slots from near to far is the same as the arrangement order of the multiple second memory slot signal groups from inside to outside, where the second direction and the first direction are a pair of opposite directions.

5. The arrangement structure according to claim 4, wherein When the CPU chip uses an Intel processor chip with the model SapphireRapids W-2400 / 3400, the multiple first memory slot signal groups include memory slot signal group D, memory slot signal group C, memory slot signal group B, and memory slot signal group A that are arranged in sequence from inside to outside, and the multiple second memory slot signal groups include memory slot signal group H, memory slot signal group G, memory slot signal group F, and memory slot signal group E that are arranged in sequence from inside to outside. The multiple first memory slots include memory slot D that corresponds to and is connected to memory slot signal group D, memory slot C that corresponds to and is connected to memory slot signal group C, memory slot B that corresponds to and is connected to memory slot signal group B, and memory slot A that corresponds to and is connected to memory slot signal group A. Memory slot D, memory slot C, memory slot B, and memory slot A are arranged in sequence in the first direction. The multiple second memory slots include memory slot H that corresponds to and is connected to memory slot signal group H, memory slot G that corresponds to and is connected to memory slot signal group G, memory slot F that corresponds to and is connected to memory slot signal group F, and memory slot E that corresponds to and is connected to memory slot signal group E. Memory slot H, memory slot G, memory slot F, and memory slot E are arranged in sequence in the second direction.

6. The arrangement structure according to claim 1, wherein Multiple traces located between the multiple memory slot signal groups and the multiple memory slots have the same other parameters except for length.

7. The arrangement structure according to claim 6, characterized in that, The other parameters include line pitch, width, thickness, and / or material.

8. The arrangement structure according to claim 1, wherein, The inner traces located between the multiple memory slot signal groups and the multiple memory slots cross the outer traces by combining signal layering and vias. Among them, the inner traces refer to the traces whose two ends are respectively and correspondingly connected to the third memory slot signal group and the third memory slot, the outer traces refer to the traces whose two ends are respectively and correspondingly connected to the fourth memory slot signal group and the fourth memory slot, the third memory slot signal group and the fourth memory slot signal group both belong to the multiple memory slot signal groups and the third memory slot signal group is closer to the inside than the fourth memory slot signal group, and the third memory slot and the fourth memory slot both belong to the multiple memory slots and the third memory slot is closer to the CPU chip than the fourth memory slot.

9. The arrangement structure according to claim 1, characterized in that, The inner traces located between the multiple memory slot signal groups and the multiple memory slots have more serpentine segments than the outer traces. Among them, the inner traces refer to the traces whose two ends are respectively and correspondingly connected to the third memory slot signal group and the third memory slot, the outer traces refer to the traces whose two ends are respectively and correspondingly connected to the fourth memory slot signal group and the fourth memory slot, the third memory slot signal group and the fourth memory slot signal group both belong to the multiple memory slot signal groups and the third memory slot signal group is closer to the inside than the fourth memory slot signal group, and the third memory slot and the fourth memory slot both belong to the multiple memory slots and the third memory slot is closer to the CPU chip than the fourth memory slot.

10. A main board, characterized in that, It includes a printed circuit board and the layout structure according to any one of claims 1 to 9, wherein the layout structure is located on the printed circuit board.

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