Memory device

Abstract

A memory device may include a substrate, a plurality of memory cells and a head device. The substrate may have a first side and a second side opposite to each other. A plurality of memory cells may be formed on the first side of the substrate. The head device may be formed on a first side of the substrate. The head device may be configured to selectively couple a supply voltage to the plurality of memory cells through the first supply path combination or the second supply path combination based on a control signal.

Description

Technical Field

[0001] This disclosure relates to a memory device. Background Art

[0002] The development of electronic devices, such as computers, portable devices, smart phones, Internet of Things (IoT) devices, etc., has increased the demand for memory devices. As the size of memory devices (e.g., static random-access memory (SRAM)) shrinks, the oxide diffusion (OD) region becomes smaller, resulting in a reduction in the number of backside power vias with high resistance. This results in a larger voltage drop (e.g., IR drop), which reduces the speed of the SRAM. Summary of the Utility Model

[0003] According to some embodiments of the present disclosure, a memory device includes: a substrate having a first side and a second side opposite to each other; a plurality of memory cells located on the first side of the substrate; and a head device located on the first side of the substrate; wherein the head device couples a power supply to the plurality of memory cells through a first power supply path combination or a second power supply path combination.

[0004] According to some embodiments of the present disclosure, a memory device includes: a plurality of memory cells located on a front side of a substrate; a head device located on the front side; a first conductor structure located on a back side of the substrate; a first via structure located on the back side and electrically coupling the first conductor structure to a first source / drain terminal of the head device; a plurality of second via structures located on the back side and respectively electrically coupling the first conductor structure to the plurality of memory cells; a second conductor structure disposed on the front side; a third via structure disposed on the front side and configured to electrically couple a second source / drain terminal of the head device to the second conductor structure; and a plurality of fourth via structures disposed on the front side and respectively electrically coupling the second conductor structure to the plurality of memory cells.

[0005] According to some embodiments of the present disclosure, a memory device includes: a substrate having a first side and a second side opposite to each other; a plurality of first transistors and a second transistor located on the first side of the substrate; a plurality of memory cells including a metal structure and the plurality of first transistors located on the first side of the substrate; a head device including the second transistor; wherein the head device couples a power supply to the plurality of memory cells through a first power supply path combination or a second power supply path combination. Description of the Drawings

[0006] As will be best understood in conjunction with the accompanying drawings, aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In practice, for clarity of discussion, the dimensions of various features may be increased or decreased arbitrarily.

[0007] Figure 1 Cross-sectional view of an example memory device having a switchable power supply path according to some embodiments;

[0008] Figure 2 Illustrating the front-side layout design and back-side layout design of an example memory device having a switchable power supply path according to some embodiments; Figure 1 of

[0009] Figure 3 Illustrating the Figure 1 example circuit diagram of an example memory device having a switchable power supply path according to some embodiments;

[0010] Figure 4 Illustrating the Figure 1 example circuit diagram of an example memory device having a switchable power supply path according to some embodiments;

[0011] Figure 5 Illustrating the Figure 1 front-side layout design and back-side layout design of an example memory device having a switchable power supply path according to some embodiments;

[0012] Figure 6 Illustrating the Figure 1 example circuit diagram of an example memory device having a switchable power supply path according to some embodiments;

[0013] Figure 7 Illustrating the Figure 1 example circuit diagram of an example memory device having a switchable power supply path according to some embodiments;

[0014] Figure 8 Illustrating an example method flowchart for operating a memory device having a switchable power supply path according to some embodiments; Figure 1 of

[0015] Figure 9 Illustrating an example method flowchart for manufacturing a memory device having a switchable power supply path according to some embodiments; Figure 1 of

[0016]

Symbol Description

[0017] 100: Memory device

[0018] 102: Substrate

[0019] 102A: Side

[0020] 102B: Side

[0021] 104: Memory cell

[0022] 106: Head device

[0023] 106A: Path

[0024] 106B: Path

[0025] 108: Through - hole structure

[0026] 110: Through - hole structure / Head BVD

[0027] 112: Conductor structure

[0028] 114: Conductor structure

[0029] 116: Through - hole structure

[0030] 118: Through - hole structure

[0031] 800, 900: Method

[0032] 802, 804, 905, 910, 915: Operation

[0033] M0, M1, M2: Front - side metallization layer

[0034] BM0, BM1, BM2: Back - side metallization layer Detailed implementation manners

[0035] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these specific embodiments or examples are only examples and are not intended to be limiting. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature may not be in direct contact. Additionally, the disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate a relationship between the various embodiments and / or configurations discussed.

[0036] Additionally, for ease of description, spatial relative terms (such as "under", "below", "lower", "above", "upper", "top", "bottom", and the like) may be used herein to describe the relationship of one component or feature to another component or feature as illustrated in the figures. In addition to the orientation depicted in the figures, spatial relative terms are also intended to encompass different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and thus the spatial relative descriptors used herein may be interpreted accordingly.

[0037] In a static random-access memory (SRAM), NMOS and PMOS transistors are formed in oxide diffusion (OD) regions. The OD regions, sometimes labeled as "oxide diffusion" regions, define the active regions of each transistor, i.e., the regions where the source, drain, and channel are formed under the gate of the transistor. The OD is defined between passive regions, such as shallow trench isolation (STI) or field oxide (FOX) regions. The OD regions contain PMOS or NMOS transistors. Interruptions (gaps) separate adjacent OD regions.

[0038] Power supplies (e.g., VDD and VSS) in a memory device (e.g., SRAM) can be evenly distributed through metal tracks and stripes (e.g., a power delivery network (PDN) or power grid). Each metal layer used in the PDN may have a finite resistivity. According to Ohm's law, when current flows through the power delivery network, a portion of the applied voltage may drop in the PDN. The amount of voltage drop can be V = I * R, called the IR drop. To mitigate the IR drop and improve SRAM performance, a larger oxide diffusion (OD) region and a smaller backside power via resistance are required. The OD region can be the region where the source, drain, and channel are formed under the gate of the transistor. In a small OD region, implementing backside power delivery (BVD) may result in a significant IR drop. When the backside BVD has a high resistance (high-R), this IR drop causes the VDDPUx voltage to decrease, resulting in a decrease in SRAM speed and performance. The IR drop can be mitigated by employing front-side power assist from a larger OD (e.g., front-side power supply), thus forming a parallel circuit. The front-side power assist can help offset the impact of the backside IR drop, thereby improving the overall power supply and performance of the SRAM.

[0039] The present disclosure provides various embodiments of methods for solving leakage problems in the standby / hold mode of a static random-access memory (SRAM) and achieving high-speed operation in the task mode. For example, a foot / head system is introduced. This system allows switching between a single-sided power rail and a double-sided power rail. By doing so, the SRAM can minimize leakage during the standby / hold mode and save power when not being actively accessed. On the other hand, during the task mode, the double-sided power rail can facilitate high-speed operation, ensuring optimal performance of the SRAM when in use.

[0040] Figure 1 FIG. 4 is a cross-sectional view of an example memory device (e.g., SRAM) 100 having a switchable power supply path according to some embodiments. Figure 2 Illustrates the front-side layout design and the back-side layout design of an example memory device 100 Figure 1 having a switchable power supply path according to some embodiments. In Figure 1 the illustrated embodiment, the memory device 100 includes a substrate 102, a plurality of memory cells 104, a head device 106, a first conductor structure 114, a second conductor structure 112, a first via structure (e.g., head BVD) 110, a plurality of second via structures (e.g., BVD) 118, a third via structure (e.g., head VD) 108, and a plurality of fourth via structures (e.g., VD) 116. Figure 1 The cross-sectional view of FIG. 4 is cut along the length direction (e.g., the X direction) of the memory device 100. Although not explicitly shown in Figure 1 FIG. 4, the elements of the memory device 100 can be operatively coupled to each other and to control logic circuitry and / or a power supply. For example, in some embodiments, the head device 106 can be at least electrically coupled to the memory cells 104. The control logic circuitry ( Figure 1 not shown in FIG. 4) is a hardware element that can control the coupled elements (e.g., 102 to 118). In some embodiments, the memory device 100 can have a larger oxide diffusion (OD) region and a low-resistance backside power delivery (BVD).

[0041] The substrate 102 may have a first side 102A and a second side 102B that face each other. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may be doped (e.g., doped with a p-type or n-type dopant) or undoped. The substrate may be a wafer, such as a silicon wafer. Generally, an SOI substrate includes a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is disposed on a substrate, typically a silicon or glass substrate. Other substrates may also be used, such as multi-layer or gradient substrates. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including SiGe, GaAsP, AlInAs, AlGaAs, GaInAs, GaInP, and / or GaInAsP; or combinations thereof.

[0042] A plurality of memory cells 104 may be formed on the first side 102A of the substrate 102. The plurality of memory cells 104 may be hardware elements for storing data. Each of the plurality of memory cells 104 may have p-type conductivity or n-type conductivity. In one aspect, the plurality of memory cells 104 may be embodied as a semiconductor memory device. The plurality of memory cells 104 may include a plurality of rows (e.g., R1, R2, R3,..., R M ) each extending in a first direction (e.g., the X direction) and a plurality of columns (e.g., C1, C2, C3,..., C N ) each extending in a second direction (e.g., the Y direction). Each of the row / column may include one or more conductive structures. In some embodiments, each memory cell 104 is disposed at the intersection of a corresponding row and a corresponding column and may be operated based on a voltage or current passing through the respective conductive structures of the column and the row. A row decoder ( Figure 1 , not shown in the figure) may be a hardware element capable of receiving a row address of the plurality of memory cells 104 and asserting a conductive structure (e.g., a word line) at that row address. A column decoder ( Figure 1 , not shown in the figure) may be a hardware element capable of receiving a column address of the plurality of memory cells 104 and asserting one or more conductive structures (e.g., bit lines, source lines) at that column address.

[0043] The head device 106 may be formed on the first side 102A of the substrate 102. The head device 106 may be configured to selectively couple a power supply voltage (such as VDD or VSS) to the plurality of memory cells 104 based on a control signal (such as a PD signal) through a first power supply path combination (such as 106A and 106B) or a second power supply path combination (such as only 106B). In some embodiments, the head device 106 may have p-type conductivity (such as a p-type transistor), and the power supply voltage may be VDD. In certain embodiments, the head device 106 may have n-type conductivity (such as an n-type transistor), and the power supply voltage may be VSS. The head device 106 may be configured as a foot. The head device 106 may also be configured as a head. A foot may be a circuit that allows the power supply of a specific circuit block or portion to be disconnected or reduced. A head may be a circuit that can connect or enhance the power supply of a specific circuit block or portion. For embodiments using a head, a power supply line having a power supply voltage (such as VDD) (such as a first power supply path combination (such as 106A and 106B) and / or a second power supply path combination (such as only 106B)) may be coupled to the memory cells 104. In some embodiments, the power supply voltage may be VDD or VSS.

[0044] In some embodiments, the head device 106 may be electrically coupled to the first conductor structure 114 through a first via structure (such as head BVD) 110. The first conductor structure 114 may be disposed on the second side 102B of the substrate 102. The first conductor structure 114 may be configured to provide a power supply voltage (such as VDD or VSS). The first via structure 110 may be disposed on the second side 102B of the substrate 102. The first via structure 110 may be configured to electrically couple the first conductor structure 114 to the first source / drain terminal of the head device 106. A plurality of second via structures 118 may be disposed on the second side 102B of the substrate 102. The plurality of second via structures (such as BVD) 118 may be configured to electrically couple the first conductor structure 114 to the memory cells 104 respectively.

[0045] On the backside 102B, the memory device 100 may include a first conductor structure 114. The first conductor structure 114 may include a plurality of backside metallization layers (e.g., BM0, BM1, BM2). Each of the backside metallization layers may include a plurality of backend interconnect structures, metal lines, and via structures embedded in a corresponding dielectric material (e.g., inter-metal dielectric (IMD)). For example, the memory device 100 includes the first conductor structure 114, BM0, BM1, and BM2. Although three backside metallization layers are shown, it should be understood that the memory device 100 may include any number of backside metallization layers and still be within the scope of this disclosure. The backside metallization layer BM0 may include metal lines (sometimes referred to as "BM0 traces") and via structures (sometimes referred to as "BV0s"); the backside metallization layer BM1 may include metal lines (sometimes referred to as "BM1 traces") and via structures (sometimes referred to as "BV1s"); and the backside metallization layer BM2 may include metal lines (sometimes referred to as "BM2 traces"). The second via structure 118 may allow the memory cell 104 to make electrical contact with the BM2 trace through the BM0 trace, BV0, BM1 trace, and BV1.

[0046] In some embodiments, the head device 106 may be electrically coupled to the second conductor structure 112 through a third via structure (e.g., head VD) 108. The second conductor structure 112 may be disposed on the first side 102A of the substrate 102. The second conductor structure 112 may be used to deliver a power supply voltage (e.g., VDD or VSS) to the memory cell 104. The third via structure 108 may be disposed on the first side 102A of the substrate 102. The third via structure 108 may be used to electrically couple the second source / drain terminal of the head device 106 to the second conductor structure 112. A plurality of fourth via structures 116 may be disposed on the first side 102A of the substrate 102. The plurality of fourth via structures (e.g., VD) 116 may be used to electrically couple the second conductor structure 112 to the memory cell 104 respectively.

[0047] In some embodiments, the first via structure (e.g., head BVD) 110 has a first width extending along a first direction (e.g., the Y direction) perpendicular to the second direction (e.g., the X direction), and the first conductor structure extends along the second direction. The second via structure (e.g., BVD) 118, the third via structure (e.g., head VD) 108, and the fourth via structure (e.g., VD) 116 may have a second width extending along the first direction (e.g., the Y direction). The first width (e.g., 30 nm) is significantly greater than the second width (e.g., 20 nm). In other words, the first via structure (e.g., head BVD) 110 is larger than the third via structure (e.g., head VD) 108.

[0048] Above the third vias structure (e.g., head VD) 108 and the fourth vias structure (e.g., VD) 116, the memory device 100 may include a second conductor structure 112. The second conductor structure 112 may include a plurality of front-side metallization layers (e.g., M0, M1, M2). Each of the front-side metallization layers may include a plurality of back-end interconnect structures, metal lines, and via structures embedded in a corresponding dielectric material (e.g., inter-metal dielectric (IMD)). For example, the memory device 100 includes the second conductor structure 112, M0, M1, and M2. Although three front-side metallization layers are shown, it should be understood that the memory device 100 may include any number of front-side metallization layers while still being within the scope of this disclosure. The front-side metallization layer M0 may include metal lines (sometimes referred to as "M0 traces") and via structures (sometimes referred to as "V0"); the front-side metallization layer M1 includes metal lines (sometimes referred to as "M1 traces") and via structures (sometimes referred to as "V1"); and the front-side metallization layer M2 may include metal lines (sometimes referred to as "M2 traces"). The fourth via structure 116 may allow the memory cell 104 to make electrical contact with the M2 trace through the M0 trace, V0, M1 trace, and V1. The following Figure 3 and Figure 4 will be used to describe the operation of the memory device 100.

[0049] Figure 3 Illustrate an example circuit diagram of an example memory device Figure 1 with a switchable power supply path according to some embodiments. Figure 4 Illustrate an example circuit diagram of an example memory device Figure 1 with a switchable power supply path according to some embodiments. The head device may have p-type conductivity and the power supply voltage may be VDD. There may be a power supply path from the first conductor structure 114 to one of the memory cells 104. The first path 106B may extend from the first conductor structure 114, through one of the second via structures 118, and extend to one of the memory cells 104. The second path 106A may extend from the first conductor structure 114, through each of the first via structure 110, the head device 106, the third via structure 108, and the fourth via structure 116, and extend to one of the memory cells 104. The first power supply path combination may include the first path 106B and the second path 106A. The second power supply path combination may include the first path 106B.

[0050] In the task mode (e.g., when PD = 0), the head device 106 can be turned on. The first power supply path combination (e.g., the first path 106B + the second path 106A) can be selected. In this case, due to the low resistance (low-R) of the head BVD 110, the strong power supply voltage (e.g., VDDPUx) for the pull-up transistor can be strong (smaller IR drop). This low resistance results in a smaller IR drop, enabling the pull-up transistor to work more efficiently and effectively, thereby improving the speed and performance of the SRAM. In this case, VDDPUx = VDD - small ΔV. For example, VDD can be 1V. After the IR drop (e.g., ΔV = 0.02V), VDDPUx can become 0.98V.

[0051] In the standby or hold mode (e.g., when PD = 1), the head device 106 can be turned off. The second power supply path combination (e.g., the first path 106B) can be selected. In this case, power is delivered only through the backside power delivery (BVD). Due to the high resistance (high-R) of the multiple second vias structures (e.g., BVD) 118, the power supply voltage of the pull-up transistor (e.g., VDDPUx) may have a large IR drop. However, this configuration can reduce the power consumption of the SRAM latch. In this case, VDDPUx = VDD - large ΔV. For example, VDD can be 1V. After the IR drop (e.g., ΔV = 0.1V), VDDPUx can become 0.9V.

[0052] When a control signal (e.g., the PD signal) is provided in the first logic state (e.g., when PD = 0), the head device 106 can be used to couple a power supply voltage (e.g., VDD) to one or more of the memory cells 104 through the first power supply path combination (e.g., the first path 106B + the second path 106A). When a control signal (e.g., the PD signal) is provided in the second logic state (e.g., when PD = 1), the head device 106 can be used to couple a power supply voltage (e.g., VDD) to one or more of the memory cells 104 through the second power supply path combination (e.g., the first path 106B).

[0053] Figure 5 Describing the front-side layout design and the back-side layout design of an example memory device with a switchable power supply path according to some embodiments Figure 1 of. Figure 6 Describing the Figure 1 example circuit diagram of an example memory device with a switchable power supply path according to some embodiments Figure 7 Describing the Figure 1 example circuit diagram of an example memory device with a switchable power supply path according to some embodiments

[0054] In addition to the head device 106 having different types of conductivity (e.g., n-type) and different supply voltages (e.g., VSS), Figure 5 、 Figure 6 、 Figure 7 the memory device 100 is substantially similar to Figure 1 the memory device 100. The head device 106 can be used for the feet. For embodiments using the feet, a power supply line having a supply voltage (e.g., VSS) (e.g., a first power supply path combination (e.g., 106A and 106B) and / or a second power supply path combination (e.g., only 106B)) can be coupled to the memory cell 104.

[0055] In the task mode (e.g., when PD = 1), the head device 106 can be turned on. The first power supply path combination (e.g., the first path 106B + the second path 106A) can be selected. In this case, due to the low resistance (low-R) of the head BVD 110, the strong supply voltage (e.g., VSSPDx) for the pull-down transistor can be strong (smaller IR drop). This low resistance results in a smaller IR drop, making the pull-down transistor work more efficiently and effectively, thereby improving the speed and performance of the SRAM. In this case, VSSPDx = VSS + small ΔV. For example, VSS can be 0V. After the IR drop (e.g., ΔV = 0.02V), VSSPDx can become 0.02V.

[0056] In the standby or hold mode (e.g., when PD = 0), the head device 106 can be turned off. The second power supply path combination (e.g., the first path 106B) can be selected. In this case, power is delivered only through the backside power delivery (BVD). Due to the high resistance (high-R) of the plurality of second vias structures (e.g., BVD) 118, the supply voltage of the pull-down transistor (e.g., VSSPDx) may have a large IR drop. However, this configuration can reduce the power consumption of the SRAM latch. In this case, VSSPDx = VDD + large ΔV. For example, VDD can be 0V. After the IR drop (e.g., ΔV = 0.1V), VSSPDx can become 0.1V.

[0057] When a control signal (e.g., a PD signal) is provided in a first logic state (e.g., when PD = 1), the head device 106 can be used to couple a power supply voltage (e.g., VSS) to one or more of the memory cells 104 through a first power supply path combination (e.g., the first path 106B + the second path 106A). When the control signal (e.g., the PD signal) is provided in a second logic state (e.g., when PD = 0), the head device 106 can be used to couple the power supply voltage (e.g., VSS) to one or more of the memory cells 104 through a second power supply path combination (e.g., the first path 106B).

[0058] Figure 8 Illustrates an example method for operating Figure 1 a memory device having a switchable power supply path according to some embodiments. Method 800 can be used to operate memory device 100. It should be noted that method 800 is only an example and is not intended to limit the present disclosure. Thus, it should be understood that additional operations can be provided before, during, and after Figure 8 method 800, and some other operations can be briefly described herein only.

[0059] Method 800 begins with operation 802, in which the memory device 100 carries a power supply voltage (e.g., VDD or VSS) on a first conductor structure 114 disposed on a first side 102B of the substrate 102. For example, in Figure 1 , the head device 106 can be used to selectively couple the power supply voltage (e.g., VDD or VSS) to the memory cells 104 through a first power supply path combination (e.g., 106A and 106B) or a second power supply path combination (e.g., only 106B) based on a control signal (e.g., the PD signal). In some embodiments, the first power supply path combination can include a first path 106B and a second path 106A. The first path 106B can extend from the first conductor structure 114, through one of a plurality of first via structures disposed on the first side 102B, and extend to the memory cell 104. The second path 106A can extend from the first conductor structure 114, through the head device 106 and one of a plurality of second via structures 108, 110, 116 disposed on the second side 102A, and extend to the memory cell 104. The second power supply path combination can include a single path 106B. The single path 106B can extend from the first conductor structure 114, through one of a plurality of first via structures 118 disposed on the first side 102B, and extend to the memory cell 104.

[0060] Method 800 proceeds to operation 804, where a control signal is received to turn on or off the head device 106 disposed on the second side 102A of the substrate 102. For example, the head device 106 may have p-type conductivity and the power supply voltage may be VDD. In Figure 3 when the head device 106 is turned on (e.g., PD = 0), the power supply voltage (e.g., VDD) is delivered to the memory cells 104 disposed on the second side 102A through the first power supply path combination (e.g., the first path 106B + the second path 106A). In Figure 4 when the head device 106 is turned off (e.g., PD = 1), the power supply voltage (e.g., VDD) is delivered to the memory cells 104 through the second power supply path combination (e.g., the first path 106B). For another example, the head device may have n-type conductivity and the power supply voltage may be VSS. In Figure 6 when the head device 106 is turned on (e.g., PD = 1), the power supply voltage (e.g., VSS) is delivered to the memory cells 104 disposed on the second side 102A through the first power supply path combination (e.g., the first path 106B + the second path 106A). In Figure 7 when the head device 106 is turned off (e.g., PD = 0), the power supply voltage (e.g., VSS) is delivered to the memory cells 104 through the second power supply path combination (e.g., the first path 106B).

[0061] The memory design incorporates several features to optimize power consumption and performance. One such feature is the addition of a head or a foot with a large oxide diffusion (OD) region and vias to efficiently supply power (VDD / VSS) to the SRAM. During the task mode, when the head or the foot is activated, the power supply becomes bilateral, using front-side and back-side power supplies to ensure a healthier power environment within the SRAM. This improves the overall performance and speed of the memory device.

[0062] Conversely, in the standby or hold mode, when the head or the foot is turned off, the power supply switches to unilateral (back-side) delivery. This configuration results in a weaker power supply within the SRAM, which is particularly suitable for promoting data retention while minimizing power consumption. This energy-saving method allows the memory device to efficiently retain data without unnecessary power consumption. The present disclosure provides a power management method applicable to a multi-port SRAM with latch-based memory.

[0063] In one aspect of the present disclosure, a memory device is disclosed. The memory device includes: a substrate having a first side and a second side opposite to each other; a plurality of memory cells formed on the first side of the substrate; and a head device formed on the first side of the substrate. The head device is configured to selectively couple a power supply voltage to the plurality of memory cells based on a control signal through a first power supply path combination or a second power supply path combination. According to some embodiments of the present disclosure, the memory device further includes: a first conductor structure disposed on the second side of the substrate and configured to provide the power supply voltage; a first via structure disposed on the second side of the substrate and configured to electrically couple the first conductor structure to a first source / drain terminal of the head device; a plurality of second via structures disposed on the second side of the substrate and configured to electrically couple the first conductor structure to the plurality of memory cells respectively; a second conductor structure disposed on the first side of the substrate and configured to deliver the power supply voltage to the plurality of memory cells; a third via structure disposed on the first side of the substrate and configured to electrically couple a second source / drain terminal of the head device to the second conductor structure; and a plurality of fourth via structures disposed on the first side of the substrate and configured to electrically couple the second conductor structure to the plurality of memory cells respectively. According to some embodiments of the present disclosure, the first power supply path combination includes: a first path extending from the first conductor structure, passing through one of the plurality of second via structures, and extending to one of the plurality of memory cells; and a second path extending from the first conductor structure, passing through the first via structure, the head device, the third via structure, and one of the plurality of fourth via structures, and extending to one of the plurality of memory cells. According to some embodiments of the present disclosure, the head device is turned on. According to some embodiments of the present disclosure, the second power supply path combination includes: a path extending from the first conductor structure, passing through one of the plurality of second via structures, and extending to one of the plurality of memory cells. According to some embodiments of the present disclosure, the head device is turned off. According to some embodiments of the present disclosure, the power supply voltage is VDD or VSS. According to some embodiments of the present disclosure, the first via structure has a first width extending along a first direction perpendicular to a second direction in which the first conductor structure extends, and the plurality of second via structures, the plurality of third via structures, and the plurality of fourth via structures have a second width extending along the first direction. According to some embodiments of the present disclosure, the first width is greater than the second width. According to some embodiments of the present disclosure, when the control signal is provided in a first logic state, the head device is configured to couple the power supply voltage to one or more of the plurality of memory cells through the first power supply path combination, and when the control signal is provided in a second logic state, the head device is configured to couple the power supply voltage to one or more of the plurality of memory cells through the second power supply path combination.

[0064] In another aspect of the present disclosure, a memory device is disclosed. The memory device includes: a plurality of memory cells formed on a front side of a substrate; a head device also formed on the front side; a first conductor structure disposed on a back side of the substrate and configured to provide a power supply voltage; a first via structure disposed on the back side and configured to electrically couple the first conductor structure to a first source / drain terminal of the head device; a plurality of second via structures disposed on the back side and configured to electrically couple the first conductor structure to the memory cells respectively; a second conductor structure disposed on the front side and configured to deliver the power supply voltage to the memory cells; a third via structure disposed on the front side and configured to electrically couple a second source / drain terminal of the head device to the second conductor structure; and a plurality of fourth via structures disposed on the front side and configured to electrically couple the second conductor structure to the memory cells respectively. According to some embodiments of the present disclosure, when the head device is turned on, the power supply voltage is delivered to one or more of the plurality of memory cells through a first path and a second path. According to some embodiments of the present disclosure, the first path extends from the first conductor structure, passes through a corresponding one of the plurality of second via structures, and extends to the one or more memory cells, and the second path extends from the first conductor structure, passes through the first via structure, the head device, the third via structure, the second conductor structure, and a corresponding one of the plurality of fourth via structures, and extends to the one or more memory cells. According to some embodiments of the present disclosure, when the head device is turned off, the power supply voltage is delivered to one or more of the plurality of memory cells through a single path. According to some embodiments of the present disclosure, the single path extends from the first conductor structure, passes through a corresponding one of the plurality of second via structures, and extends to the one or more memory cells. According to some embodiments of the present disclosure, the head device has p-type conductivity and the power supply voltage is VDD. According to some embodiments of the present disclosure, the head device has n-type conductivity and the power supply voltage is VSS. According to some embodiments of the present disclosure, the first conductor structure and the second conductor structure each extend along a first direction, the first via structure has a first width extending along a second direction perpendicular to the first direction, each of the plurality of second via structures, the third via structure, and the plurality of fourth via structures has a second width extending along the second direction, and the first width is substantially greater than the second width.

[0065] In one aspect of the present disclosure, a method for operating a memory device is disclosed. The method includes carrying a power supply voltage on a first conductor structure disposed on a first side of a substrate. The method includes receiving a control signal to turn on or off a head device disposed on a second side of the substrate. The method includes: when the head device is turned on, causing the power supply voltage to be delivered to a memory cell disposed on the second side through a first power supply path combination. The method includes: when the head device is turned off, causing the power supply voltage to be delivered to the memory cell through a second power supply path combination. According to some embodiments of the present disclosure, a method for manufacturing a plurality of memory devices includes the steps of: providing a substrate having a first side and a second side opposite to each other; forming a plurality of first transistors and a second transistor on the first side of the substrate; and forming a metal structure on the first side of the substrate, wherein the plurality of first transistors and the metal structure are for a plurality of memory cells on the first side of the substrate; wherein the second transistor is for a head device on the first side of the substrate; wherein the second transistor is configured to selectively couple a power supply voltage to the plurality of memory cells through a first power supply path combination or a second power supply path combination based on a control signal. According to some embodiments of the present disclosure, the method further includes the steps of: forming a second conductor structure on the first side of the substrate, wherein the second conductor structure is configured to deliver the power supply voltage to the plurality of first transistors; forming a third via structure on the first side of the substrate, wherein the third via structure is configured to electrically couple a second source / drain terminal of the second transistor to the second conductor structure; and forming a plurality of fourth via structures on the first side of the substrate, wherein the plurality of fourth via structures are configured to electrically couple the second conductor structure to the plurality of first transistors respectively; forming a first conductor structure on the second side of the substrate, wherein the first conductor structure is configured to provide the power supply voltage; forming a first via structure on the second side of the substrate, wherein the first via structure is configured to electrically couple the first conductor structure to a first source / drain terminal of the second transistor; and forming a plurality of second via structures on the second side of the substrate, wherein the plurality of second via structures are configured to electrically couple the first conductor structure to the plurality of first transistors respectively.

[0066] According to some embodiments of the present disclosure, a memory device includes: a substrate having a first side and a second side opposite to each other; a plurality of memory cells located on the first side of the substrate; and a head device located on the first side of the substrate; wherein the head device couples a power supply to the plurality of memory cells through a first power supply path combination or a second power supply path combination.

[0067] According to some embodiments of the present disclosure, a memory device includes: a plurality of memory cells located on a front side of a substrate; a head device located on the front side; a first conductor structure located on a back side of the substrate; a first via structure located on the back side and electrically coupling the first conductor structure to a first source / drain terminal of the head device; a plurality of second via structures located on the back side and respectively electrically coupling the first conductor structure to the plurality of memory cells; a second conductor structure disposed on the front side and configured to deliver a power supply voltage to the plurality of memory cells; a third via structure disposed on the front side and configured to electrically couple a second source / drain terminal of the head device to the second conductor structure; and a plurality of fourth via structures disposed on the front side and respectively electrically coupling the second conductor structure to the plurality of memory cells.

[0068] According to some embodiments of the present disclosure, a memory device includes: a substrate having a first side and a second side opposite to each other; a plurality of first transistors and a second transistor located on the first side of the substrate; a plurality of memory cells including a metal structure and the plurality of first transistors located on the first side of the substrate; a head device including the second transistor; wherein the head device couples a power supply to the plurality of memory cells through a first power supply path combination or a second power supply path combination.

[0069] Figure 9 Illustrate an exemplary method for manufacturing Figure 1 a memory device with a switchable power supply path according to some embodiments. It should be understood that, for a better understanding of the concepts of the present disclosure, Figure 9 and Figure 1 . Therefore, it should be noted that additional processes may be provided before, during, and after the Figure 9 method, and some other processes may be briefly described herein only.

[0070] Now referring to Figure 9 , operation 905 may provide a substrate 102. The substrate 102 may have a first side 102A and a second side 102B opposite to each other. The substrate 102 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like. The semiconductor substrate may be doped (e.g., doped with a p-type or n-type dopant) or undoped.

[0071] Next, method 900 proceeds to operation 910 of forming a plurality of first transistors and second transistors on a first side 102A of substrate 102. The plurality of first transistors can be hardware elements for storing data. Each of the plurality of first transistors can have p-type conductivity or n-type conductivity. In one aspect, the plurality of first transistors can be embodied as a semiconductor memory device. In some embodiments, the second transistor can be used for the head device 106 on the first side 102A of substrate 102. The second transistor can have p-type conductivity or n-type conductivity.

[0072] Next, method 900 proceeds to operation 915 of forming metal structures (e.g., word lines and / or bit lines, interconnects) on the first side 102A of substrate 102. The plurality of first transistors and the metal structures (e.g., word lines and / or bit lines) can be used for a plurality of memory cells on the first side 102A of substrate 102. In some embodiments, a second conductor structure 112 can be formed on the first side 102A of substrate 102. The second conductor structure 112 can be used to deliver a power supply voltage to the first transistor. A third via structure 108 can be formed on the first side 102A of substrate 102. The third via structure 108 can be used to electrically couple a second source / drain terminal of the second transistor to the second conductor structure 112. A plurality of fourth via structures 108 can be formed on the first side 102A of substrate 102. The plurality of fourth via structures 108 can be used to electrically couple the second conductor structure 112 to the first transistors respectively. A first conductor structure 114 can be formed on a second side 102B of substrate 102. The first conductor structure 114 can be used to provide a power supply voltage. A first via structure 110 can be formed on the second side 102B of substrate 102. The first via structure 110 can be used to electrically couple the first conductor structure 114 to a first source / drain terminal of the second transistor. A plurality of second via structures 118 can be formed on the second side 102B of substrate 102. The plurality of second via structures 118 can be used to electrically couple the first conductor structure 114 to the first transistors respectively.

[0073] In some embodiments, a second transistor may be used to selectively couple a power supply voltage to a plurality of memory cells 104 (e.g., a first transistor) based on a control signal through a first power supply path combination (e.g., 106A and 106B) or a second power supply path combination (e.g., only 106B). The first power supply path combination (e.g., 106A and 106B) may include: a first path 106B extending from a first conductor structure 114, passing through one of a plurality of second vias structures disposed on a second side, and extending to the first transistor; and a second path 106A extending from the first conductor structure 114, passing through the second transistor and one of a plurality of second vias structures disposed on a first side, and extending to the first transistor. The second power supply path combination 106A may include: a single path extending from the first conductor structure 114, passing through one of a plurality of first via structures 118 disposed on the second side, and extending to the first transistor.

[0074] As used herein, the terms "about" and "approximately" generally indicate a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "about" may indicate a value of a given quantity that varies within, for example, 10% to 30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0075] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that various changes, substitutions, and alterations may be made therein without departing from the spirit and scope of the present disclosure.

Claims

1. A memory device, characterized in that, Comprising: A substrate having a first side and a second side opposite to each other; A plurality of memory cells located on the first side of the substrate; And A head device located on the first side of the substrate; Wherein the head device couples a power supply to the plurality of memory cells through a first power supply path combination or a second power supply path combination.

2. The memory device according to claim 1, characterized in that, Further comprising: A first conductor structure located on the second side of the substrate; A first via structure located on the second side of the substrate and electrically coupling the first conductor structure to a first source / drain terminal of the head device; A plurality of second via structures located on the second side of the substrate and respectively electrically coupling the first conductor structure to the plurality of memory cells; A second conductor structure located on the first side of the substrate; A third via structure located on the first side of the substrate and electrically coupling a second source / drain terminal of the head device to the second conductor structure; and A plurality of fourth via structures located on the first side of the substrate and respectively electrically coupling the second conductor structure to the plurality of memory cells.

3. The memory device according to claim 2, wherein, The first power supply path combination includes: A first path extending from the first conductor structure, passing through one of the plurality of second via structures, and extending to one of the plurality of memory cells; and A second path extending from the first conductor structure, passing through the first via structure, the head device, the third via structure, and one of the plurality of fourth via structures, and extending to one of the plurality of memory cells.

4. The memory device according to claim 2, wherein The second power supply path combination includes: A path extending from the first conductor structure, passing through one of the plurality of second via structures, and extending to one of the plurality of memory cells.

5. The memory device according to claim 2, wherein The first via structure has a first width extending in a first direction perpendicular to a second direction in which the first conductor structure extends, and the plurality of second via structures, the third via structure, and the plurality of fourth via structures have a second width extending in the first direction.

6. The memory device according to claim 5, wherein, The first width is greater than the second width.

7. A memory device, characterized in that, Comprising: A plurality of memory cells located on a front side of a substrate; A head device located on the front side; A first conductor structure located on a back side of the substrate; A first via structure located on the back side and electrically coupling the first conductor structure to a first source / drain terminal of the head device; A plurality of second via structures located on the back side and respectively electrically coupling the first conductor structure to the plurality of memory cells; A second conductor structure located on the front side; A third via structure located on the front side and electrically coupling a second source / drain terminal of the head device to the second conductor structure; and A plurality of fourth via structures located on the front side and respectively electrically coupling the second conductor structure to the plurality of memory cells.

8. The memory device according to claim 7, wherein The first conductor structure and the second conductor structure each extend along a first direction. The first via structure has a first width extending along a second direction perpendicular to the first direction. Each of the plurality of second via structures, the third via structure, and the plurality of fourth via structures has a second width extending along the second direction, and the first width is greater than the second width.

9. The memory device according to claim 7, wherein The head device is a p-type conductive device.

10. A memory device, characterized in that, Comprising: a substrate having a first side and a second side opposite to each other; a plurality of first transistors and a second transistor located on the first side of the substrate; a plurality of memory cells including a metal structure and the plurality of first transistors located on the first side of the substrate; and a head device including the second transistor, wherein the head device couples a power supply to the plurality of memory cells through a first power supply path combination or a second power supply path combination.

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