Diamagnetic packaging structure of chip, chip and electronic equipment

Abstract

The utility model provides a diamagnetic packaging structure of a chip, the chip and electronic equipment, and the structure comprises a substrate which is provided with a mounting surface; the chip body is provided with a first surface and a second surface which are arranged oppositely, and the chip body is arranged on the mounting surface through the first surface of the chip body; the first magnetic shielding layer is arranged between the substrate and the chip body, and the first magnetic shielding layer is used for shielding interference of an external magnetic field on the chip body in the direction corresponding to the first surface of the chip body; the packaging layer is provided with a packaging surface, and the packaging layer is used for wrapping the chip body, the first magnetic shielding layer and the substrate; the second magnetic shielding layer is arranged on the packaging surface, and the second magnetic shielding layer is used for shielding interference of an external magnetic field on the chip body in the direction corresponding to the second surface of the chip body; the first magnetic shielding layer and the second magnetic shielding layer are arranged in parallel, and the first magnetic shielding layer and the second magnetic shielding layer cooperatively shield interference of an external magnetic field on the chip body.

Description

Technical Field

[0001] This application relates to the technical field of anti-magnetic packaging, and particularly relates to an anti-magnetic packaging structure for a chip, a chip, and an electronic device. Background Art

[0002] A magnetic field is a physical phenomenon generated by magnetic substances or electric currents, which can interfere with a chip, affecting or even damaging the normal operation of the chip. For example, a magnetic field can cause current induction, magnetization, or magnetic field coupling in the chip, resulting in signal distortion, data loss, or performance degradation. During the chip design and manufacturing process, anti-magnetic packaging technology is usually used to manufacture anti-magnetic packaging materials and structures to protect the chip from external magnetic field interference. Existing anti-magnetic packaging technologies usually attach the anti-magnetic packaging structure to the chip during chip packaging, and the anti-magnetic packaging structure has only a single layer, resulting in limited magnetic shielding effect for the chip. Therefore, improving the magnetic shielding effect on the chip is an urgent problem to be solved in this field. Summary of the Utility Model

[0003] The purpose of the embodiments of this application is to provide an anti-magnetic packaging structure for a chip, a chip, and an electronic device, including:

[0004] A substrate, the substrate having a mounting surface;

[0005] A chip body, the chip body having a first surface and a second surface disposed opposite to each other, and the chip body is disposed on the mounting surface through the first surface of the chip body;

[0006] A first magnetic shielding layer, the first magnetic shielding layer being disposed between the substrate and the chip body, and the first magnetic shielding layer is used to shield the interference of the external magnetic field on the chip body in the corresponding direction of the first surface of the chip body;

[0007] A packaging layer, the packaging layer having a packaging surface, and the packaging layer is used to enclose the chip body, the first magnetic shielding layer, and the substrate;

[0008] A second magnetic shielding layer, the second magnetic shielding layer being disposed on the packaging surface, and the second magnetic shielding layer is used to shield the interference of the external magnetic field on the chip body in the corresponding direction of the second surface of the chip body;

[0009] Wherein, the first magnetic shielding layer and the second magnetic shielding layer are arranged in parallel, and the first magnetic shielding layer and the second magnetic shielding layer cooperate to shield the interference of the external magnetic field on the chip body.

[0010] Optionally, both the first magnetic shielding layer and the second magnetic shielding layer include a plurality of magnetically shielding layers stacked on top of each other, wherein the plurality of magnetically shielding layers stacked on top of each other are used to enhance the magnetic field shielding function of the first magnetic shielding layer and the second magnetic shielding layer.

[0011] Optionally, a first adhesive layer is provided between the first magnetic shielding layer and the substrate, and the first adhesive layer is used to bond the first magnetic shielding layer to the substrate.

[0012] Optionally, a second adhesive layer is provided between the chip body and the first magnetic shielding layer, and the second adhesive layer is used to bond the chip body to the first magnetic shielding layer.

[0013] Optionally, a third adhesive layer is provided between the second magnetic shielding layer and the encapsulation layer, and the third adhesive layer is used to bond the second magnetic shielding layer to the encapsulation layer.

[0014] Optionally, both the first magnetic shielding layer and the second magnetic shielding layer are used to absorb the magnetic induction lines of the external magnetic field and form a magnetic vacuum in the region where the chip body is located.

[0015] Optionally, the encapsulation layer includes a resin matrix, and a magnetic shielding material is provided in the resin matrix, and the magnetic shielding material is used to enhance the magnetic field shielding function.

[0016] Optionally, the diamagnetic materials provided in the first magnetic shielding layer and the second magnetic shielding layer at least include ferrite and permalloy; a magnetoresistive random access memory is provided in the chip body, and no magnetic shielding layer is provided around the magnetoresistive random access memory.

[0017] An embodiment of the present application further provides a chip, which includes the anti-magnetic encapsulation structure of the above chip, and the chip body of the chip is arranged in the anti-magnetic encapsulation structure of the chip.

[0018] An embodiment of the present application further provides an electronic device, including: a chip, the chip includes the anti-magnetic encapsulation structure of the above chip, and the anti-magnetic encapsulation structure of the chip is used to encapsulate the chip body of the chip.

[0019] The anti-magnetic encapsulation structure of the chip in the embodiment of the present application has a first magnetic shielding layer and a second magnetic shielding layer. The first magnetic shielding layer and the second magnetic shielding layer are a double-layer magnetic shielding layer arranged in parallel. The first magnetic shielding layer and the second magnetic shielding layer cooperate to shield the interference of the external magnetic field on the chip body. The double-layer magnetic shielding layer can lead out the magnetic induction lines in different directions from the surface of the grain unit, improving the anti-magnetic performance of the anti-magnetic encapsulation structure. And the encapsulation process of the anti-magnetic encapsulation structure in the embodiment of the present application is more simplified, reducing the difficulty of wire bonding. Description of the Drawings

[0020] Figure 1 It is a schematic structural diagram of the anti-magnetic packaging structure of the chip provided by the embodiment of the present application;

[0021] Figure 2 It is another schematic structural diagram of the anti-magnetic packaging structure of the chip provided by the embodiment of the present application.

[0022] Reference numerals:

[0023] 10 - Substrate; 20 - Chip body; 30 - First magnetic shielding layer; 40 - Encapsulation layer; 50 - Second magnetic shielding layer; 60 - First adhesive layer; 70 - Second adhesive layer; 80 - Third adhesive layer. Detailed implementation manners

[0024] Reference is made herein to the various solutions and features of the present application with reference to the accompanying drawings.

[0025] It should be understood that various modifications can be made to the embodiments applied herein. Therefore, the above description should not be regarded as a limitation, but only as an example of the embodiments. Those skilled in the art will think of other modifications within the scope and spirit of the present application.

[0026] The accompanying drawings included in the specification and forming a part of the specification illustrate the embodiments of the present application, and together with the general description of the present application given above and the detailed description of the embodiments given below are used to explain the principles of the present application.

[0027] These and other features of the present application will become apparent from the following description of the preferred forms of the embodiments given by way of non-limiting examples with reference to the accompanying drawings.

[0028] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art can surely implement many other equivalent forms of the present application.

[0029] When combined with the accompanying drawings, the above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description.

[0030] Hereinafter, specific embodiments of the present application will be described with reference to the accompanying drawings; however, it should be understood that the embodiments applied are only examples of the present application, and it can be implemented in various ways. Well-known and / or repetitive functions and structures are not described in detail to avoid unnecessary or redundant details from obscuring the present application. Therefore, the specific structural and functional details applied herein are not intended to be limiting, but only as a basis for the claims and a representative basis for teaching those skilled in the art to use the present application in substantially any suitable detailed structure in a variety of ways.

[0031] This specification may use phrases such as "in one embodiment", "in another embodiment", "in yet another embodiment", or "in other embodiments", which may each refer to one or more of the same or different embodiments according to the present application.

[0032] An anti-magnetic packaging structure for a chip according to an embodiment of the present application is used to package the die unit of the chip to obtain the anti-magnetic packaging structure of the chip. The chip may be a SOC (System on Chip) or a chip including a SOC. A magnetoresistive random access memory (Magnetoresistive Random Access Memory ， MRAM) may be provided in the chip. MRAM is a magnetic storage medium and is very sensitive to external magnetic fields. During the use of the chip, it may be interfered by external magnetic fields, such as permanent magnets or electromagnetic fields. The external magnetic field will affect the normal operation of the chip, and thus affect the normal operation of the MRAM. The anti-magnetic packaging structure of the chip of the present application respectively provides magnetic shielding layers on both sides of the die unit of the chip to form an anti-magnetic packaging structure with a double-layer magnetic shielding layer. The double-layer magnetic shielding layer can jointly shield the interference of the external magnetic field on the chip, has a strong anti-magnetic interference function, and simplifies the packaging process.

[0033] The following will describe the anti-magnetic packaging structure of the chip in detail with reference to the accompanying drawings. Figure 1 and Figure 2 is a schematic diagram of the anti-magnetic packaging structure of the chip according to an embodiment of the present application. As Figure 1 shown, the anti-magnetic packaging structure of the chip includes:

[0034] A substrate 10, the substrate 10 having a mounting surface;

[0035] A chip body 20, the chip body 20 having a first surface and a second surface opposite to each other, and the chip body 20 is disposed on the mounting surface through the first surface of the chip body 20;

[0036] A first magnetic shielding layer 30, the first magnetic shielding layer 30 being disposed between the substrate 10 and the chip body 20, and the first magnetic shielding layer 30 being used to shield the interference of the external magnetic field on the chip body 20 in the corresponding direction of the first surface of the chip body 20;

[0037] A packaging layer 40, the packaging layer 40 having a packaging surface, and the packaging layer 40 being used to wrap the chip body 20, the first magnetic shielding layer 30, and the substrate 10 therein;

[0038] The second magnetic shielding layer 50 is disposed on the encapsulation surface, and the second magnetic shielding layer 50 is used to shield the interference of the external magnetic field on the chip body 20 in the corresponding direction of the second face of the chip body 20;

[0039] Wherein, the first magnetic shielding layer 30 and the second magnetic shielding layer 50 are arranged in parallel, and the first magnetic shielding layer 30 and the second magnetic shielding layer 50 cooperate to shield the interference of the external magnetic field on the chip body 20.

[0040] In this embodiment, the anti-magnetic encapsulation structure of the chip is provided with a substrate 10. The substrate 10 has a mounting surface, and the mounting surface is disposed on the surface of the substrate 10. The mounting surface is used to mount the chip body 20 on the surface of the substrate 10. The anti-magnetic encapsulation structure of the chip is provided with a chip body 20. The chip body 20 can be a die unit of the chip. The chip body 20 can include multiple stacked die units. The chip body 20 has a first face and a second face arranged opposite to each other. The first face of the chip body 20 can be attached to the mounting surface of the substrate 10 so that the chip body 20 is mounted on the substrate 10. The anti-magnetic encapsulation structure of the chip is provided with a first magnetic shielding layer 30. The first magnetic shielding layer 30 is disposed between the substrate 10 and the chip body 20. Specifically, the first magnetic shielding layer 30 is disposed between the mounting surface of the substrate 10 and the first face of the chip body 20. The first magnetic shielding layer 30 can cover the chip body 20. The first magnetic shielding layer 30 can be composed of a high magnetic permeability metal. The first magnetic shielding layer 30 is used to shield the interference of the external magnetic field on the chip body 20 in the corresponding direction of the first face of the chip body 20. The anti-magnetic encapsulation structure of the chip is provided with an encapsulation layer 40. The encapsulation layer 40 is composed of a resin material. The encapsulation layer 40 has an encapsulation surface. The encapsulation layer 40 is used to wrap the chip body 20, the first magnetic shielding layer 30, and the substrate 10. The encapsulation layer 40 has a protective effect on the anti-magnetic encapsulation structure of the chip. The anti-magnetic encapsulation structure of the chip is provided with a second magnetic shielding layer 50. The second magnetic shielding layer 50 is disposed on the encapsulation surface. The second magnetic shielding layer 50 can cover the chip body 20. The second magnetic shielding layer 50 can be composed of a high magnetic permeability metal. The second magnetic shielding layer 50 is used to shield the interference of the external magnetic field on the chip body 20 in the corresponding direction of the second face of the chip body 20.

[0041] The first magnetic shielding layer 30 and the second magnetic shielding layer 50 are respectively disposed on both sides of the chip body 20. The first magnetic shielding layer 30 and the second magnetic shielding layer 50 are arranged in parallel. Moreover, the first magnetic shielding layer 30 and the second magnetic shielding layer 50 are also arranged in parallel with the chip body 20. It should be noted that the "parallel" mentioned here is not the absolute parallel in the strict mathematical sense. In the actual application scenario, when the relative positional relationship between two surfaces or structures is within a specific tolerance range, such that from the perspective of actual use effects and normal observation and measurement, they present an approximately parallel state, it can be considered that the "parallel" relationship referred to in this application is satisfied. This "parallel" state allows for a certain degree of slight deviation, which is inevitable in the actual production and manufacturing process and will not have a substantial adverse impact on the implementation and expected effects of the technical solution involved in this application.

[0042] The first magnetic shielding layer 30 and the second magnetic shielding layer 50 cooperate to shield the interference of the external magnetic field on the chip body 20. Specifically, the first magnetic shielding layer 30 and the second magnetic shielding layer 50 form an anti-magnetic encapsulation structure with a double-layer magnetic shielding layer. The double-layer magnetic shielding layer can jointly shield the interference of the external magnetic field on the chip. The first magnetic shielding layer 30 and the second magnetic shielding layer 50 have the function of magnetic conduction, thereby shielding the interference of the external magnetic field. For example, in the case where no anti-magnetic encapsulation structure is provided, the magnetic induction line loop will penetrate the chip. By providing a double-layer magnetic shielding layer on both sides of the grain unit of the chip, the magnetic induction lines can be led out from the surface of the grain unit, avoiding the magnetic induction lines from penetrating the grain unit. The double-layer magnetic shielding layer can lead out the magnetic induction lines in different directions from the surface of the grain unit, improving the anti-magnetic performance of the anti-magnetic encapsulation structure of the chip.

[0043] During the process of encapsulating the chip body 20 in this embodiment, first, the first magnetic shielding layer 30 is disposed on the surface of the substrate 10, then the chip body 20 is disposed on the first magnetic shielding layer 30, and the chip body 20 is connected to the substrate 10 by wire bonding. Then, the chip body 20, the first magnetic shielding layer 30, and the substrate 10 are encapsulated by the encapsulation layer 40. Finally, the second magnetic shielding layer 50 is disposed on the encapsulation layer 40 to form an anti-magnetic encapsulation structure with a double-layer magnetic shielding layer. The encapsulation process is more simplified, and the difficulty of wire bonding is reduced.

[0044] In this embodiment, the first magnetic shielding layer 30 may include a plurality of magnetically shielding layers stacked on top of each other, and the second magnetic shielding layer 50 may also include a plurality of magnetically shielding layers stacked on top of each other. The plurality of magnetically shielding layers stacked on top of each other may be composed of a high magnetic permeability metal. That is, both the first magnetic shielding layer 30 and the second magnetic shielding layer 50 may be composed of a plurality of high magnetic permeability metal layers stacked on top of each other. The plurality of magnetically shielding layers stacked on top of each other are used to enhance the magnetic field shielding function of the first magnetic shielding layer 30 and the second magnetic shielding layer 50. The first magnetic shielding layer 30 and the second magnetic shielding layer 50 form an anti-magnetic encapsulation structure with a double-layer magnetic shielding layer. Each magnetic shielding layer in the double-layer magnetic shielding layer may include a plurality of high magnetic permeability metal layers stacked on top of each other, and the shielding effect of the magnetic field of the overall anti-magnetic encapsulation structure of the chip is enhanced.

[0045] In this embodiment, as Figure 2 shown, a first adhesive layer 60 is provided between the first magnetic shielding layer 30 and the substrate 10. The first adhesive layer 60 may be a double-sided tape. The first adhesive layer 60 is used to bond the first magnetic shielding layer 30 to the substrate 10. The first magnetic shielding layer 30 can be adhered to the surface of the substrate 10 through the double-sided tape. Through the first adhesive layer 60, the relative fixation between the first magnetic shielding layer 30 and the substrate 10 can be achieved, and the first adhesive layer 60 can also play an insulating role between the first magnetic shielding layer 30 and the substrate 10. By bonding the first magnetic shielding layer 30 to the substrate 10 through the first adhesive layer 60, the process is simple and the processing efficiency is improved.

[0046] In this embodiment, as Figure 2 shown, a second adhesive layer 70 is provided between the chip body 20 and the first magnetic shielding layer 30. The second adhesive layer 70 may be a double-sided tape. The second adhesive layer 70 is used to bond the chip body 20 to the first magnetic shielding layer 30. The chip body 20 can be adhered to the first magnetic shielding layer 30 through the double-sided tape. Through the second adhesive layer 70, the relative fixation between the chip body 20 and the first magnetic shielding layer 30 can be achieved, and the second adhesive layer 70 can also play an insulating role between the chip body 20 and the first magnetic shielding layer 30 to prevent a short circuit between the chip body 20 and the first magnetic shielding layer 30. By bonding the chip body 20 to the first magnetic shielding layer 30 through the second adhesive layer 70, the process is simple and the reliability of the anti-magnetic encapsulation structure of the chip is improved.

[0047] In this embodiment, as Figure 2As shown, a third adhesive layer 80 is provided between the second magnetic shielding layer 50 and the encapsulation layer 40. The third adhesive layer 80 can be a double-sided tape. The third adhesive layer 80 is used to bond the second magnetic shielding layer 50 to the encapsulation layer 40. The second magnetic shielding layer 50 can be adhered to the encapsulation layer 40 through the double-sided tape. Through the third adhesive layer 80, the relative fixation between the second magnetic shielding layer 50 and the encapsulation layer 40 can be achieved. By bonding the second magnetic shielding layer 50 to the encapsulation layer 40 through the third adhesive layer 80, the process is simple, the processing efficiency is improved, and the reliability of the anti-magnetic encapsulation structure of the chip is improved.

[0048] In this embodiment, the first magnetic shielding layer 30 and the second magnetic shielding layer 50 can be composed of materials with high anti-magnetic performance. Materials with high anti-magnetic performance are usually materials with high magnetic permeability and high magnetic saturation induction intensity, which can absorb and disperse magnetic fields. By arranging the first magnetic shielding layer 30 and the second magnetic shielding layer 50 made of materials with high anti-magnetic performance in the anti-magnetic encapsulation structure, when there is a magnetic source in the external environment, the first magnetic shielding layer 30 and the second magnetic shielding layer 50 can absorb the magnetic induction lines of the external magnetic field, forming a magnetic vacuum in the area where the chip body 20 is located between the first magnetic shielding layer 30 and the second magnetic shielding layer 50, so as to block the external magnetic field from entering the chip body 20 and reduce the interference inside the anti-magnetic encapsulation structure.

[0049] In this embodiment, the encapsulation layer 40 includes a resin matrix, and a magnetic shielding material is provided in the resin matrix. The magnetic shielding material is used to enhance the magnetic field shielding function of the anti-magnetic encapsulation structure. Specifically, the encapsulation layer 40 is composed of a resin material. The magnetic shielding material can be mixed with the resin material to jointly form the encapsulation layer 40, so that the encapsulation layer 40 has anti-magnetic performance. For example, the magnetic shielding material can be processed into a powder or granular material, and then the powder or granular magnetic shielding material is mixed with the resin material, and then the mixed material is made into the encapsulation layer 40. In this way, the encapsulation layer 40 not only has the performance of encapsulation, but also has anti-magnetic performance, improving the anti-magnetic effect of the anti-magnetic encapsulation structure while ensuring the encapsulation effect.

[0050] In this embodiment, the diamagnetic materials provided in the first magnetic shielding layer 30 and the second magnetic shielding layer 50 at least include ferrite and permalloy. The diamagnetic materials provided in the first magnetic shielding layer 30 and the second magnetic shielding layer 50 can also be silicon-iron alloy, iron-silicon-chromium alloy or cobalt-iron alloy. During the process of manufacturing the magnetic shielding layer, one or more of the above diamagnetic materials can be used to form a magnetic metal composite material. By combining different diamagnetic materials, the magnetic shielding layer can have better diamagnetic properties. When manufacturing the diamagnetic encapsulation structure, mechanical strength, thermal conductivity and electrical properties also need to be considered. Encapsulation materials with good mechanical strength, thermal conductivity and electrical properties can be combined with diamagnetic materials to meet the requirements of mechanical strength, thermal conductivity and electrical properties while ensuring the diamagnetic properties, so as to ensure the normal operation of the chip under diamagnetic encapsulation. A magnetoresistive random access memory (MRAM) is provided in the chip body 20. No magnetic shielding layer is provided around the MRAM. Whether the stored data is 0 or 1 is determined by whether the magnetization directions of the internal free layer and the fixed layer of the MRAM are the same or opposite. Since the MRAM realizes data storage based on the magnetic effect, it is very sensitive to the external magnetic field. Therefore, it is necessary to shield the interference of the magnetic field on the MRAM to ensure the normal operation of the MRAM. Usually, a magnetic shielding layer is provided around the MRAM. The diamagnetic encapsulation structure of this embodiment has a double-layer magnetic shielding layer. The double-layer magnetic shielding layer is arranged in parallel on both sides of the chip body 20. The double-layer magnetic shielding layer can jointly shield the interference of the external magnetic field on the chip body 20, and thus can shield the interference of the external magnetic field on the MRAM in the chip body 20. The magnetic field direction of the MRAM is fixed. The influence of the external magnetic field on the MRAM usually comes from two directions, the south pole and the north pole. The magnetic field in the horizontal direction has little influence on the MRAM. Therefore, by arranging the first magnetic shielding layer 30 and the second magnetic shielding layer 50 in parallel on both sides of the chip body 20, the interference of the external magnetic field on the MRAM can be effectively shielded. The diamagnetic encapsulation structure with a double-layer magnetic shielding layer has a simple process and a low manufacturing cost.

[0051] This application also provides a chip, which includes a chip body 20 and a diamagnetic encapsulation structure of the chip. The chip body 20 can be a die unit, and the chip body 20 is arranged in the diamagnetic encapsulation structure of the chip. The chip body 20 is arranged between the substrate 10 and the first magnetic shielding layer 30 of the diamagnetic encapsulation structure of the chip. The second magnetic shielding layer 50 of the diamagnetic encapsulation structure of the chip is arranged on the encapsulation surface. The first magnetic shielding layer 30 and the second magnetic shielding layer 50 are arranged in parallel on both sides of the chip body 20 respectively. The first magnetic shielding layer 30 and the second magnetic shielding layer 50 form a diamagnetic encapsulation structure with a double-layer magnetic shielding layer. The double-layer magnetic shielding layer can jointly shield the interference of the external magnetic field on the chip.

[0052] The present application also provides an electronic device, including a chip. The chip includes an anti-magnetic packaging structure of the chip and a chip body 20. The anti-magnetic packaging structure of the chip is used to package the chip body 20 of the chip. During the process of packaging the chip body 20, first, a first magnetic shielding layer 30 of the anti-magnetic packaging structure of the chip is disposed on the surface of a substrate 10, then the chip body 20 is disposed on the first magnetic shielding layer 30, and the chip body 20 is connected to the substrate 10 by wire bonding. Next, the chip body 20, the first magnetic shielding layer 30, and the substrate 10 are packaged by a packaging layer 40 of the anti-magnetic packaging structure of the chip. Finally, a second magnetic shielding layer 50 of the anti-magnetic packaging structure of the chip is disposed on the packaging layer 40 to form an anti-magnetic packaging structure with a double-layer magnetic shielding layer.

[0053] The above description is only a preferred embodiment of the present utility model and an explanation of the applied technical principles. Those skilled in the art should understand that the scope of disclosure involved in the present utility model is not limited to the technical solution formed by the specific combination of the above technical features, and should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the above disclosed concept. For example, the technical solutions formed by mutually replacing the above features with the technical features (but not limited to) having similar functions disclosed in the present utility model.

[0054] In addition, although the operations are depicted in a particular order, this should not be construed as requiring that the operations be performed in the particular order shown or in a sequential order. In certain environments, multitasking and parallel processing may be advantageous. Similarly, although a number of specific implementation details are included in the above discussion, these should not be construed as limiting the scope of the present utility model. Certain features described in the context of separate embodiments may also be implemented combinatorially in a single embodiment. Conversely, the various features described in the context of a single embodiment may also be implemented separately or in any suitable sub-combination in multiple embodiments.

[0055] Although the subject matter has been described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are merely example forms of implementing the claims.

[0056] The above has described multiple embodiments of the present utility model in detail, but the present utility model is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications to the embodiments based on the concept of the present utility model, and these variations and modifications should all fall within the scope of protection required by the present utility model.

Claims

1. An anti-magnetic packaging structure for a chip, characterized in that, Comprising: A substrate having a mounting surface; A chip body having a first surface and a second surface disposed opposite to each other, and the chip body is disposed on the mounting surface through the first surface of the chip body; A first magnetic shielding layer disposed between the substrate and the chip body, and the first magnetic shielding layer is used to shield the interference of the external magnetic field on the chip body in the corresponding direction of the first surface of the chip body; A packaging layer having a packaging surface, and the packaging layer is used to enclose the chip body, the first magnetic shielding layer and the substrate; A second magnetic shielding layer disposed on the packaging surface, and the second magnetic shielding layer is used to shield the interference of the external magnetic field on the chip body in the corresponding direction of the second surface of the chip body; Wherein, the first magnetic shielding layer and the second magnetic shielding layer are arranged in parallel, and the first magnetic shielding layer and the second magnetic shielding layer cooperate to shield the interference of the external magnetic field on the chip body.

2. The anti-magnetic packaging structure of the chip according to claim 1, characterized in that, Both the first magnetic shielding layer and the second magnetic shielding layer include a plurality of superimposed magnetic shielding layers, wherein the plurality of superimposed magnetic shielding layers are used to enhance the magnetic field shielding function of the first magnetic shielding layer and the second magnetic shielding layer.

3. The anti-magnetic packaging structure of the chip according to claim 1, wherein, A first adhesive layer is disposed between the first magnetic shielding layer and the substrate, and the first adhesive layer is used to bond the first magnetic shielding layer to the substrate.

4. The anti-magnetic packaging structure of the chip according to claim 1, characterized in that, A second adhesive layer is disposed between the chip body and the first magnetic shielding layer, and the second adhesive layer is used to bond the chip body to the first magnetic shielding layer.

5. The anti-magnetic packaging structure of the chip according to claim 1, characterized in that, A third adhesive layer is disposed between the second magnetic shielding layer and the packaging layer, and the third adhesive layer is used to bond the second magnetic shielding layer to the packaging layer.

6. The anti-magnetic packaging structure of the chip according to claim 1, characterized in that, Both the first magnetic shielding layer and the second magnetic shielding layer are used to absorb the magnetic induction lines of the external magnetic field to form a magnetic vacuum in the region where the chip body is located.

7. The anti-magnetic packaging structure of the chip according to claim 1, characterized in that, The packaging layer includes a resin matrix, and a magnetic shielding material is disposed in the resin matrix, and the magnetic shielding material is used to enhance the magnetic field shielding function of the anti-magnetic packaging structure.

8. The anti-magnetic packaging structure of the chip according to claim 1, characterized in that, The anti-magnetic materials disposed in the first magnetic shielding layer and the second magnetic shielding layer at least include ferrite and permalloy; a magnetoresistive random access memory is disposed in the chip body, and no magnetic shielding layer is disposed around the magnetoresistive random access memory.

9. A chip, characterized in that, The chip includes an anti-magnetic packaging structure of the chip according to any one of claims 1-8, and the chip body of the chip is disposed in the anti-magnetic packaging structure of the chip.

10. An electronic device, characterized in that, Comprising: The chip according to claim 9, the chip includes an anti-magnetic packaging structure of the chip according to any one of claims 1-8, and the anti-magnetic packaging structure of the chip is used to package the chip body of the chip.

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