Semiconductor structure

Abstract

The utility model provides a semiconductor structure. The semiconductor structure comprises a first dielectric layer arranged on a semiconductor device, a conductive structure arranged in the first dielectric layer, a blocking structure comprising a top part and a bottom part, a conductive lining layer arranged on the blocking structure and a conductive plug arranged on the conductive lining layer. The top portion is disposed on the first dielectric layer, and the bottom portion extends into the first dielectric layer and is disposed between the conductive structure and the first dielectric layer.

Description

Technical Field

[0001] The present utility model relates to a semiconductor technology, and particularly to a semiconductor structure and a method for forming the same. Background Art

[0002] With the progress of semiconductor technology, the demand for higher storage capacity, faster processing systems, higher performance, and lower costs is increasing continuously. To meet these demands, the semiconductor industry has been continuously reducing the size of semiconductor devices, such as metal-oxide-semiconductor field-effect transistors (MOSFETs), fin field-effect transistors (finFETs), and gate-all-around (GAA) FETs located within an integrated circuit (IC) wafer. The miniaturization of the size has increased the complexity of manufacturing integrated circuits (ICs). Summary of the Utility Model

[0003] In some embodiments, a semiconductor structure is provided, including: a first dielectric layer disposed on a semiconductor device; a conductive structure disposed within the first dielectric layer; a blocking structure including a top portion and a bottom portion; a conductive liner disposed on the blocking structure; and a conductive plug disposed on the conductive liner. The top portion is disposed on the first dielectric layer, and the bottom portion extends into the first dielectric layer and is disposed between the conductive structure and the first dielectric layer.

[0004] According to an embodiment of the present utility model, it further includes: an etch stop layer disposed between the conductive structure and the first dielectric layer, wherein the bottom portion is disposed on and in contact with the etch stop layer.

[0005] According to an embodiment of the present utility model, it further includes: a second dielectric layer disposed on the first dielectric layer, wherein the top portion is disposed within the second dielectric layer.

[0006] According to an embodiment of the present utility model, wherein the bottom portion extends within the first dielectric layer to a distance that is 10% to 50% of the height of the first dielectric layer.

[0007] According to an embodiment of the present utility model, wherein the bottom portion surrounds the sidewall of the conductive structure.

[0008] According to an embodiment of the present utility model, it further includes: an etch stop layer disposed on the first dielectric layer; and a second dielectric layer disposed on the etch stop layer.

[0009] According to an embodiment of the present invention, the upper surface of the second dielectric layer and the barrier structure are substantially coplanar with each other.

[0010] According to an embodiment of the present invention, the upper surface of the conductive liner and the conductive plug are substantially coplanar with each other.

[0011] According to an embodiment of the present invention, the bottom portion extends into the first dielectric layer to a distance in the range of 0.5 nm to 10 nm.

[0012] According to an embodiment of the present invention, the upper surface of the first dielectric layer and the conductive structure are substantially coplanar with each other.

[0013] At least one embodiment of the present invention has the following advantages or technical effects:

[0014] Having a barrier structure in the interconnect can reduce the resistance of the interconnect and minimize or prevent metal diffusion into the semiconductor device. Additionally, the barrier structure interconnect having an inner connection portion and a contact portion may include (e.g., barrier structure 134) a liner and / or plug that can surround the interconnect to reduce the resistance of the interconnect. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1A An isometric view of an integrated circuit (IC) according to some embodiments is shown.

[0016] Figures 1B - 1I A cross-sectional view of an integrated circuit (IC) having a conductive structure according to some embodiments is shown.

[0017] Figure 2 A flowchart of a method for forming an integrated circuit (IC) having a conductive structure according to some embodiments is shown.

[0018] Figures 3 - 21 Cross-sectional views of an integrated circuit (IC) having a conductive structure at various stages of its manufacturing process according to some embodiments are shown.

[0019] Wherein the reference numerals are described as follows:

[0020] 100: Integrated circuit

[0021] 101: Field effect transistor 101; N-type field effect transistor; P-type field effect transistor; Fin field effect transistor; Gate-all-around field effect transistor

[0022] 102: Inner connection structure

[0023] 103: Region

[0024] 104: Substrate

[0025] 106: Shallow trench isolation region

[0026] 108: Fin structure

[0027] 110A, 110B, 110C: Source / drain region

[0028] 112A, 112B, 112C: Gate structure

[0029] 113: Gate stack

[0030] 113A: Interface oxide layer

[0031] 113B: High-k gate dielectric layer

[0032] 113C: Work function metal layer

[0033] 113D: Gate metal fill layer

[0034] 114: Gate spacer

[0035] 115: Gate capping structure

[0036] 115A: Conductive gate cap

[0037] 115B: Insulating gate cap

[0038] 117: Inner spacer layer

[0039] 118A: Etch stop layer; First etch stop layer

[0040] 118B: Etch stop layer; Second etch stop layer

[0041] 120A: First interlayer dielectric layer

[0042] 120B: Second interlayer dielectric layer

[0043] 121: Nanostructure channel region

[0044] 122A, 122B: Source / drain contact structure

[0045] 123A: Silicide layer

[0046] 123B: Adhesion layer

[0047] 123C: Contact plug

[0048] 124: Via structure; Linerless via structure

[0049] 124t: Top portion

[0050] 124t1: Straight edge profile

[0051] 124t2: Inclined Edge Profile Outline

[0052] 124t3: Curved Edge Profile Outline

[0053] 125, 127: Interface

[0054] 126: Gate Contact Structure; Gate Contact Structure without Liner

[0055] 128A, 128B, 129: Etch Stop Layer

[0056] 130: Interlayer Dielectric Layer

[0057] 132, 133: Interconnect

[0058] 134, 135: Barrier Structure

[0059] 134A, 135A: Interconnection Part; Top Part

[0060] 134B, 135B: Contact Part; Bottom Part

[0061] 134s, 135s: Lower Surface

[0062] 136, 140B, 142B: Liner

[0063] 138: Conductive Plug

[0064] 140: Via Structure; Via Structure with Liner

[0065] 140A: Via Plug

[0066] 140At: Top Part

[0067] 142: Gate Contact Structure; Gate Contact Structure with Liner

[0068] 142A: Contact Plug

[0069] 200: Method

[0070] 205, 210, 215, 220: Operation Steps 424, 426, 1540, 1542: Top Edge Interface

[0071] 544, 744, 1644: Trench

[0072] 628, 834, 936, 938, 1355, 1728: Film Layer

[0073] 746, 1346: Opening

[0074] D1, D2: Distance

[0075] H1: Height

[0076] T1, T2: Thickness. Detailed implementation manners

[0077] The following disclosure provides many different embodiments or examples for implementing different characteristic components of the present utility model. The following disclosure is a specific example of describing each component and its arrangement manner to simplify the present disclosure. Of course, these are only examples for illustration and are not used to define the present creation. For example, if the following disclosure describes forming a first characteristic component on or above a second characteristic component, it means that it includes an embodiment in which the formed first characteristic component and the second characteristic component are in direct contact, and also includes an embodiment in which additional characteristic components can be formed between the first characteristic component and the second characteristic component, so that the first characteristic component and the second characteristic component may not be in direct contact. In addition, the present disclosure will repeat reference numerals and / or words in various different examples. The repetition is for the purpose of simplification and clarity, rather than self-listing the relationship between the various different embodiments and / or configurations being discussed.

[0078] Spatially related terms, such as "below", "beneath", "under", "above", "on", etc., are used herein to easily express the relationship between elements or characteristic components shown in the drawings in this specification and other elements or characteristic components. These spatially related terms cover not only the orientations shown in the drawings but also different orientations during the use or operation of the device. This device can have different orientations (rotated 90 degrees or other orientations), and the spatially related symbols used herein have corresponding interpretations.

[0079] It should be noted that the reference to "an embodiment", "one embodiment", "exemplary embodiment", "exemplary", etc. in the specification indicates that the described embodiment may include specific characteristic components, structures, or characteristics, but each embodiment does not necessarily include the specific characteristic components, structures, or characteristics. Furthermore, the above terms do not necessarily refer to the same embodiment. Furthermore, when combining an embodiment to describe a specific characteristic component, structure, or characteristic, whether explicitly stated or not, implementing the above characteristic components, structures, or characteristics in combination with other embodiments will be within the knowledge scope of those with ordinary knowledge in the relevant technical field.

[0080] It should be understood that the terms or phrases herein are for the purpose of illustration rather than limitation, so that those with ordinary knowledge in the relevant technical field can interpret the terms or phrases in this specification according to the teachings herein.

[0081] In some embodiments, the terms “about” and “substantially” may mean that a value of a given quantity varies within 5% to 20% of that numerical value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±6%, ±7%, ±8%, ±8%, ±9%, ±10 - 15%, ±15 - 20%). These numerical values are merely examples and are not limiting. The terms “about” and “substantially” may mean a percentage of a numerical value as interpreted by one of ordinary skill in the art in light of the teachings herein.

[0082] The fin structures disclosed herein can be patterned by any suitable method. For example, one or more optical lithography processes (including double patterning or multiple patterning processes) can be used to pattern the fin structures. Double patterning or multiple patterning processes can combine optical lithography and self-alignment processes, thereby allowing the formation of patterns having, for example, smaller pitch than that obtained using a single direct optical lithography process. For example, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process, and then the sacrificial layer is removed, and the remaining spacers can be used to pattern the fin structures.

[0083] A gate-all-around (GAA) transistor structure can be patterned by any suitable method. For example, one or more optical lithography processes (including double patterning or multiple patterning processes) can be used to pattern the fin structures. Double patterning or multiple patterning processes can combine optical lithography and self-alignment processes, thereby allowing the formation of patterns having, for example, smaller pitch than that obtained using a single direct optical lithography process. For example, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. Then the sacrificial layer is removed, and the remaining spacers can be used to pattern the gate-all-around (GAA) transistor structure.

[0084] The increasing demand for small, portable, multi-functional electronic devices has increased the demand for low-power devices that are capable of performing increasingly complex and sophisticated functions while providing increasing storage capacity. Accordingly, the semiconductor industry continues to adopt semiconductor devices and interconnect structures to fabricate low-cost, high-performance, and low-power integrated circuits (ICs). These goals are largely achieved by miniaturizing the size of semiconductor devices and / or interconnect structures. However, the continued miniaturization of the interconnect lines of the interconnect structures poses significant challenges, such as an increase in the resistance of the interconnect lines and an increase in metal diffusion from the interconnect lines to the underlying contact structures of the semiconductor devices.

[0085] To address the above challenges, the present disclosure provides an exemplary integrated circuit (IC) having a barrier structure in an interconnect of an inner connection structure to reduce the resistance of the interconnect and minimize or prevent metal diffusion from a liner and / or plug in the interconnect to a contact structure under a semiconductor device (e.g., a gate-all-around (GAA) field-effect transistor (FET) or a fin field-effect transistor (finFET)). Additionally, the present disclosure provides an exemplary method of forming an integrated circuit (IC). In some embodiments, the interconnect may be disposed on a contact structure of a semiconductor device and on an interlayer dielectric (ILD) layer surrounding the contact structure. The interconnect may include a barrier structure having an inner connection portion and a contact portion. The inner connection portion may surround an inner connection liner and / or plug of the interconnect and may have a thin profile with a thickness of about 0.5 nm to 3 nm to reduce the resistance of the interconnect.

[0086] Due to the thin profile of the inner connection portion, there may be non-uniformity in the thickness of the bottom portion of the inner connection portion. The thickness non-uniformity may occur at the interface between the underlying contact structure and the interlayer dielectric (ILD) layer. Such thickness non-uniformity may cause metal to diffuse from the inner connection liner and / or plug through the top edge and / or sidewall of the contact structure to the contact structure. The presence of the contact portion may prevent or minimize the above-mentioned metal diffusion to the contact structure and improve the performance of the integrated circuit (IC). The contact portion may extend from the lower surface of the inner connection portion and surround the top portion of the contact structure to provide a metal diffusion barrier layer at the top edge and / or sidewall of the contact structure. In some embodiments, the contact portion may have a thickness of about 0.5 nm to 2 nm and may extend a distance of about 10% to 50% of the thickness of the interlayer dielectric (ILD) layer.

[0087] Figure 1A An isometric view of an integrated circuit (IC) 100 having a field-effect transistor (FET) 101 and an inner connection structure 102 disposed on the FET 101 is shown, according to some embodiments. Figures 1B - 1I Shows, according to some embodiments, along Figure 1A A different cross-sectional schematic view of the integrated circuit (IC) 100 along line A-A. Figures 1B - 1I A cross-sectional schematic view of the integrated circuit (IC) 100 having additional structures is shown. For simplicity, the additional structures are not shown in Figure 1A In. Figures 1C - 1H Shows Figure 1B And Figure 1I In region 103 along Figure 1A Respective enlarged cross-sectional views along line A-A. Unless otherwise noted, the elements in the figures and Figures 1A - 1IElements with the same reference numerals in the [description] may be used interchangeably with each other. In some embodiments, the field effect transistor (FET) 101 may represent an n-type field effect transistor (FET) 101 (NFET 101) or a p-type field effect transistor (FET) 101 (PFET 101), and unless otherwise specified, the description of the field effect transistor (FET) 101 applies to both the n-type field effect transistor (FET) 101 and the p-type field effect transistor (FET) 101.

[0088] Please refer to Figure 1A and 1B , in some embodiments, the field effect transistor (FET) 101 may include (i) a substrate 104, (ii) a shallow trench isolation (STI) region 106 disposed on the substrate 104, (iii) a fin structure 108 disposed on the substrate 104, (iv) source / drain (S / D) regions 110A - 110C disposed on the fin structure 108 (the S / D region 110C is visible in Figure 1A ; the source / drain (S / D) regions 110A - 110B are visible in Figure 1B and Figure 1I ), (v) gate structures 112A - 112C disposed on the fin structure 108, (vi) gate spacer walls 114 disposed on the gate structures 112A - 112C, (vii) a first etch stop layer (ESL) 118A disposed on the source / drain (S / D) regions 110A - 110C, (viii) a first interlayer dielectric (ILD) layer 120A disposed on the first etch stop layer (ESL) 118A, (ix) a second etch stop layer (ESL) 118B disposed on the first etch stop layer (ESL) 118A and the first interlayer dielectric (ILD) layer 120A, (x) a second interlayer dielectric (ILD) layer 120B disposed on the second etch stop layer (ESL) 118B, (xi) source / drain (S / D) contact structures 122A and 122B respectively disposed on the source / drain (S / D) regions 110A and 110B, (xii) a via structure 124 disposed on the contact structure 122B, and (xiii) a gate contact structure 126 disposed on the gate structure 112A. Unless otherwise specified, the descriptions of the source / drain (S / D) regions 110A - 110C are interchangeable with each other, the descriptions of the gate structures 112A - 112C are interchangeable with each other, and the descriptions of the contact structures 122A and 122B are interchangeable with each other. The source / drain (S / D) regions 110A - 11C may refer to the source or the drain, and are individually or jointly referred to as the source or the drain depending on the context. Unless otherwise specified, the description of the via structure 124 applies to the gate contact structure 126.

[0089] In some embodiments, the substrate 104 may be a semiconductor material such as silicon, germanium (Ge), silicon germanium (SiGe), silicon-on-insulator (SOI) structures, and combinations thereof. Further, the substrate 104 may be doped with p-type dopants (e.g., boron, indium, aluminum, or gallium) or n-type dopants (e.g., phosphorus or arsenic). In some embodiments, the shallow trench isolation (STI) regions 106, the gate spacer 114, the etch stop layer (ESL) 118A, and the interlayer dielectric (ILD) layer 120A may include insulating materials such as silicon dioxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiOC), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and silicon germanium oxide (SiGeOx). In some embodiments, the etch stop layer (ESL) 118B and the interlayer dielectric (ILD) layer 120B may include dielectric materials such as lanthanum oxide (LaO), aluminum oxide (Al2O3), yttrium oxide (Y2O3), tantalum carbonitride (TaCN), zirconium silicide (ZrSi), SiOCN, SiOC, SiCN, zirconium nitride (ZrN), zirconium aluminum oxide (ZrAlO), TiO2, Ta2O3, ZrO2, HfO2, SiN, hafnium silicide (HfSi), aluminum oxynitride (AlON), SiO2, SiC, zinc oxide (ZnO). In some embodiments, the etch stop layer (ESL) 118B may have a thickness of about 3 nm to 40 nm, and the interlayer dielectric (ILD) layer 120B may have a thickness of about 3 nm to 50 nm along the Z-axis for sufficient electrical isolation between the via structure 124 and the gate contact structure 126.

[0090] In some embodiments, the fin structure 108 may include a material similar to the substrate 104. The fin structure 108 may have long side edges extending along the X-axis. For an N-type field effect transistor (NFET) 101, the source / drain (S / D) regions 110A - 110C may include epitaxially grown semiconductor material (e.g., Si) and n-type dopants (e.g., phosphorus and other suitable n-type dopants). For a P-type field effect transistor (PFET) 101, the source / drain (S / D) regions 110A - 110C may include epitaxially grown semiconductor material (e.g., Si and SiGe) and p-type dopants (e.g., boron and other suitable p-type dopants).

[0091] In some embodiments, each of the gate structures 112A-112C may include a gate stack 113 disposed on the fin structure 108 and a gate capping structure 115 disposed on the gate stack 113. In some embodiments, the gate stack 113 may include (i) an interfacial oxide (IL) layer 113A, (ii) a high-k (HK) gate dielectric layer 113B disposed on the interfacial oxide (IL) layer 113A, (iii) a work function metal (WFM) layer 113C disposed on the high-k (HK) gate dielectric layer 113B, and (iv) a gate metal fill layer 113D disposed on the work function metal (WFM) layer 113C. In some embodiments, each of the gate structures 112A-112C may have a gate length of about 2 nm to 50 nm along the X axis.

[0092] In some embodiments, the interfacial oxide (IL) layer 113A may include SiO2, SiGeOx, or germanium oxide (GeOx). In some embodiments, the high-k (HK) gate dielectric layer 113B may include a high-k dielectric material such as hafnium oxide (HfO2), titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O3), hafnium silicate (HfSiO4), zirconium oxide (ZrO2), and zirconium silicate (ZrSiO2). In some embodiments, the work function metal (WFM) layer 113C may include titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), tantalum aluminum (TaAl), tantalum aluminum carbide (TaAlC), aluminum-doped titanium, aluminum-doped titanium nitride, aluminum-doped tantalum, aluminum-doped tantalum nitride, or other suitable aluminum-based materials for n-type field effect transistors (FETs). In some embodiments, the work function metal (WFM) layer 113C may include titanium-based or tantalum-based nitrides or alloys substantially free of aluminum (e.g., without Al), such as titanium nitride (TiN), titanium silicon nitride (TiSiN), titanium gold (Ti-Au) alloy, titanium copper (Ti-Cu) alloy, tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tantalum gold (Ta-Au) alloy, and tantalum copper (Ta-Cu) for p-type field effect transistors (FETs). In some embodiments, the gate metal fill layer 113D may include a suitable conductive material such as tungsten (W), titanium (Ti), silver (Ag), ruthenium (Ru), molybdenum (Mo), copper (Cu), cobalt (Co), aluminum (Al), iridium (Ir), nickel (Ni), metal alloys, and combinations thereof.

[0093] In some embodiments, each gate capping structure 115 may include a conductive gate cap 115A disposed on the gate stack 113 and an insulating gate cap 115B disposed on the conductive gate cap 115A. The insulating gate cap 115B protects the underlying conductive gate cap 115A and the gate stack 113 from structural and / or compositional degradation during subsequent processes of the field effect transistor (FET) 101. In some embodiments, the insulating gate cap 115B may include a dielectric material such as LaO, Al2O3, Y2O3, TaCN, ZrSi, SiOCN, SiOC, SiCN, ZrN, ZrAlO, TiO2, Ta2O3, ZrO2, HfO2, SiN, HfSi, AlON, SiO2, SiC, and ZnO. In some embodiments, the top portion of the insulating gate cap 115B may have a thickness T1 of about 1 nm to 30 nm, and the bottom portion of the insulating gate cap 115B may have a thickness T2 of about 1 nm to 50 nm for sufficient protection of the conductive gate cap 115A and the gate stack 113. The top portion of the insulating gate cap 115B may not be located on the gate spacer 114, while its bottom portion is located between the gate spacers 114, and vice versa.

[0094] The conductive gate cap 115A provides a conductive interface between the gate stack 113 and the gate contact structure 126 to electrically connect the gate stack 113 to the gate contact structure 126 without directly forming the gate contact structure 126 on the gate stack 113 or within the gate contact structure 126. The gate contact structure 126 is not directly formed on or within the gate stack 113 to prevent any process materials used to form the gate contact structure 126 from contaminating the gate stack 113. In some embodiments, the conductive gate cap 115A may include a metal material such as W, Ru, Ir, Mo, other suitable metal materials, and combinations thereof. In some embodiments, the conductive gate cap 115A may have a thickness along the Z-axis of about 1 nm to 10 nm to adequately control the depth profile of the gate contact structure 126.

[0095] In some embodiments, each of the source / drain (S / D) contact structures 122A and 122B may include (i) a silicide layer 123A disposed within each of the source / drain (S / D) regions 110A and 110B, (ii) an adhesion layer 123B disposed on the silicide layer 123A, and (iii) a contact plug 123C disposed on the adhesion layer 123B. In some embodiments, for an N-type field effect transistor (NFET) 101, the silicide layer 123A may include titanium silicide (TixSiy), tantalum silicide (TaxSiy), molybdenum silicide (MoxSiy), zirconium silicide (ZrxSiy), hafnium silicide (HfxSiy), scandium silicide (ScxSiy), yttrium silicide (YxSiy), terbium silicide (TbxSiy), lutetium silicide (LuxSiy), erbium silicide (ErxSiy), ytterbium silicide (YbxSiy), europium silicide (EuxSiy), thorium silicide (ThxSiy), other suitable metal silicide materials, or a combination thereof. In some embodiments, for a P-type field effect transistor (PFET) 101, the silicide layer 123A may include nickel silicide (NixSiy), cobalt silicide (CoxSiy), manganese silicide (MnxSiy), tungsten silicide (WxSiy), iron silicide (FexSiy), rhodium silicide (RhxSiy), palladium silicide (PdxSiy), ruthenium silicide (RuxSiy), platinum silicide (PtxSiy), iridium silicide (IrxSiy), osmium silicide (OsxSiy), other suitable metal silicide materials, or a combination thereof.

[0096] In some embodiments, the adhesion layer 123B (also referred to as a "liner layer" or a "glue layer") may include a metal nitride, such as titanium nitride (TiN), tantalum nitride (TaN), and other suitable metal nitride materials. In some embodiments, the contact plug 123C may include a conductive material having a low resistivity (e.g., a resistivity of about 50 μΩ-cm or less), such as W, Ru, Al, Mo, Ir, Ni, Co, osmium (Os), rhodium (Rh), other suitable low resistivity conductive materials, and combinations thereof.

[0097] Please refer to Figures 1B - 1E, the source / drain (S / D) contact structure 122B can be electrically connected to the upper internal connection structure 102 through the via structure 124. The bottom of the via structure 124 can be disposed within the source / drain (S / D) contact structure 122B and can include a conductive material such as W, Ru, Al, Mo, Ti. In some embodiments, the conductive material of the via structure 124 is formed by a bottom-up method and without a liner (also referred to as an "adhesion layer" or "glue layer") along the sidewalls of the via structure 124. In this way, the via structure 124 can be referred to as a "linerless via structure 124". In some embodiments, the via structure 124 can have different top edge profile contours, such as Figure 1C the straight edge profile contour 124t1 shown in Figure 1D the inclined edge profile contour 124t2 shown in Figure 1E and the curved edge profile contour 124t3 shown in Figure 1C . The top edge profile contour of the via structure 124 can depend on the configuration of the portion of the internal connection structure 102 surrounding the top portion of the via structure 124, as described in detail below. In some embodiments, the via structure 124 having the top edge profile contour 124t1 can have an upper surface substantially coplanar with the upper surface of the interlayer dielectric (ILD) layer 120B, as shown in Figure 1C . On the other hand, the upper surface of the via structure 124 having the top edge profile contour 124t2 or 124t3 can be at a higher horizontal surface plane height than the upper surface of the interlayer dielectric (ILD) layer 120B, as shown in Figure 1D and 1E .

[0098] In some embodiments, instead of the via structure 124, the field effect transistor (FET) 101 can have a via structure 140 disposed within the source / drain (S / D) contact structure 122B, as shown in Figures 1F - 1H . The via structure 140 can include a via plug 140A and a liner 140B along the sidewalls and surrounding the via plug 140A, where the via structure 140 can also be referred to as a "lined via structure 140". Unless otherwise specified, the description of the via structure 124 is applicable to the via plug 140A. In some embodiments, the liner 140B can include W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, TaN, TiO2, ZnO, or Al2O3. In some embodiments, the liner 140B can have a thickness of about 0.1 nm to 3 nm. The materials of the via plug 140A and the liner 140B can be different from each other.

[0099] Refer to Figures 1B - 1E, the gate structure 112A can be electrically connected to the upper internal connection structure 102 through the gate contact structure 126. The gate contact structure 126 can be disposed within the conductive gate capping 115A and can include a conductive material such as W, Ru, Al, Mo, Ti. Similar to the via structure 124, the gate contact structure 126 can be formed without a liner and can thus be referred to as the "linerless gate contact structure 126". In some embodiments, the gate contact structure 126 can have a height of approximately 5 nm to 80 nm. In some embodiments, the gate contact structure 126, the contact plug 123C, and the via structure 124 can have the same conductive material. In some embodiments, the gate contact structure 126, the contact plug 123C, and the via structure 124 can have ruthenium. In some embodiments, instead of the gate contact structure 126, the field effect transistor (FET) 101 can have a gate contact structure 142 disposed within the gate structure 112A, as Figures 1F - 1H shown. The gate contact structure 142 can include a contact plug 142A and a liner 142B along the sidewalls and surrounding the contact plug 142A, where the gate contact structure 142 can also be referred to as the "lined gate contact structure 142". Unless otherwise specified, the description of the gate contact structure 126 is applicable to the contact plug 142A. Unless otherwise specified, the descriptions of the via structure 140, the via plug 140A, and the liner 140B are respectively applicable to the gate contact structure 142, the contact plug 142A, and the liner 142B.

[0100] Please refer to Figure 1B and Figure 1C, the inner connection structure 102 can be disposed on the interlayer dielectric (ILD) layer 120B, the via structure 124, and the gate contact structure 126. In some embodiments, the inner connection structure 102 can include (i) etch stop layers (ESLs) 128A and 128B, (ii) an interlayer dielectric (ILD) layer 130 disposed on the etch stop layer (ESL) 128A, and (iii) inner wiring 132. The etch stop layer (ESL) 128A can be directly disposed on the interlayer dielectric (ILD) layer 120B. The etch stop layer (ESL) 128B can be disposed on the interface 125 between the top portion of the interlayer dielectric (ILD) layer 120B and the via structure 124 and between the interlayer dielectric (ILD) layer 120B and the bottom portion of the via structure 124. In some embodiments, the etch stop layers (ESLs) 128A and 128B can include dielectric materials such as, for example, LaO, Al2O3, Y2O3, TaCN, ZrSi, SiOCN, SiOC, SiCN, ZrN, ZrAlO, TiO2, Ta2O3, ZrO2, HfO2, SiN, HfSi, AlON, SiO2, SiC, and ZnO. The interlayer dielectric (ILD) layer 130 can include a low-k dielectric material having a dielectric constant lower than that of SiO2. In some embodiments, the low-k (LK) or ultra-low-k (ELK) dielectric material can include SiOC, SiCN, or SiOCN.

[0101] The inner wiring 132 can electrically connect the field effect transistor (FET) 101 to a power supply and / or an active device. In some embodiments, each inner wiring 132 can include (i) a barrier structure 134, (ii) a liner layer 136 disposed on the barrier structure 134, and (iii) a conductive plug 138 disposed on the liner layer 136. In some embodiments, the barrier structure 134 can include a conductive material such as W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, and TaN. In some embodiments, the liner layer 136 can be used as a seed layer for forming the conductive plug 138 and can include a conductive material such as Co, W, Ru, Al, Mo, Ti, TiN, TiSi, CoSi, NiSi, Cu, and TaN. In some embodiments, the conductive plug 138 can include a conductive material such as W, Ru, Al, Mo, Ti, Cu, and Co. The material of the barrier structure 134 can be different from the materials of the liner layer 136 and the conductive plug 138. In some embodiments, the liner layer 136 can have a thickness of about 0.1 nm to 3 nm to sufficiently form the conductive plug 138. In some embodiments, the liner layer 136 can be absent, and the conductive plug 138 can be directly disposed on the barrier structure 134.

[0102] The barrier structure 134 can be used to prevent or minimize the diffusion of metal atoms from the liner 136 and / or the conductive plug 138 to the via structure 124, while minimizing the resistance of the interconnect 132. In some embodiments, the barrier structure 134 can include (i) an interconnect portion 134A (also referred to as the "top portion 134A") and (ii) a contact portion 134B (also referred to as the "bottom portion 134B"). The interconnect portion 134A can directly contact and surround the sidewalls and the lower surface of the liner 136 (or the conductive plug 138 if the liner 136 is absent). Further, the interconnect portion 134A can be directly disposed on the via structure 124. In some embodiments, the interconnect portion 134A can have a thickness of about 0.5 nm to 2 nm to minimize the resistance of the interconnect 132 while preventing or minimizing the diffusion of metal atoms. The liner 136 and / or the conductive plug 138 are connected to the via structure 124. Since the interconnect portion 134A has a thin profile, if formed above the top edge interface (not shown) between the interlayer dielectric (ILD) layer 120B and the via structure 124, defects may exist in the bottom portion of the interconnect portion 134A. These defects may be vulnerable to metal diffusion from the liner 136 and / or the conductive plug 138 to the via structure 124. The formation of the above-mentioned top edge interface below the lower surface 134s of the interconnect portion 134A can be prevented by the contact portion 134B. The presence of the contact portion 134B can reduce the trade-off between minimizing the resistance of the interconnect 132 and preventing metal diffusion from the liner 136 and / or the conductive plug 138 to the via structure 124.

[0103] The contact portion 134B can be disposed between the top portion of the interlayer dielectric (ILD) layer 120B and the via structure 124 to prevent the formation of the top edge interface below the lower surface 134s, and can be disposed on the etch stop layer (ESL) 128B to prevent the formation of the contact portion 134B on the interface 125. Further, the contact portion 134B can extend a distance D1 in the negative Z direction from the lower surface 134s of the interconnect portion 134A and surround the top portion of the via structure 124. In some embodiments, the contact portion 134B can have a thickness of about 1 nm to 2 nm, and the distance D1 can be about 0.5 nm to 10 nm, or about 10% to 50% of the height H1 of the interlayer dielectric (ILD) layer 120B. Within these ranges of the thickness and the distance D1, the contact portion 134B together with the interconnect portion 134A can sufficiently prevent or minimize the diffusion of metal atoms from the liner 136 and / or the conductive plug 138 to the via structure 124 while minimizing the resistance of the interconnect 132. In some embodiments, the interface between the contact portion 134B and the via structure 124 can be substantially linear, which can control the top edge profile of the via structure 124 to a straight edge profile 124t1.

[0104] Please refer to Figure 1D , in some embodiments, the inner connection structure 102 may include inner connection lines 133 and an etch stop layer (ESL) 129, instead of inner connection lines 132 and etch stop layers (ESL) 128A and 128B. Unless otherwise specified, Figure 1C the description of the inner connection structure 102 of Figure 1D is applicable to the inner connection structure 102 of

[0105] Similar to the barrier structure 134, the barrier structure 135 can be used to prevent or minimize the diffusion of metal atoms from the liner 136 and / or the conductive plug 138 to the via structure 124, while minimizing the resistance of the inner connection line 133. The barrier structure 135 may include (i) an inner connection portion 135A (also referred to as "top portion 135A") and (ii) a contact portion 135B (also referred to as "bottom portion 135B"). The inner connection portion 135A may directly contact and surround the sidewalls and the lower surface of the liner 136 (or the conductive plug 138 if the liner 136 is absent). Furthermore, the inner connection portion 135A may be directly disposed on the via structure 124. In some embodiments, the inner connection portion 135A may have a thickness of about 0.5 nm to 2 nm to minimize the resistance of the inner connection line 133 while preventing or minimizing the diffusion of metal atoms from the inner connection line 133. The liner 136 and / or the conductive plug 138 are connected to the via structure 124.

[0106] Similar to the contact portion 134B, the contact portion 135B can be used to prevent the formation of a top edge interface below the lower surface 135s of the inner connection portion 135A. The contact portion 135B can surround the top portion 124t of the via structure 124 and can be disposed on the interlayer dielectric (ILD) layer 120B to prevent the formation of a top edge interface below the lower surface 135s. Furthermore, the contact portion 135B can be disposed in the etch stop layer (ESL) 129 and extend a distance D2 from the lower surface 135s of the inner connection portion 135A in the negative Z direction. In some embodiments, the contact portion 134B can have a thickness of about 1 nm to 2 nm, and the distance D2 can be less than the thickness of the etch stop layer (ESL) 129. Within these ranges of the thickness and the distance D2, the contact portion 135B together with the inner connection portion 135A can sufficiently prevent or minimize the diffusion of metal atoms from the liner 136 and / or the conductive plug 138 to the via structure 124 while minimizing the resistance of the inner connection 135. In some embodiments, due to the slanted edge profile 124t2 of the via structure 124, an inclined interface can be formed between the contact portion 135B and the via structure 124.

[0107] Please refer to Figure 1E , in some embodiments, the inner connection 133 can be disposed on the via structure 124 and the gate contact structure 126 that do not have a slanted edge profile 124t2 but have a curved edge profile 124t3. Unless otherwise specified, the description of Figure 1D the inner connection structure 102 is applicable to the inner connection structure 102 of FIG. 1E. In some embodiments, due to the curved edge profile 124t3 of the via structure 124, a curved interface can be formed between the contact portion 135B and the via structure 124.

[0108] Please refer to Figure 1F , in some embodiments, the inner connection structure 102 can be disposed on the via structure 140 and the gate contact structure 126 instead of on the via structure 124 and the gate contact structure 126. Unless otherwise specified, Figure 1C the description of the inner connection structure 102 is applicable to Figure 1FThe inner connection structure 102 of the via plug 140A can be formed by the etch stop layer (ESL) 128B. The etch stop layer (ESL) 128B can be disposed between the top portion of the interlayer dielectric (ILD) layer 120B and the via plug 140A, and can be disposed on the liner 140B and on the interface 127 between the interlayer dielectric (ILD) layer 120B and the bottom portion of the via structure 140. The inner connection portion 134A can be directly disposed on the via plug 140A. The contact portion 134B can be disposed between the top portion of the interlayer dielectric (ILD) layer 120B and the via plug 140A to prevent the formation of a top edge interface below the lower surface 134s. Furthermore, the contact portion 134B can surround the top portion of the via plug 140A. In some embodiments, the interface between the contact portion 134B and the via plug 140A may be substantially linear, which may control the top edge cross-sectional profile of the via plug 140A to be a straight edge cross-sectional profile 124t1.

[0109] Please refer to Figure 1G , the internal connection 132 may be replaced by the internal connection 133 disposed on the via structure 140 and the gate contact structure 142. Unless otherwise specified, Figure 1D The description of the inner connection structure 102 is generally applicable to Figure 1G The inner connection structure 102 of the via structure 102. The inner connection portion 135A can be directly disposed on the via structure 140. The contact portion 135B can surround the top portion 140t of the via structure 140 and can be disposed on the interlayer dielectric (ILD) layer 120B. The contact portion 135B can directly contact the top edge and sidewall of the liner 140B. In some embodiments, due to the inclined edge profile 124t2 of the via structure 140, an inclined interface can be formed between the contact portion 135B and the via structure 140.

[0110] Please refer to Figure 1H In some embodiments, the interconnect 133 may be disposed on the via structure 140 and the gate contact structure 142 that have a curved edge profile 124t3 instead of an inclined edge profile 124t2. Figure 1G The description of the inner connection structure 102 is generally applicable to Figure 1H The inner connection structure 102 is different from Figure 1G In the via structure 140 of FIG. 1H , the top portion 140At of the via plug 140A is not surrounded by the liner 140B in the via structure 140 of FIG. 1H . As a result, the contact portion 135B can directly contact and surround the top portion 140At of the via plug 140A, and can be disposed on the upper surface of the liner 140B and the interlayer dielectric (ILD) layer 120B. In some embodiments, due to the curved edge profile 124t3 of the via plug 140A, a curved interface can be formed between the contact portion 135B and the via plug 140.

[0111] The above descriptions of the inner connection structure 102 with respect to the via hole structure 124 and the via hole structure 140 are respectively applicable to the gate contact structure 126 and the gate contact structure 142.

[0112] Please refer to Figure 1I , in some embodiments, the field effect transistor (FET) 101 may be a gate-all-around field effect transistor (GAA FET) 101, rather than Figure 1B the fin field effect transistor (finFET) 101 shown. For the gate-all-around field effect transistor (GAA FET) 101, the gate structures 112A - 112C may have a cross-sectional schematic diagram as Figure 1I shown, rather than having Figure 1B the cross-sectional schematic diagram shown. The gate structures 112A - 112C of the gate-all-around field effect transistor (GAA FET) 101 may surround the nanostructure channel region 121. As used herein, the term "nanostructure" defines a structure, film layer, and / or region having a horizontal dimension (e.g., along the X-axis and / or Y-axis) and / or a vertical dimension (e.g., along the Z-axis) less than about 100 nm, such as about 90 nm, about 50 nm, about 10 nm, or other values less than about 100 nm are also within the scope of the present disclosure. In some embodiments, the nanostructure channel region 121 may be in the form of nanosheets, nanowires, nanorods, nanotubes, or other suitable nanostructure shapes.

[0113] The nanostructure channel region 121 may include a semiconductor material similar to or different from the substrate 104. In some embodiments, the nanostructure channel region 110 may include Si, SiAs, silicon phosphide (SiP), SiC, SiCP, SiGe, silicon germanium boron (SiGeB), germanium boron (GeB), silicon-germanium-tin-boron (SiGeSnB), III-V group semiconductor compounds, or other suitable semiconductor materials. Although the nanostructure channel region 121 is shown with a rectangular cross-section, the nanostructure channel region 121 may have a cross-section of other geometric shapes (e.g., circular, elliptical, triangular, or polygonal). The gate portions of the gate structures 112A - 112C surrounding the nanostructure channel region 121 may be electrically isolated from the adjacent source / drain (S / D) regions 110A - 110C by an inner spacer layer 117. The inner spacer layer 117 may include an insulating material, such as SiOx, SiN, SiCN, SiOCN, and other suitable insulating materials.

[0114] Figure 2 Shows a flowchart of an exemplary method 200 for manufacturing an integrated circuit (IC) 100 having a Figures 1B - 1H cross-sectional schematic diagram. For illustrative purposes, reference will be made to the manufacturing of an IC asFigures 3 - 21 An example manufacturing process of the integrated circuit (IC) 100 shown is used to illustrate Figure 2 the operation steps shown. Figures 3 - 21 FIG. shows a cross-sectional schematic view of the integrated circuit (IC) 100 along the Figure 1A A-A line at various manufacturing stages according to some embodiments. Figures 5 - 21 FIG. shows according to some embodiments Figure 1B and Figure 4 an enlarged schematic view of the region 103 at various manufacturing stages. Depending on the specific application, the operation steps may be performed in a different order or not performed. It should be noted that the method 200 may not result in a complete integrated circuit (IC) 100. Therefore, it should be understood that additional processes may be provided before, during, and after the method 200, and some other processes may only be briefly described herein. Unless otherwise specified, Figures 1A - 1H and Figures 3 - 21 components with the same reference numerals in

[0115] Please refer to Figure 2 , in operation step 205, source / drain (S / D) regions and gate structures are formed on the fin structure on the substrate. For example, as Figure 3 shown, source / drain (S / D) regions 110A and 110B and gate structures 112A - 112C can be formed on the fin structure 108. The fabrication of the source / drain (S / D) regions 110A and 110B can include forming openings (not shown) in the fin structure 108 and epitaxially growing semiconductor material in the openings. After the formation of the source / drain (S / D) regions 110A and 110B, the formation of the gate structures 112A and 112C can follow, which can then be followed by depositing an etch stop layer (ESL) 118A on the source / drain (S / D) regions 110A and 110B and depositing an interlayer dielectric (ILD) layer 120A on the etch stop layer (ESL) 118A.

[0116] Please refer to Figure 2 , in operation step 210, source / drain (S / D) contact structures are formed on the source / drain (S / D) regions. For example, as Figure 3 shown, source / drain (S / D) contact structures 122A and 122B are formed on the source / drain (S / D) regions 110A and 110B. The fabrication of the source / drain (S / D) contact structures 122A and 122B can include forming openings (not shown) through the interlayer dielectric (ILD) layer 120A and the etch stop layer (ESL) 118A on the source / drain (S / D) regions 110A and 110B and forming the source / drain (S / D) contact structures 122A and 122B in the openings.

[0117] Please refer to Figure 2 In operation step 215, a via structure is formed on one of the source / drain (S / D) regions, and a gate contact structure is formed on one of the gate structures. For example, as shown in Figure 4 , the via structure 124 is formed on the source / drain (S / D) region 110B, and the gate contact structure 126 is formed on the gate structure 112A. In some embodiments, the via structure 124 and the gate contact structure 126 can be formed simultaneously with the same conductive material. The fabrication of the via structure 124 and the gate contact structure 126 can include (i) depositing an etch stop layer (ESL) 118B on the source / drain (S / D) contact structures 122A and 122B and the gate structures 112A - 112C, as shown in Figure 4 , (ii) depositing an interlayer dielectric (ILD) layer 120B on the etch stop layer (ESL) 118B, (iii) forming via openings (not shown) through the interlayer dielectric (ILD) layer 120B and the etch stop layer (ESL) 118B on the source / drain (S / D) contact structure 122A and forming gate contact openings (not shown) on the gate structure 112A, and (iv) forming the via structure 124 in the via opening and forming the gate contact structure 126 in the gate contact opening. In some embodiments, instead of the via structure 124 and the gate contact structure 126, a via structure 140 can be formed in the via opening, and a gate contact structure 142 can be formed in the gate contact opening, as shown in Figure 15 . The interlayer dielectric (ILD) layer 120B, the via structure 124 (or the via structure 140), and the gate contact structure 126 (or the gate contact structure 142) can be substantially coplanar with each other.

[0118] Please refer to Figure 2 In operation step 220, an inner connection structure is formed on the via structure and the gate contact structure.

[0119] In some embodiments, an inner connection structure 102 as shown in Figure 1C can be formed on the via structure 124 and the gate contact structure 126, as referred to in Figures 5 - 10 . Figure 1C The fabrication of the inner connection structure 102 as shown in Figure 5 can include the following sequential operation steps: (i) forming a trench 544 surrounding the via structure 124 and / or the gate contact structure 126 and located at the top edge interfaces 424 and 426, as shown in Figure 6As shown, (iii) deposit an interlayer dielectric (ILD) layer 130 on the film layer 628, (iv) etch portions of the interlayer dielectric (ILD) layer 130 and portions of the etch layer 628 on the via structure 124 and the gate contact structure 126 to form an opening 746, as Figure 7 shown, (v) etch portions of the film layer 628 surrounding the via structure 124 and the gate contact structure 126 to form trenches 744, as Figure 7 shown, (vi) deposit a film layer 834 of a material having a barrier structure 134 in the opening 746 and the trenches 744, as Figure 8 shown, (vii) deposit a film layer 936 of a material having a liner 136 on the film layer 834, as Figure 9 shown, (viii) deposit a film layer 938 of a material having a conductive plug 138 on the film layer 936, as Figure 9 shown and (ix) perform a chemical mechanical polishing (CMP) process on the Figure 9 structure to form the Figure 10 structure, wherein the upper surfaces of the interlayer dielectric (ILD) layer 130, the barrier structure 134, the liner 136, and the conductive plug 138 are substantially coplanar. In some embodiments, trenches 544 may be formed within the via structure 124 or the gate contact structure 126, rather than within both the via structure 124 and the gate contact structure 126.

[0120] In some embodiments, Figure 1D the inner connection structure 102 may be formed on the via structure 124 and the gate contact structure 126, as referenced Figures 11 - 14 above. Figure 1D Fabrication of the inner connection structure 102 may include the following sequential operating steps: (i) perform an etching process on the Figure 4 structure to remove the interlayer dielectric (ILD) layer 120B and expose the top portions 124t of the via structure 124 and the gate contact structure 126, as Figure 11 shown, (ii) deposit an etch stop layer (ESL) 129 on the Figure 11 structure to cover the top portions 124t, as Figure 12 shown, (iii) deposit an interlayer dielectric (ILD) layer 130 on the etch stop layer (ESL) 129, as Figure 12 shown, (iv) etch portions of the interlayer dielectric (ILD) layer 130 on the via structure 124 and the gate contact structure 126 to form an opening 1346, as Figure 13As shown, (v) etch a portion of the etch stop layer (ESL) 129 (not shown) located on and around the via structure 124 and the gate contact structure 126 to expose the top portion 124t. (vi) Deposit a film layer 1335 having a barrier structure 135 into the opening 1346 and covering the top portion 124t, as Figure 13 shown. (vii) Similar to the operation step (vi) described above with reference to Figure 9 deposit a film layer 936 having a liner 136 on the film layer 1335. (viii) Deposit a film layer 938 having a conductive plug 138 on the film layer 1335. And (ix) perform a chemical mechanical polishing (CMP) process on the film layer 1335, the film layer 936, and the film layer 938 to form Figure 14 a structure in which the upper surfaces of the interlayer dielectric (ILD) layer 130, the barrier structure 135, the liner 136, and the conductive plug 138 are substantially coplanar with each other.

[0121] In some embodiments, in addition to performing a chemical mechanical polishing (CMP) process on the Figure 4 structure to remove the interlayer dielectric (ILD) layer 120B and expose the top portion 124t, replacing the etching process performed in operation step (i) described above with reference to Figure 11 the inner connection structure 102 of Figure 1E can be formed by using the process for forming the inner connection structure 102 of Figure 1D described above. In some embodiments, performing a chemical mechanical polishing (CMP) process on the Figure 4 structure can form a curved edge profile 124t3, as Figure 1E shown. In some embodiments, performing a chemical mechanical polishing (CMP) process may include using a polishing liquid having the following components: (i) an abrasive material such as TiO2, SiO2, cerium oxide (CeO2), ZrO2, and / or Al2O3, (ii) an oxidizing agent such as hydrogen peroxide (H2O2), periodic acid (H5IO6), and ferrous nitrite (FeNO3), (iii) a chelating agent such as ammonia (NH3), ethylenediaminetetraacetic acid (EDTA), and amine, (iv) a pH regulator such as potassium hydroxide (KOH), citric acid (C6H8O7), acetic acid, organic acid, and ammonium hydroxide (NH4OH), and (v) a surfactant such as organic acid, ethanol, ethylenediaminetetraacetic acid (EDTA), and acetic acid. In some embodiments, the concentration of the abrasive material in the polishing liquid composition may be less than about 6%, and the concentration of other chemical agents in the polishing liquid composition may be less than about 3%. In some embodiments, the polishing liquid composition may have a pH value of about 4 to 12.

[0122] In some embodiments, Figure 1F an inner connection structure 102 of Figures 15 - 19 may be formed on the via hole structure 140 and the gate contact structure 142, as referred to Figure 1F as described. Figure 16 The fabrication of the inner connection structure 102 of Figure 17 may include the following sequential operation steps: (i) forming trenches 1644 surrounding the via hole structure 140 and the gate contact structure 142 and located at the top edge interfaces 1540 and 1542 (shown in FIG. 15), as Figure 18 shown, (ii) depositing a film layer 1728 of a material having etch stop layers (ESLs) 128A and 128B in the trenches 1644 and on the interlayer dielectric (ILD) layer 120B, as Figure 18 shown, (iii) depositing an interlayer dielectric (ILD) layer 130 on the film layer 1728, (iv) etching portions of the interlayer dielectric (ILD) layer 130 and the film layer 1728 located on the via hole structure 140 and the gate contact structure 142 to form openings 746, as Figure 9 shown, (v) etching portions of the film layer 1728 surrounding the via hole structure 140 and the gate contact structure 142 to form trenches 744, as Figure 9 shown, (v) similar to operation step (v) described above with reference to FIG. 8, depositing a film layer 834 of a material having a barrier structure 134 in the openings 746 and the trenches 744, (vi) similar to Figure 19 operation step (vi) described above with reference to

[0123] In some embodiments, Figure 1G the fabrication of the inner connection structure 102 of Figure 15 may include: (i) performing an etching process on the Figure 20 structure of Figure 20 to remove the interlayer dielectric (ILD) layer 120B and expose the top portion 140t, as Figure 1D shown and (ii) performing operation steps (ii)-(ix) of the process for forming the inner connection structure 102 of

[0124] In some embodiments, Figure 1HFabrication of the internal connection structure 102 may include: (i) performing a chemical mechanical polishing (CMP) process on the structure of FIG. 15 to remove the interlayer dielectric (ILD) layer 120B and expose the top portion 140t, as Figure 21 shown and (ii) performing the operation steps (ii)-(ix) of the process of forming the Figure 21 internal connection structure 102 on the Figure 1D structure.

[0125] The present disclosure provides an exemplary integrated circuit (IC) (e.g., integrated circuit (IC) 100) having barrier structures (e.g., barrier structures 134 and 135) in internal connections (e.g., internal connections 132 and 133) to reduce the resistance of the internal connections and minimize or prevent metal from diffusing from the liner (e.g., liner 136) and / or plug (e.g., conductive plug 138) in the internal connections to the underlying contact structure (e.g., gate contact structure 126) of a semiconductor device (e.g., gate-all-around field effect transistor (GAA FET) 102 or fin field effect transistor (finFET) 102). Additionally, the present disclosure provides an exemplary method (e.g., method 200) of forming an integrated circuit (IC). In some embodiments, the internal connections may be disposed on the contact structures of the semiconductor device and the interlayer dielectric (ILD) layer surrounding the contact structures. The internal connections may include a barrier structure (e.g., barrier structure 134) having an internal connection portion (e.g., internal connection portion 134A) and a contact portion (e.g., contact portion 134B). The internal connection portion may surround the internal connection liner and / or plug of the internal connection, and may have a thin profile thickness of about 0.5 nm to 3 nm to reduce the resistance of the internal connection.

[0126] Due to the thin profile of the internal connection portion, the bottom portion thickness of the internal connection portion may have non-uniformity. The thickness non-uniformity may occur at the underlying interface between the contact structure and the interlayer dielectric (ILD) layer. This thickness non-uniformity may cause metal to diffuse from the internal connection liner and / or plug through the top edge and / or sidewall of the contact structure to the contact structure. The presence of the contact portion can prevent or minimize metal diffusion to the contact structure and improve the integrated circuit (IC) performance. The contact portion may extend from the lower surface (e.g., lower surface 134s) of the internal connection portion and surround the top portion of the contact structure, thus providing a metal diffusion barrier layer at the top edge and / or sidewall of the contact structure. In some embodiments, the contact portion may have a thickness of about 0.5 nm to 2 nm and may extend a distance that is about 10% to 50% of the thickness of the interlayer dielectric (ILD) layer.

[0127] In some embodiments, a method of forming a semiconductor structure includes: depositing a first dielectric layer on a semiconductor device; forming a conductive structure within the first dielectric layer; removing a portion of the first dielectric layer to expose a sidewall of the conductive structure; forming a barrier structure surrounding the sidewall of the conductive structure; depositing a conductive layer on the barrier structure; and performing a polishing process on the barrier structure and the conductive layer.

[0128] In some embodiments, removing the portion of the first dielectric layer includes forming a trench surrounding the sidewall of the conductive structure. In some embodiments, removing the portion of the first dielectric layer includes etching the portion of the first dielectric layer at an interface between the first dielectric layer and the conductive structure. In some embodiments, removing the portion of the first dielectric layer includes performing a chemical mechanical polishing process on the first dielectric layer. In some embodiments, the method further includes depositing a second dielectric layer on an upper surface of the first dielectric layer and on the sidewalls of the conductive structure before forming the barrier structure. In some embodiments, the method further includes depositing an etch stop layer on an upper surface of the first dielectric layer and on the sidewalls of the conductive structure; and etching a portion of the etch stop layer in contact with the sidewalls of the conductive structure before forming the barrier structure. In some embodiments, forming the barrier structure includes: forming a first portion on an upper surface of the conductive structure; and forming a second portion surrounding the sidewall of the conductive structure. In some embodiments, forming the barrier structure includes: forming a first portion on an upper surface of the conductive structure; and forming a second portion extending from a lower surface of the first portion to an upper surface of the first dielectric layer and surrounding the sidewall of the conductive structure. In some embodiments, forming the barrier structure includes: forming a first portion on an upper surface of the conductive structure and on the first dielectric layer; and forming a second portion extending from a lower surface of the first portion into the first dielectric layer and surrounding the sidewall of the conductive structure. In some embodiments, forming the barrier structure includes forming the barrier structure between a top edge of the first dielectric layer and the conductive structure.

[0129] In some embodiments, a method of forming a semiconductor structure includes: forming a semiconductor device and forming an interconnect structure on the semiconductor device. Forming the semiconductor device includes: forming a gate structure on a substrate; depositing a dielectric layer on the gate structure; and forming a contact structure on the gate structure and within the dielectric layer. Forming the interconnect structure includes: forming a barrier structure surrounding a top portion of the contact structure; depositing a liner on the barrier structure; depositing a conductive layer on the liner; and performing a polishing process on the barrier structure, the liner, and the conductive layer.

[0130] In some embodiments, forming the barrier structure includes forming a trench surrounding a top portion of the contact structure. In some embodiments, forming the barrier structure includes: forming a first portion of the barrier structure on an upper surface of a dielectric layer; and forming a second portion of the barrier structure extending a distance below the upper surface of the dielectric layer, which is about 10% to 50% of the height of the dielectric layer. In some embodiments, forming the barrier structure includes forming a barrier structure at an interface between the dielectric layer and the conductive structure. In some embodiments, the method further includes: depositing an etch stop layer on the contact structure before forming the barrier structure. In some embodiments, the method further includes: forming a trench surrounding a top portion of the contact structure; and depositing an etch stop layer in the trench before forming the barrier structure.

[0131] In some embodiments, a semiconductor structure includes: a first dielectric layer disposed on a semiconductor device; a conductive structure disposed within the first dielectric layer; a barrier structure including a top portion and a bottom portion; a conductive liner disposed on the barrier structure; and a conductive plug disposed on the conductive liner. The top portion is disposed on the first dielectric layer, and the bottom portion extends into the first dielectric layer and is disposed between the conductive structure and the first dielectric layer.

[0132] In some embodiments, the semiconductor structure further includes: an etch stop layer disposed between the conductive structure and the first dielectric layer, wherein the bottom portion is disposed on and in contact with the etch stop layer. In some embodiments, the semiconductor structure further includes: a second dielectric layer disposed on the first dielectric layer, wherein the top portion is disposed within the second dielectric layer. In some embodiments, the bottom portion extends into the first dielectric layer a distance that is about 10% to 50% of the height of the first dielectric layer. In some embodiments, the bottom portion surrounds a sidewall of the conductive structure. In some embodiments, the semiconductor structure further includes: an etch stop layer disposed on the first dielectric layer; and a second dielectric layer disposed on the etch stop layer. In some embodiments, an upper surface of the second dielectric layer and the barrier structure are substantially coplanar with each other. In some embodiments, an upper surface of the conductive liner and the conductive plug are substantially coplanar with each other. In some embodiments, the bottom portion extends into the first dielectric layer a distance within a range of 0.5 nm to 10 nm. In some embodiments, an upper surface of the first dielectric layer and the conductive structure are substantially coplanar with each other.

[0133] The characteristic components of several embodiments of the present utility model are outlined above, enabling those with ordinary knowledge in the relevant technical field to more easily understand the form of the present disclosure. Any person with ordinary knowledge in the relevant technical field should understand that the present disclosure can be easily used as a basis for the modification or design of other processes or structures to achieve the same purposes as the embodiments described herein and / or obtain the same advantages. Any person with ordinary knowledge in the relevant technical field can also understand that equivalent structures to the above do not depart from the spirit and protection scope of the present disclosure, and can be modified, substituted, and refined without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A first dielectric layer disposed on a semiconductor device; A conductive structure disposed within the first dielectric layer; A barrier structure including a top portion and a bottom portion, wherein: The top portion is disposed on the first dielectric layer; and The bottom portion extends into the first dielectric layer and is disposed between the conductive structure and the first dielectric layer; A conductive liner disposed on the barrier structure; and A conductive plug disposed on the conductive liner.

2. The semiconductor structure according to claim 1, wherein Further comprising: An etch stop layer disposed between the conductive structure and the first dielectric layer, wherein the bottom portion is disposed on and in contact with the etch stop layer.

3. The semiconductor structure according to claim 1 or 2, characterized in that, Further comprising: A second dielectric layer disposed on the first dielectric layer, wherein the top portion is disposed within the second dielectric layer.

4. The semiconductor structure according to claim 1 or 2, characterized in that, Wherein the bottom portion extends into the first dielectric layer to a distance that is 10% to 50% of the height of the first dielectric layer.

5. The semiconductor structure according to claim 4, wherein Wherein the bottom portion surrounds the sidewall of the conductive structure.

6. The semiconductor structure according to claim 1 or 2, characterized in that, Further comprising: An etch stop layer disposed on the first dielectric layer; And A second dielectric layer disposed on the etch stop layer.

7. The semiconductor structure according to claim 6, wherein Wherein the upper surface of the second dielectric layer and the barrier structure are substantially coplanar with each other.

8. The semiconductor structure according to claim 6, wherein, Wherein the upper surfaces of the conductive liner and the conductive plug are substantially coplanar with each other.

9. The semiconductor structure according to claim 1 or 2, characterized in that, Wherein the bottom portion extends into the first dielectric layer to a distance in the range of 0.5 nm to 10 nm.

10. The semiconductor structure according to claim 1 or 2, wherein Wherein the upper surfaces of the first dielectric layer and the conductive structure are substantially coplanar with each other.

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