Circuit control chip packaging structure
By enabling the interconnection of fan-out structure and upper flip structure on formal chips, the problem of inability to use bond wire connection is solved, and more chip packaging options are provided to meet the diversified market needs.
Patent Information
- Application Number
- CN202422150192.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-02
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-09-02
AI Technical Summary
The existing chip packaging structure cannot achieve signal control or power management without using bonded wire connections, and cannot meet the diversified market needs.
The fan-out structure is realized based on the formal chip, and the upper layer is stacked inverted structure. The chip is interconnected with the substrate and electronic components through conductive columns and rewiring layers, and the connection is carried out using a hot ball.
It provides a double-sided fan-out stacked packaging structure, which realizes the signal control of the chip to electronic components, and the process is relatively easy to meet the diversified market needs.
Smart Images
Figure CN223079125U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor packaging, and more particularly to a packaging structure for a circuit control chip. Background Art
[0002] In the existing packaging structures of signal control or power management chips, the chips are generally of the flip-chip type, and the controlled objects are generally interconnected with the chip circuits through bonding wires, and their structures are relatively single. With the change of market demands, for example, in the case where the controlled objects cannot be connected by bonding wires, the existing packaging structures cannot be realized.
[0003] Therefore, a new packaging structure is needed, which can utilize the existing process technologies that can be achieved to realize the signal control of the chip over electronic devices even in the case where bonding wires cannot be used, providing more choices for the market. Summary of the Utility Model
[0004] In order to solve the above problems, the utility model provides a packaging structure for a circuit control chip including a power supply substrate, a control chip, and a controlled electronic component, directly realizing a fan-out structure on the basis of a face-up chip, and stacking flip-chip structured controlled electronic components on the upper layer, providing more choices for the market.
[0005] According to one aspect of the utility model, a packaging structure for a circuit control chip is provided, which includes a chip, the chip is externally encapsulated with a first encapsulant, a first redistribution layer and a second redistribution layer are respectively provided on the front and back sides of the chip, conductive pillars penetrating through the first encapsulant around the chip and interconnected with the first redistribution layer and the second redistribution layer at both ends are provided, solder balls one are implanted on the first redistribution layer on the front side of the chip, the chip implanted with the solder balls one is mounted on a substrate to form an interconnection, solder balls two are implanted on the back side of the substrate, and an electronic component is mounted on the second redistribution layer on the back side of the chip.
[0006] In some embodiments, the conductive pillars are copper pillars formed by electroplating copper filling or conductive adhesive pillars formed by injecting a guiding adhesive material.
[0007] In some embodiments, a filler layer is formed between the first redistribution layer and the substrate through underfilling.
[0008] In some embodiments, a second encapsulant is formed by integrally encapsulating the first redistribution layer, the first encapsulant, the second redistribution layer, and the electronic component on the substrate.
[0009] In some embodiments, the back side of the chip is exposed by thinning the first encapsulant to make the back side of the chip flush with the surface of the first encapsulant.
[0010] In some embodiments, the diameter of the solder balls one is 120 - 250 μm, and the diameter of the solder balls two is 300 - 600 μm.
[0011] In some embodiments, the line width and line pitch of the first and second redistribution layers are 5 - 20 μm, the number of circuit layers is 3 - 6, and the number of internal circuit layers of the substrate is 2 - 4.
[0012] In some embodiments, the electronic component is an optical sensor device or a signal unit for controlling a mechanical structure.
[0013] Compared with the prior art, the beneficial effects of the present utility model are as follows: The circuit control chip packaging structure provided by the present utility model is a double-sided fan-out stacked packaging structure. First, a chip for signal control or power management is encapsulated, then a double-sided fan-out RDL (ReDistribution Layer) circuit is fabricated, and then the front RDL side thereof is mounted on a power supply substrate through solder balls, and an electronic component for signal management is mounted on the back RDL, so as to realize signal control of the chip over the electronic component. The manufacturing process and technology of this circuit control chip packaging structure are relatively easy to implement based on the prior art, providing more choices for the market and meeting the growing product requirements. BRIEF DESCRIPTION OF THE DRAWINGS
[0014] Figure 1 is a schematic structural diagram of an embodiment of a circuit control chip packaging structure of the present utility model;
[0015] Figure 2 is a schematic packaging process diagram of chip encapsulation and formation of conductive pillars;
[0016] Figure 3 is a schematic packaging process diagram of forming a fan-out structure on both sides of the chip and mounting it on a substrate;
[0017] Figure 4 is a schematic subsequent packaging process diagram of mounting electronic components. DETAILED DESCRIPTION OF THE EMBODIMENTS
[0018] The present utility model will be further described below in conjunction with the detailed embodiments.
[0019] Such as Figure 1As shown in the figure, a circuit control chip packaging structure according to an embodiment of the present utility model includes a chip 1, which is a chip for signal control or power management. There is a circuit of bonding pads 11 on the front of the chip 1. The chip 1 is externally encapsulated with a first encapsulation body 2. The front and back of the chip 1 are respectively provided with a first redistribution layer 4 and a second redistribution layer 5. A plurality of conductive pillars 3 penetrate through the first encapsulation body 2 around the chip 1. The two ends of the conductive pillars 3 are respectively connected to the first redistribution layer 4 and the second redistribution layer 5 to achieve interconnection. Solder balls 41 are planted on the first redistribution layer 4 on the front of the chip 1. The chip 1 with the solder balls 41 planted is mounted on a substrate 6 to form an interconnection. Solder balls 61 are planted on the back of the substrate 6. An electronic component 8 is mounted on the second redistribution layer 5 on the back of the chip 1. The main functions of the substrate 6 are to supply power to the chip, ground it, and achieve partial signal intercommunication. The electronic component 8 can be an optical sensor, a signal unit for controlling a mechanical structure, etc.
[0020] In practical applications, after the chip 1 is encapsulated, the back of the chip 1 is exposed by thinning the first encapsulation body 2, making the back of the chip 1 flush with the surface of the first encapsulation body 2.
[0021] Holes are drilled in the first encapsulation body 2 around the chip 1. The drilling depth penetrates the first encapsulation body 2. The conductive pillars 3 are located in the holes. The forming method of the conductive pillars 3 can be copper pillars formed by electroplating copper in the holes, or conductive adhesive pillars formed by injecting conductive adhesive materials into the holes.
[0022] To improve the reliability of direct soldering, a bottom filling can be performed between the first redistribution layer 4 and the substrate 6 according to requirements to form a filling layer 7.
[0023] According to the requirements of the actual use scenario, the first redistribution layer 4, the first encapsulation body 2, the second redistribution layer 5, and the electronic component 8 on the substrate 6 can be integrally encapsulated to form a second encapsulation body 9.
[0024] Combined Figures 2 to 4 , the packaging process of the circuit control chip packaging structure described in the present application is specifically described as follows:
[0025] Step 1: As shown in 1A, one or more chips 1 are mounted on a temporary metal carrier 100 in the form of FACE DOWN (circuit layer facing down) using a temporary bonding film 101. Figure 2 As shown in 1B, the mounted chips 1 are encapsulated with epoxy resin to form a first encapsulation body 2.
[0026] Step 2: Figure 2 The encapsulated chips 1 and the first encapsulation body 2 are separated from the temporary bonding film 101 through a debonding process and ground and thinned. The thickness after thinning is determined according to the design requirements, and the back of the chip 1 can be exposed, as
[0027] Step 3:Figure 2 As shown in 1C.
[0028] Step Four: As Figure 2 shown in 1D, laser drilling is performed on the first encapsulation body 2 around the chip 1 to form holes 30 with a drilling diameter of 100 - 200 μm and a drilling depth that penetrates the first encapsulation body 2.
[0029] Step Five: As Figure 2 shown in 1E, electroplating copper filling is performed on the drilled chip 1 to form copper pillars; conductive adhesive materials can also be injected into the laser holes to form conductive adhesive pillars. That is, conductive pillars 3 are formed to conduct the front and back sides of the first encapsulation body 2.
[0030] Step Six: A first redistribution layer 4 (RDL, ReDistribution Layer) is fabricated on the front of the first encapsulation body 2. The RDL line width and line pitch are 5 - 20 μm, and the circuit generally has 3 - 6 layers. Through the RDL, the circuit of the front solder pads 11 of the chip 1 is fanned out to the surfaces of the chip 1 and the first encapsulation body 2 and interconnected with the conductive pillars 3, as Figure 3 shown in 1F.
[0031] Step Seven: A second redistribution layer 5 (RDL, ReDistribution Layer) is fabricated on the back of the first encapsulation body 2. The RDL line width and line pitch are 5 - 20 μm, and the circuit generally has 3 - 6 layers. It is connected to the conductive pillars 3 through the RDL to achieve interconnection with the chip 1, as Figure 3 shown in 1G.
[0032] Step Eight: As Figure 3 shown in 1H, ball mounting is performed on the RDL on the front, that is, the first redistribution layer 4, to form the first solder balls 41 with a diameter of generally 120 - 250 μm.
[0033] Step Nine: As Figure 3 shown in 1I, the fan - out structure with completed RDL and ball mounting is cut into single chips and then mounted on the substrate 6, and underfilling is performed between the RDL (the first redistribution layer 4) and the substrate 6 according to requirements, that is, a filling material layer 7 is formed to improve the reliability of direct soldering between the two.
[0034] The main functions of the substrate 6 are to supply power to the chip 1, ground it, and enable partial signal intercommunication. The substrate 6 internally contains 2 - 4 layers of metal circuits.
[0035] Step Ten: An electronic component 8 is mounted on the side of the back RDL (the second redistribution layer 5) away from the chip 1, as Figure 4 shown in 1J. The electronic component 8 can be an optoelectronic sensor device or a signal unit for controlling a mechanical structure, etc.
[0036] Step Eleven: According to the requirements of the actual usage scenario, the fan-out structure and the electronic component 8 can be integrally encapsulated, that is, the redistribution layer one 4, the encapsulant one 2, the redistribution layer two 5 and the electronic component 8 on the substrate 6 are integrally encapsulated to form the encapsulant two 9, as Figure 4 shown in Figure 1K.
[0037] Step Twelve: As shown in Figure 4 Figure 1L, finally, solder balls two 61 are formed by ball planting on the back of the substrate 6 for connection to an external circuit. The diameter of the solder balls two 61 is generally 300 - 600 um.
[0038] The circuit control chip packaging structure provided by the present utility model is a double-sided fan-out stacked packaging structure. During packaging, first, the chips for signal control or power management are encapsulated, then the double-sided fan-out RDL (ReDistribution Layer) lines are fabricated, and then the front RDL side is mounted on the power supply substrate 6 through solder balls, and the signal management type electronic components 8 are mounted on the back RDL, thereby realizing the signal control of the chip 1 over the electronic components 8.
[0039] The process of this circuit control chip packaging structure directly realizes the fan-out structure based on the flip-chip 1, and its manufacturing process and technology are relatively easy. The controlled electronic components 8 in the upper stacked flip-chip structure provide more choices for the market.
[0040] The above are only some embodiments of the present utility model. It should be noted that for those of ordinary skill in the art, without departing from the creative concept of the present utility model, other deformations and improvements can be made, and these all belong to the protection scope of the present utility model.
Claims
1. A circuit control chip packaging structure, including a chip (1), the chip (1) is externally encapsulated with a first encapsulation body (2), characterized in that, On the front and back sides of the chip (1), a first redistribution layer (4) and a second redistribution layer (5) are respectively provided. A conductive pillar (3) whose two ends are respectively interconnected with the first redistribution layer (4) and the second redistribution layer (5) penetrates through the first encapsulant (2) around the chip (1). Solder balls one (41) are planted on the first redistribution layer (4) on the front side of the chip (1). The chip (1) with the solder balls one (41) planted thereon is mounted on the substrate (6) to form an interconnection. Solder balls two (61) are planted on the back side of the substrate (6). An electronic component (8) is mounted on the second redistribution layer (5) on the back side of the chip (1).
2. The circuit control chip packaging structure according to claim 1, characterized in that, The conductive pillar (3) is a copper pillar formed by electroplating copper filling or a conductive adhesive pillar formed by injecting a guiding adhesive material.
3. The circuit control chip packaging structure according to claim 1, characterized in that, A filler layer (7) is formed between the first redistribution layer (4) and the substrate (6) by underfilling.
4. The circuit control chip packaging structure according to claim 1, characterized in that A second encapsulant (9) is formed by overall encapsulation of the first redistribution layer (4), the first encapsulant (2), the second redistribution layer (5) and the electronic component (8) on the substrate (6).
5. The circuit control chip packaging structure according to claim 1, characterized in that The back side of the chip (1) is exposed by thinning the first encapsulant (2) so that the back side of the chip (1) is flush with the surface of the first encapsulant (2).
6. The circuit control chip packaging structure according to claim 1, characterized in that The diameter of the solder balls one (41) is 120 - 250 μm, and the diameter of the solder balls two (61) is 300 - 600 μm.
7. The circuit control chip package structure according to claim 1, wherein The line width and line pitch of the first redistribution layer (4) and the second redistribution layer (5) are 5 - 20 μm, and the circuit is 3 - 6 layers. The internal circuit of the substrate (6) is 2 - 4 layers.
8. The circuit control chip packaging structure according to claim 1, characterized in that, The electronic component (8) is an optical sensor device or a signal unit for controlling a mechanical structure.