Frequency hopping zero intermediate frequency receiver circuit

Abstract

The utility model provides a frequency hopping zero intermediate frequency receiver circuit, which is characterized in that a radio frequency amplification circuit is connected with the input end of a power distribution circuit through a controllable attenuation circuit, the output end of the power distribution circuit is respectively connected with the input ends of two orthogonal demodulation circuits, the output end of a first PLL circuit is connected with the local oscillation end of a first orthogonal demodulation circuit, and the output end of a second PLL circuit is connected with the local oscillation end of a second orthogonal demodulation circuit. The output end of the second PLL circuit is connected with the local oscillation end of the second orthogonal demodulation circuit; two outputs of the first orthogonal demodulation circuit are respectively connected with the input end of the first baseband pre-amplification circuit, and two outputs of the second orthogonal demodulation circuit are respectively connected with the input end of the second baseband pre-amplification circuit; the two output ends of each baseband pre-amplification circuit are respectively connected with the input end of the electronic switch circuit, and the output end of the electronic switch circuit is connected with the final-stage amplification circuit through the baseband filter circuit. The PLL load is not changed at the switching moment of the electronic switch, the influence of PLL load traction can be obviously relieved, and the frequency switching time is reduced by more than 80% compared with that of a traditional ping-pong phase-locked loop.

Description

Technical Field

[0001] The utility model relates to the field of communications, and in particular to a frequency-hopping zero-IF receiver circuit. Background Art

[0002] In the field of radio frequency-hopping communication, the frequency-hopping speed index of the receiver is extremely crucial. In frequency-hopping communication, the communication frequency points are not fixed but change rapidly. The tuning frequency of the receiver for processing frequency-hopping signals also needs to perform frequency-hopping operation. The main application scenario of radio frequency-hopping communication is anti-jamming communication, and the frequency-hopping speed is one of the key factors for its anti-jamming ability.

[0003] The traditional method for improving the frequency-hopping speed of a zero-IF receiver is to internally install a "ping-pong phase-locked loop" to provide a frequency-converted local oscillator. The "ping-pong phase-locked loop" uses multiple phase-locked loops (PLLs) to work alternately, and achieves fast frequency hopping through the switching of a radio frequency electronic switch. That is, one of the multiple PLLs works at the current target frequency point, and the radio frequency electronic switch switches this PLL to the output state, while the remaining PLLs are in the non-output state and prepare for the next target frequency point. After preparation, they wait to be switched to the output state. In an ideal state, the above method can make the frequency conversion time only the switching time of the electronic switch. However, at the moment when the electronic switch switches, the voltage-controlled oscillator (VCO), which is an essential component of the PLL, will experience load pulling due to the change in load, causing the already locked PLL to unlock and relock, greatly delaying the frequency conversion time. Therefore, designing a circuit that can alleviate the load pulling of the PLL is crucial for increasing the frequency-hopping speed. Summary of the Invention

[0004] In order to solve the problems existing in the background art, the utility model proposes a frequency-hopping zero-IF receiver circuit.

[0005] A frequency-hopping zero-IF receiver circuit, the input end of a radio frequency amplification circuit receives a signal to be processed, the output end of the radio frequency amplification circuit is connected to the input end of a power distribution circuit through a controllable attenuation circuit, the output ends of the power distribution circuit are respectively connected to the input ends of a first quadrature demodulation circuit and a second quadrature demodulation circuit, the output end of a first PLL circuit is connected to the local oscillator end of the first quadrature demodulation circuit, and the output end of a second PLL circuit is connected to the local oscillator end of the second quadrature demodulation circuit; the I / Q two-way outputs of the first quadrature demodulation circuit are respectively connected to the input ends of a first baseband pre-amplification circuit, and the I / Q two-way outputs of the second quadrature demodulation circuit are respectively connected to the input ends of a second baseband pre-amplification circuit; the two output ends of the first baseband pre-amplification circuit and the two output ends of the second baseband pre-amplification circuit are respectively connected to the input ends of an electronic switch circuit, the output end of the electronic switch circuit is connected to the input end of a final amplification circuit through a baseband filter circuit, and the output end of the final amplification circuit outputs the processed signal.

[0006] Based on the above, the RF amplification circuit includes a cascaded primary RF amplifier and a secondary RF amplifier. The input end of the primary RF amplifier receives the signal to be processed, and the output end of the secondary RF amplifier is connected to the input end of the controllable attenuation circuit.

[0007] Based on the above, the first quadrature demodulation circuit and the second quadrature demodulation circuit are respectively quadrature demodulators, with the model number ADL5380ACPZ.

[0008] Based on the above, the first PLL circuit and the second PLL circuit are respectively PLL chips, with the model number HMC835LP6GE.

[0009] Based on the above, the baseband filtering circuit includes a cascaded programmable baseband filter and an LC filter. The model number of the programmable baseband filter is LTC6603IUF.

[0010] The present utility model has substantial features and progress compared with the prior art. Specifically, the present utility model respectively configures two parallel quadrature demodulation circuits, PLL circuits, and baseband pre-amplification circuits, and selects the output channel through the electronic switch circuit, that is, one path operating at the current target frequency point is used for output, and the other path prepares for the next target frequency point. After preparation, it waits to switch to the output state and works alternately. During the moment of electronic switch switching, the PLL load does not change, which can significantly alleviate the influence of PLL load pulling. The frequency switching time is reduced by more than 80% compared with the traditional "ping-pong phase-locked loop". Description of the Drawings

[0011] Figure 1 is the structural schematic block diagram of the present utility model.

[0012] Figure 2 is the circuit principle schematic diagram of the RF amplification circuit of the present utility model.

[0013] Figure 3 is the circuit principle schematic diagram of the quadrature demodulation circuit of the present utility model.

[0014] Figure 4 is the circuit principle schematic diagram of the PLL circuit of the present utility model.

[0015] Figure 5 is the circuit principle schematic diagram of the baseband filtering circuit of the present utility model. Detailed Embodiments

[0016] The following will clearly and completely describe the technical solutions in the embodiments of the present utility model in conjunction with the accompanying drawings in the embodiments of the present utility model. Obviously, the described embodiments are only a part of the embodiments of the present utility model, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present utility model without creative efforts shall fall within the protection scope of the present utility model.

[0017] As Figure 1 shown, a frequency-hopping zero-IF receiver circuit includes a radio frequency amplification circuit, a controllable attenuation circuit, a power distribution circuit, a first quadrature demodulation circuit, a second quadrature demodulation circuit, a first PLL circuit, a second PLL circuit, a first baseband preamplification circuit, a second baseband preamplification circuit, an electronic switch circuit, a baseband filter circuit, and a final amplification circuit. The input end of the radio frequency amplification circuit receives a signal to be processed. The output end of the radio frequency amplification circuit is connected to the input end of the power distribution circuit through the controllable attenuation circuit. The output end of the power distribution circuit is respectively connected to the input ends of the first quadrature demodulation circuit and the second quadrature demodulation circuit. The output end of the first PLL circuit is connected to the local oscillator end of the first quadrature demodulation circuit. The output end of the second PLL circuit is connected to the local oscillator end of the second quadrature demodulation circuit. The I / Q two-way outputs of the first quadrature demodulation circuit are respectively connected to the input ends of the first baseband preamplification circuit. The I / Q two-way outputs of the second quadrature demodulation circuit are respectively connected to the input ends of the second baseband preamplification circuit. The two output ends of the first baseband preamplification circuit and the two output ends of the second baseband preamplification circuit are respectively connected to the input end of the electronic switch circuit. The output end of the electronic switch circuit is connected to the input end of the final amplification circuit through the baseband filter circuit. The output end of the final amplification circuit outputs the processed signal.

[0018] The input end of the radio frequency amplification circuit is connected to an antenna. The signal received by the antenna is amplified and variably attenuated and then divided into two paths, which respectively enter independent quadrature demodulation circuits to demodulate independent I / Q signals. After being preamplified by independent baseband preamplification circuits, the output path is selected by an electronic switch, and then output after baseband filtering and final amplification. Two independent PLL (phase-locked loop) circuits provide local oscillator signals for quadrature demodulation.

[0019] In this embodiment, as Figure 2 shown, the radio frequency amplification circuit includes two cascaded first-stage amplifiers N1 and second-stage amplifiers N2. The models of the two-stage amplifiers are both MNA-7A+. The 2nd pin of the first-stage amplifier N1 is connected to the antenna (IN1 end) through a capacitor C2 to receive the signal to be processed. The 5th pin of the second-stage amplifier N2 is connected to the controllable attenuation circuit through a capacitor C68. The two-stage amplifiers are cascaded to obtain the necessary gain. As Figure 3As shown, the controllable attenuation circuit includes an attenuator N3, model number HMC624LP4E. The 6th pin of the attenuator N3 is connected to the RF amplification circuit. After performing controllable attenuation on the received signal, it is connected to the power distribution circuit through the 13th pin. Among them, the 2nd, 3rd, and 4th pins are connected to the external microprocessor for controlling the attenuation amount. As Figure 4 As shown, the power distribution circuit includes a power divider N4, model number SIPS123SP4. The 3rd pin of the power divider N4 is connected to the controllable attenuation circuit. After dividing the signal into two paths, they respectively enter two independent quadrature demodulation circuits. As Figure 5 As shown, the quadrature demodulation circuit is a quadrature demodulator N18, model number ADL5380ACPZ. The IN2 end of the quadrature demodulator N18 receives the RF signal output by the power distribution circuit (OUT41 end / OUT42 end), the IN3 end receives the local oscillator signal of the PLL circuit, the 3rd pin IP end and the 4th pin IN end output the I-channel baseband signal, and the 15th pin QN end and the 16th pin QP end output the Q-channel baseband signal. Figure 5 Only one quadrature demodulator is shown in the figure. In practice, two quadrature demodulators are respectively configured. As Figure 6 As shown, the first PLL circuit and the second PLL circuit are respectively PLL chips N17, model number HMC835LP6GE. The 26th pin LO1_N end is used to connect to the IN3 end of the quadrature demodulator N18, that is, to provide the local oscillator signal for the quadrature demodulator N18. Among them, the 31st, 32nd, 33rd pins, etc. are connected to the external microprocessor for controlling the output frequency point. Figure 6 Only one PLL chip is shown in the figure. In practice, two PLL chips are respectively configured. The I / Q signals output by each quadrature demodulator N18 are respectively amplified by a baseband pre-amplification circuit and then output to the electronic switch circuit. The electronic switch circuit is a low-frequency electronic switch circuit. After the electronic switch circuit selects the output path, it is sent to the baseband filter circuit for filtering processing. As Figure 7 As shown, the baseband pre-amplification circuit includes a differential operational amplifier N7, model number AD8138ARMZ. The 1st pin IN- and the 8th pin IN+ of the differential operational amplifier N7 are the baseband signal input pins, and the 5th pin OUT- and the 8th pin OUT+ of the differential operational amplifier N7 are the baseband signal output pins, which form a differential amplification circuit with resistors R71, R72, R73, and R74. The 1st pin IN- and the 8th pin IN+ of the differential operational amplifier N7 are the baseband signal input pins for receiving the I-channel baseband signal or the Q-channel baseband signal output by the quadrature demodulation circuit, and the 5th pin OUT- and the 8th pin OUT+ of the differential operational amplifier N7 are the baseband signal output pins for connecting to the electronic switch circuit. Figure 7 Only one baseband pre-amplification circuit is shown in the figure. In practice, 4 paths are respectively configured, that is, the first baseband pre-amplification circuit and the second baseband pre-amplification circuit are respectively configured with 2 differential operational amplifiers N7. As Figure 8As shown, the electronic switch circuit includes switch N8, model MAX4564EKA-T, and the 1st pin NC and 4th pin NO of switch N8 are selection input pins, which are respectively used to connect the output terminals OUT- and OTU+ of the baseband pre-amplifier circuit; the 8th pin COM is the output pin, which is used to connect the baseband filter circuit; the 3rd pin SW is connected to the external microprocessor for selecting the output path control. The electronic switch circuit is a low-frequency electronic switch circuit. After the electronic switch circuit selects the output path, it is transmitted to the baseband filter circuit for filtering. Figure 8 Only one electronic switch circuit is shown in the figure, but there are actually four. Figure 9 As shown, the baseband filter circuit includes a programmable baseband filter N9 and an LC filter. The model of the programmable baseband filter N9 is LTC6603IUF. The 23-pin INA- is used in conjunction with the LC filter composed of inductors L38, L39, capacitors C268, C277, and C278 to form a baseband filter circuit. Similarly, the 24-pin INA+, the 7-pin INB+, and the 8-pin INB- are used with the corresponding inductors and capacitors to form a baseband filter, and a total of 4 channels are configured. IN_I+ and IN_I-, IN_Q+ and IN_Q- of the programmable baseband filter N9 are respectively used to receive I-channel or Q-channel signals, that is, the output signal of the output pin 8 of the 4-channel electronic switch circuit, and OUT_I+ and OUT_I-, OUT_Q+ and OUT_Q- are respectively used to output the filtered I-channel or Q-channel signals. Among them, the 6th, 9th, and 10th pins of the programmable baseband filter N9 and the DA chip U1, model LTC2630, are connected to an external microprocessor to control the filter gain and bandwidth. The filtered I-channel or Q-channel signal is amplified by the final amplifier circuit and then output to the target device.

[0020] In this embodiment, when frequency hopping is in operation, an external microcontroller configures the PLL to be linked with the electronic switch to realize the selection of the output channel. When the first PLL circuit operates at the current target frequency, the electronic switch is configured to make the first channel in the output state and the second channel in the cut-off state. At this time, the receiver outputs the signal of the first channel, that is, the signal of the current target frequency; at the same time, the second PLL circuit uses this period of time to prepare for the next target frequency. When the second PLL circuit is ready, it waits for the frequency switching moment to come, and configures the electronic switch to make the second channel in the output state and the first channel in the cut-off state. The first PLL circuit in the cut-off state prepares the next target frequency again, and so on. At the moment of switching the electronic switch, the PLL load does not change, which can significantly alleviate the impact of PLL load pulling and reduce the frequency switching time; at the same time, the use of a low-frequency electronic switch can significantly improve the isolation compared to the "ping-pong phase-locked loop" that must use a high-frequency electronic switch.

[0021] For those skilled in the art, it is obvious that the present utility model is not limited to the details of the above exemplary embodiments, and the present utility model can be implemented in other specific forms without departing from the spirit or basic characteristics of the present utility model. Therefore, from any point of view, the embodiments should be regarded as exemplary and non-limiting. The scope of the present utility model is defined by the appended claims rather than the above description. Therefore, all changes falling within the meaning and scope of the equivalent elements of the claims are intended to be embraced within the present utility model. Any reference signs in the claims should not be construed as limiting the claims involved.

Claims

1. A frequency hopping zero-IF receiver circuit, characterized in that: The input end of the radio frequency amplification circuit receives the signal to be processed. The output end of the radio frequency amplification circuit is connected to the input end of the power distribution circuit through a controllable attenuation circuit. The output ends of the power distribution circuit are respectively connected to the input ends of the first quadrature demodulation circuit and the second quadrature demodulation circuit. The output end of the first PLL circuit is connected to the local oscillator end of the first quadrature demodulation circuit. The output end of the second PLL circuit is connected to the local oscillator end of the second quadrature demodulation circuit. The I / Q two-way outputs of the first quadrature demodulation circuit are respectively connected to the input ends of the first baseband pre-amplification circuit. The I / Q two-way outputs of the second quadrature demodulation circuit are respectively connected to the input ends of the second baseband pre-amplification circuit. The two output ends of the first baseband pre-amplification circuit and the two output ends of the second baseband pre-amplification circuit are respectively connected to the input ends of the electronic switch circuit. The output end of the electronic switch circuit is connected to the input end of the final amplification circuit through a baseband filter circuit. The output end of the final amplification circuit outputs the processed signal.

2. The frequency hopping zero-IF receiver circuit according to claim 1, characterized in that: The radio frequency amplification circuit includes a cascaded first-stage radio frequency amplifier and a second-stage radio frequency amplifier. The input end of the first-stage radio frequency amplifier receives the signal to be processed. The output end of the second-stage radio frequency amplifier is connected to the input end of the controllable attenuation circuit.

3. The frequency hopping zero-IF receiver circuit according to claim 1, characterized in that: The first quadrature demodulation circuit and the second quadrature demodulation circuit are respectively quadrature demodulators, with the model number of ADL5380ACPZ.

4. The frequency hopping zero-IF receiver circuit according to claim 1, wherein: The first PLL circuit and the second PLL circuit are respectively PLL chips, with the model number of HMC835LP6GE.

5. The frequency hopping zero-IF receiver circuit according to claim 1, wherein: The baseband filter circuit includes a cascaded programmable baseband filter and an LC filter. The model number of the programmable baseband filter is LTC6603IUF.

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