Image processing conversion board card and system for multipath signals

Abstract

The utility model discloses an image processing conversion board card and system used for multipath signals. The conversion board card comprises an FPGA image processing module, and a plurality of signal receiving modules and a plurality of signal sending modules which are respectively connected with the FPGA image processing module. Wherein each signal receiving module is connected with a signal input interface of the FPGA image processing module, and each signal transmitting module is connected with a signal output interface of the FPGA image processing module; the signal receiving module is used for converting input signals in various formats into signals which can be identified by the FPGA image processing module, and the signal sending module is used for converting the signals processed by the FPGA image processing module into signals in various formats and outputting the signals; the conversion board card also comprises a signal input interface selection module and a signal output interface selection module which are respectively connected with the FPGA image processing module. According to the utility model, flexible conversion of various image signals and flexible interconnection of various interface devices can be realized.

Description

Technical Field

[0001] The utility model relates to the technical field of image signal processing, and particularly relates to an image processing conversion board card and system for multiplex signals. Background Art

[0002] Although there are some devices for single or a few types of image signal conversion on the market currently, they cannot integrate multiple image signal conversion functions into one, and cannot meet the needs of users for flexible interconnection of multiple interface devices. Moreover, there are differences in image signal formats and transmission protocols between different interface devices. In practical applications, when different interface devices need to be connected and data interacted, there is a problem that the image signals cannot be directly compatible. Content of the Utility Model

[0003] The main purpose of the utility model is to provide an image processing conversion board card and system for multiplex signals, so as to realize flexible conversion of multiple image signals and flexible interconnection of multiple interface devices.

[0004] The technical solution adopted by the utility model is as follows: An image processing conversion board card for multiplex signals includes an FPGA image processing module, and a plurality of signal receiving modules and a plurality of signal sending modules respectively connected to the FPGA image processing module; wherein,

[0005] Each signal receiving module is connected to the signal input interface of the FPGA image processing module, and each signal sending module is connected to the signal output interface of the FPGA image processing module; the signal receiving module is used to convert the input signals in various formats into signals that the FPGA image processing module can recognize, and the signal sending module is used to convert the signals processed by the FPGA image processing module into signals in various formats for output.

[0006] This conversion board card further includes a signal input interface selection module and a signal output interface selection module, and the signal input interface selection module and the signal output interface selection module are respectively connected to the FPGA image processing module.

[0007] According to the above technical solution, the signal receiving module includes a 3G-SDI signal receiving module, a first Ethernet communication module, a first optical signal conversion module and a Camera Link signal processing module respectively connected to the signal input interface of the FPGA image processing module;

[0008] The signal sending module includes a 3G-SDI signal sending module, a second Ethernet communication module, a second optical signal conversion module and a MIPI signal processing module respectively connected to the signal output interface of the FPGA image processing module.

[0009] According to the above technical solution, the signal input interface selection module is an input DIP switch, and the signal output interface selection module is an output DIP switch.

[0010] According to the above technical solution, the 3G-SDI signal receiving module includes a GV8601 equalizer for converting an external SDI signal into a differential signal. The GV8601 equalizer receives the external SDI signal through an SDI BNC interface and inputs the converted differential signal into the FPGA image processing module through a GTX interface.

[0011] The 3G-SDI signal transmitting module includes a GV8500 equalizer for converting a differential signal into an SDI signal. The GV8500 equalizer receives the differential signal output by the FPGA image processing module through a GTX interface and outputs the converted SDI signal to an external SDI signal through an SDI BNC interface.

[0012] According to the above technical solution, the MIPI signal processing module includes a METICOM MC20902 bridge chip, and the METICOM MC20902 bridge chip is used to convert the signal format processed by the FPGA image processing module into the MIPI CSI standard level protocol.

[0013] According to the above technical solution, the Camera Link signal processing module includes a DS90CR288AMTDX / NOPB chip, and the DS90CR288AMTDX / NOPB chip is used to deserialize the serial data stream from the camera and input it into the FPGA image processing module.

[0014] According to the above technical solution, both the first Ethernet communication module and the second Ethernet communication module include an RTL8211F-CG Ethernet PHY chip; the first Ethernet communication module is used to parse the received Ethernet data packet into a signal recognizable by the FPGA image processing module, and the connected signal input interface is an RGMII interface; the second Ethernet communication module is used to encapsulate the signal processed by the FPGA image processing module into an Ethernet data packet, and the connected signal output interface is an RGMII interface.

[0015] According to the above technical solution, both the first optical signal conversion module and the second optical signal conversion module include a standard 10G LC-LC optical module; the first optical signal conversion module is used to convert the optical signal input by the signal input interface into a signal recognizable by the FPGA image processing module, and the second optical signal conversion module is used to convert the signal processed by the FPGA image processing module into an optical signal.

[0016] According to the above technical solution, the signal output interfaces of the FPGA image processing module are respectively connected to coupling capacitors to output HDMI signals for real-time display.

[0017] On the other hand, the present utility model provides an image processing conversion system for multiplex signals, and the system includes the above-mentioned image processing conversion board for multiplex signals.

[0018] The beneficial effects produced by the present utility model are as follows: The present utility model provides an image processing conversion board and system for multiplex signals. The image processing conversion board includes an FPGA image processing module, a plurality of signal receiving modules, and a plurality of signal sending modules. By selecting signal input interfaces and signal output interfaces, the FPGA image processing module converts images or signals in different formats into a unified format for storage, and retrieves the image data in the unified format when output is required, and converts it into the required format for output. The present utility model can achieve flexible conversion of various image signals and flexible interconnection of various interface devices.

[0019] Furthermore, the present utility model integrates various image conversion modules, reduces the number of connectors, and improves the reliability and stability of image signal conversion.

[0020] Of course, it is not necessary for any product implementing the present utility model to achieve all the above-mentioned advantages simultaneously. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model or the prior art, the following will briefly introduce the drawings required for description in the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present utility model. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0022] Figure 1 is a schematic structural diagram of an image processing conversion board for multiplex signals according to an embodiment of the present utility model;

[0023] Figure 2 is a connection diagram of a signal receiving circuit of a 3G-SDI signal receiving module according to an embodiment of the present utility model;

[0024] Figure 3 is a connection diagram of a signal sending circuit of a 3G-SDI signal sending module according to an embodiment of the present utility model;

[0025] Figure 4 is a circuit connection diagram of a MIPI signal processing module according to an embodiment of the present utility model;

[0026] Figure 5It is the circuit connection diagram of the first Ethernet communication module or the second Ethernet communication module of the embodiment of the present utility model;

[0027] Figure 6 It is the circuit connection diagram of the Camera Link signal processing module of the embodiment of the present utility model;

[0028] Figure 7(a) is the first part of the circuit connection diagram of the FPGA image processing module of the embodiment of the present utility model;

[0029] Figure 7(b) is the second part of the circuit connection diagram of the FPGA image processing module of the embodiment of the present utility model;

[0030] Figure 7(c) is the third part of the circuit connection diagram of the FPGA image processing module of the embodiment of the present utility model;

[0031] Figure 7(d) is the fourth part of the circuit connection diagram of the FPGA image processing module of the embodiment of the present utility model. Detailed implementation manners

[0032] In order to make the purpose, technical solutions and advantages of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0033] It should be noted that the diagrams provided in the embodiments of the present utility model only illustrate the basic concept of the present utility model in a schematic manner. Therefore, only the components related to the present utility model are shown in the diagrams, rather than being drawn according to the number, shape and size of the components in actual implementation. The types, quantities and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0034] In the present utility model, it should also be noted that when terms such as "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer", etc. appear, the orientation or positional relationship indicated is based on the orientation or positional relationship shown in the drawings. It is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, so it cannot be understood as a limitation to the present application. In addition, when terms such as "first" and "second" appear, they are only used for descriptive and distinguishing purposes and cannot be understood as indicating or implying relative importance.

[0035] Embodiment 1

[0036] This embodiment provides an image processing conversion board for multi-channel signals, including an FPGA image processing module, multiple signal receiving modules, multiple signal sending modules, a DIP switch input, and a DIP switch output. The structure is as shown in Figure 1 shown. The multiple signal receiving modules and the multiple signal sending modules are both connected to the FPGA image processing module, and the DIP switch input and the DIP switch output are also connected to the FPGA image processing module.

[0037] Among them, each signal receiving module is connected to the signal input interface of the FPGA image processing module, and is used to convert the input signals of various formats into signals that the FPGA image processing module can recognize, and input them into the FPGA image processing module through the signal input interface.

[0038] Each signal sending module is connected to the signal output interface of the FPGA image processing module, and is used to receive the signals processed by the FPGA image processing module through the signal output interface and convert them into signals of various formats for output.

[0039] The DIP switch input is used to indicate the selected signal input interface to the FPGA image processing module, and the DIP switch output is used to indicate the selected signal output interface to the FPGA image processing module.

[0040] By detecting the states of the DIP switch input and the DIP switch output, the signal input interface and the signal output interface are selected. The FPGA image processing module receives image data from the selected signal input interface, processes it into RGB format and caches it in the DDR3 memory, and then sends the RGB format image data to the selected signal output interface.

[0041] Further, the signal receiving module includes a 3G-SDI signal receiving module, a first Ethernet communication module, a first optical signal conversion module, and a Camera Link signal processing module, which are respectively connected to the signal input interface of the FPGA image processing module.

[0042] The signal sending module includes a 3G-SDI signal sending module, a second Ethernet communication module, a second optical signal conversion module, and an MIPI signal processing module, which are respectively connected to the signal output interface of the FPGA image processing module.

[0043] The FPGA image processing module is a module containing multiple FPGA image processing units. Each FPGA image processing unit contains an XC7A100TFGG484 chip. For clear layout, the FPGA image processing module is divided into four parts, and the circuit connections of each part are shown in Figures 7(a), 7(b), 7(c), and 7(d) respectively.

[0044] Among them, the circuit connection of the 3G-SDI signal receiving module is asFigure 2 As shown, the GV8601 equalizer is adopted to decode and encode the 3G-SDI signal, and convert the 3G-SDI signal into a digital signal recognizable by the FPGA image processing module. The circuit connection of the 3G-SDI signal transmission module is as Figure 3 shown. The GV8500 equalizer is adopted to convert the digital signal output by the FPGA image processing module into a 3G-SDI signal for output.

[0045] The circuit connection of the MIPI signal processing module is as Figure 4 shown. The MC20902 bridge chip of METICOM is adopted to convert the image data processed by the FPGA image processing module into the MIPI CSI standard level and protocol, simulate the MIPI CSI interface of the camera, and meet the injection simulation requirements of the MIPI CSI interface.

[0046] The circuit connection of the first Ethernet communication module and the second Ethernet communication module is as Figure 5 shown. The RTL8211F-CG Ethernet PHY chip is adopted, and the connected signal input interface or signal output interface is the RGMII interface. Among them, the first Ethernet communication module is used to receive external Ethernet data packets, parse out the image data, and transmit it to the FPGA image processing module for processing. The second Ethernet communication module is used to encapsulate the image data from the signal output interface into an Ethernet data packet for transmission.

[0047] The first optical signal conversion module and the second optical signal conversion module adopt standard 10G LC-LC optical modules to realize the mutual conversion between optical signals and electrical signals. Among them, the first optical signal conversion module is used to convert the input optical signal into an electrical signal and then transmit it to the FPGA image processing module, and the second optical signal conversion module is used to convert the electrical signal output by the FPGA image processing module into an optical signal for output, which can meet the requirements of long-distance and high-speed stable image transmission.

[0048] The circuit connection of the Camera Link signal processing module is as Figure 6 shown. The DS90CR288AMTDX / NOPB chip is adopted to receive and decode the image signal of the Camera Link interface, convert the Camera Link signal into a signal format that can be processed by the FPGA image processing module, so as to realize the connection and data transmission with the Camera Link interface device. Preferably, by adopting three groups of DS90CR288AMTDX / NOPB chips in this module, suitable configurations and connection methods can be provided for the Base, Medium, and Full three configurations of Camera Link.

[0049] Specifically, when the image processing conversion board card receives signals from an external signal source:

[0050] The signal input interface is selected by detecting the status of the input DIP switch. The FPGA image processing module analyzes and processes the image data of the selected signal input interface, uniformly converts it into the RGB format, and caches it in the DDR3 memory.

[0051] When the signal input interface corresponding to the 3G-SDI signal receiving module is selected, the external SDI image data is connected to the SDI BNC interface of the image processing conversion board card for multiple signals through a coaxial cable. The GV8601 equalizer converts the single-ended coaxial signal into a differential signal, which is connected to the FPGA image processing module through the GTX interface. The Xilinx SDI IP is used to convert the original data into RGB data, and the data is cached in the DDR3 memory through the FDMA controller.

[0052] When the signal input interface corresponding to the Camera Link signal processing module is selected, the Camera Link signal processing module uses DS90LV047ATMTCX / NOPB to output the camera control signals CC1 and CC2, providing camera trigger control and reset initialization functions. The FPGA image processing module collects the lvds differential signals output by the DS90CR288AMTDX / NOPB chip, decodes them, and converts them into RGB image data, which is cached in the DDR3 memory.

[0053] When the signal input interface corresponding to the first Ethernet communication module is selected, the Ethernet communication module uses the PHY chip RTL8211, based on the UDP protocol, to set parameters such as the exposure time, gain, and trigger mode of the camera. The FPGA image processing module performs preprocessing operations such as decoding and format conversion on the received image data, and caches the data in the DDR3 memory.

[0054] When the signal input interface corresponding to the first optical signal conversion module is selected, the optical signal of the optical module uses multimode LC fiber communication and enters the optical signal conversion module through a board-to-board connector. The FPGA image processing module receives the image data through the GTX interface, performs preprocessing operations such as decoding and format conversion, and caches the data in the DDR3 memory.

[0055] When the image processing conversion board card sends signals from an external signal source: By detecting the status of the output DIP switch, the signal output interface is selected, and the RGB format image data is converted into the format of the external signal connected to the signal output interface.

[0056] When the signal output interface corresponding to the 3G-SDI signal transmission module is selected, after the FPGA image processing module reads the RGB image data, it encodes the data into a serial data stream compliant with the 3G-SDI standard using the SMPTE SDI IP core of Xilinx. Then, the data is serialized through the GTX interface and the signal quality is optimized before being input into the 3G-SDI signal transmission module. The signal transmission circuit of the 3G-SDI signal transmission module uses the GV8500 chip to convert the differential signal output by the FPGA image processing module into a single-ended signal and enhance the driving ability of the signal, which is then output to the coaxial cable through the BNC interface.

[0057] When the signal output interface corresponding to the MIPI signal processing module is selected, the signal output interface uses the mipicsi tx interface to output the RGB image data of the FPGA image processing module. After the MIPI signal processing module reads the RGB image data, it processes the image data using the MIPI CSI2 Tx Subsystem IP and outputs the mipi csi tx image signal through the chip MC20902.

[0058] When the signal output interface corresponding to the second Ethernet communication module is selected, after the FPGA image processing module reads the RGB image data, it encodes and processes the image and uses the RGMII interface as the signal output interface to send the data to the second Ethernet communication module. The second Ethernet communication module uses the PHY chip RTL8211-CG to transmit Ethernet data packets based on the UDP protocol and outputs the data to the gigabit Ethernet interface device through the network transformer.

[0059] When the signal output interface corresponding to the second optical signal conversion module is selected, after the FPGA image processing module obtains the RGB image data from the DDR3 memory, it performs timing and format conversion on the image data through the RBG to BT1120 IP core, and then converts the processed image data into an optical signal through the second optical signal conversion module and outputs it through the GTX interface of the FPGA image processing module.

[0060] Preferably, each signal output interface is respectively connected to a 100 nF coupling capacitor to output the HDMI signal for real-time display.

[0061] This embodiment also provides an image processing and conversion system for multiplex signals, which includes the above-mentioned image processing and conversion board for multiplex signals.

[0062] Embodiment 2

[0063] This embodiment provides another image processing conversion board for multi-channel signals. The difference from the image processing conversion board described in Embodiment 1 is that the signal input interface selection module and the signal output interface selection module of the image processing conversion board in this embodiment select the signal input interface and the signal output interface by detecting the levels of the signal input interface and the signal output interface respectively.

[0064] In summary, the present invention provides an image processing conversion board and system for multi-channel signals, which can realize flexible conversion of various image signals and flexible interconnection of various interface devices.

[0065] It should be noted that according to the needs of implementation, each step / component described in this application can be split into more steps / components, or two or more steps / components or partial operations of steps / components can be combined into new steps / components to achieve the purpose of the present invention.

[0066] In the above embodiments, the magnitudes of the sequence numbers of the steps do not mean the order of execution. The order of execution of each process should be determined by its function and internal logic, and should not constitute any limitation to the implementation process of the embodiments of this application.

[0067] It should be understood that those of ordinary skill in the art can make improvements or transformations according to the above description, and all such improvements and transformations should fall within the protection scope of the appended claims of the present invention.

Claims

1. An image processing conversion board for multiplex signals, characterized in that, It includes an FPGA image processing module, as well as a plurality of signal receiving modules and a plurality of signal sending modules respectively connected to the FPGA image processing module; among them, each signal receiving module is connected to the signal input interface of the FPGA image processing module, and each signal sending module is connected to the signal output interface of the FPGA image processing module; the signal receiving module is used to convert the input signals of various formats into signals that the FPGA image processing module can recognize, and the signal sending module is used to convert the signals processed by the FPGA image processing module into signals of various formats for output; This conversion board also includes a signal input interface selection module and a signal output interface selection module, and the signal input interface selection module and the signal output interface selection module are respectively connected to the FPGA image processing module.

2. The image processing conversion board for multi-channel signals according to claim 1, wherein The signal receiving module includes a 3G-SDI signal receiving module, a first Ethernet communication module, a first optical signal conversion module, and a Camera Link signal processing module respectively connected to the signal input interface of the FPGA image processing module; The signal sending module includes a 3G-SDI signal sending module, a second Ethernet communication module, a second optical signal conversion module, and an MIPI signal processing module respectively connected to the signal output interface of the FPGA image processing module.

3. The image processing conversion board for multi-channel signals according to claim 1, characterized in that, The signal input interface selection module is an input DIP switch, and the signal output interface selection module is an output DIP switch.

4. The image processing conversion board for multiplex signals according to claim 2, wherein the 3G-SDI signal receiving module includes a GV8601 equalizer for converting an external SDI signal into a differential signal, the GV8601 equalizer receives the external SDI signal through an SDI BNC interface, and inputs the converted differential signal into the FPGA image processing module through a GTX interface; the 3G-SDI signal sending module includes a GV8500 equalizer for converting a differential signal into an SDI signal, the GV8500 equalizer receives the differential signal output by the FPGA image processing module through a GTX interface, and outputs the converted SDI signal to the external SDI signal through an SDI BNC interface.

5. The image processing conversion board for multiplex signals according to claim 2, wherein The MIPI signal processing module includes a METICOM MC20902 bridge chip, and the METICOM MC20902 bridge chip is used to convert the signal format processed by the FPGA image processing module into the MIPI CSI standard level protocol.

6. The image processing conversion board for multi-channel signals according to claim 2, characterized in that, The CameraLink signal processing module includes a DS90CR288AMTDX / NOPB chip, and the DS90CR288AMTDX / NOPB chip is used to deserialize the serial data stream from the camera and input it into the FPGA image processing module.

7. The image processing conversion board for multi-channel signals according to claim 2, wherein Both the first Ethernet communication module and the second Ethernet communication module include RTL8211F-CG Ethernet PHY chips; the first Ethernet communication module is used to parse the received Ethernet data packets into signals that the FPGA image processing module can recognize, and the connected signal input interface is an RGMII interface; The second Ethernet communication module is used to encapsulate the signals processed by the FPGA image processing module into Ethernet data packets, and the connected signal output interface is an RGMII interface.

8. The image processing conversion board for multi-channel signals according to claim 2, wherein Both the first optical signal conversion module and the second optical signal conversion module include standard 10G LC-LC optical modules; the first optical signal conversion module is used to convert the optical signals input from the signal input interface into signals recognizable by the FPGA image processing module, and the second optical signal conversion module is used to convert the signals processed by the FPGA image processing module into optical signals.

9. The image processing conversion board for multi-channel signals according to claim 1, characterized in that, The signal output interfaces of the FPGA image processing module are respectively connected to coupling capacitors to output HDMI signals for real-time display.

10. An image processing conversion system for multi-channel signals, characterized in that, The system includes the image processing conversion board for multiplex signals according to any one of claims 1-9.

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