Semiconductor device structure

Abstract

The utility model provides a semiconductor device structure which comprises a substrate, a first electron supply layer, a channel layer, a second electron supply layer, a first barrier layer, a second barrier layer and a cap layer which are sequentially stacked from bottom to top, and the cap layer is provided with a groove exposing the second barrier layer; the gate electrode is located on the second barrier layer and located in the groove, the gate electrode comprises a first metal layer, and the material of the first metal layer comprises Pt metal; wherein the first barrier layer is used for preventing Pt metal from diffusing to the second electron supply layer, the first barrier layer comprises an AlAs barrier layer, and the second barrier layer is used as a corrosion stop layer when the cap layer is corroded to form the groove. Due to the fact that the Pt metal is diffused slowly in the AlAs, the Pt metal stays in the first barrier layer through the evaporation and alloying process, the distance between the Pt metal and the channel layer is stable, and therefore the threshold voltage fluctuation of the device is relatively small.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a semiconductor device body structure. Background Art

[0002] The gate metal of the traditional pHEMT structure includes Pt metal. By adjusting the Pt thickness and the tempering process, the distance between Pt and the channel after diffusion can be controlled, so that the device exhibits different threshold voltages (Vto), and D-mode devices and E-mode devices can be fabricated.

[0003] For E-mode devices, the threshold voltage is usually positive, and it is required that the distance between Pt and the channel is relatively close. Since Pt diffuses unevenly in the barrier layer and the electron supply layer, the distance deviation between the gate Pt metal and the channel in different regions is very large, resulting in a large fluctuation in the threshold voltage of the device. Summary of the Utility Model

[0004] The purpose of the utility model is to provide a semiconductor device structure to solve one or more problems in the prior art.

[0005] To solve the above technical problems, the utility model provides a semiconductor device structure, which includes:

[0006] A substrate, a first electron supply layer, a channel layer, a second electron supply layer, a first barrier layer, a second barrier layer, and a capping layer stacked in sequence from bottom to top. The capping layer has a trench exposing the second barrier layer; and,

[0007] A gate located on the second barrier layer and within the trench. The gate includes a first metal layer, and the material of the first metal layer includes Pt metal;

[0008] Wherein, the first barrier layer is used to prevent Pt metal from diffusing into the second electron supply layer. The first barrier layer includes an AlAs barrier layer, and the second barrier layer serves as an etch stop layer when etching the capping layer to form the trench.

[0009] Optionally, in the semiconductor device structure, the thickness of the first barrier layer is

[0010] Optionally, in the semiconductor device structure, the capping layer includes a GaAs layer.

[0011] Optionally, in the semiconductor device structure, the material of the second barrier layer includes an InGaP barrier layer.

[0012] Optionally, in the semiconductor device structure, the thickness of the second barrier layer is

[0013] Optionally, in the semiconductor device structure described above, the first electron supply layer includes a first barrier layer and a first planar doped layer covering the first barrier layer;

[0014] The second electron supply layer includes a second planar doped layer and a second barrier layer covering the second planar doped layer.

[0015] Optionally, in the semiconductor device structure described above, both the first barrier layer and the second barrier layer include an Al x Ga 1-x As layer, and both the first planar doped layer and the second planar doped layer include an Al-doped silicon layer.

[0016] Optionally, in the semiconductor device structure described above, the semiconductor device structure further includes a first spatial isolation layer and a second spatial isolation layer. The first spatial isolation layer is formed between the channel layer and the first planar doped layer, and the second spatial isolation layer is formed between the second planar doped layer and the channel layer.

[0017] Optionally, in the semiconductor device structure described above, both the first spatial isolation layer and the second spatial isolation layer include an Al x Ga 1-x As layer.

[0018] Optionally, in the semiconductor device structure described above, the channel layer includes a first GaAs layer, an InGaAs layer, and a second GaAs layer stacked in sequence from bottom to top.

[0019] In summary, the semiconductor device structure provided by the present invention includes: a substrate, a first electron supply layer, a channel layer, a second electron supply layer, a first barrier layer, a second barrier layer, and a capping layer stacked in sequence from bottom to top. The capping layer has a trench exposing the second barrier layer; and a gate located on the second barrier layer and within the trench. The gate includes a first metal layer, and the material of the first metal layer includes Pt metal; wherein the first barrier layer is used to prevent the Pt metal from diffusing into the second electron supply layer, the first barrier layer includes an AlAs barrier layer, and the second barrier layer serves as an etch stop layer when etching the capping layer to form the trench. Since Pt metal diffuses very slowly in AlAs, after evaporation and alloying processes, the Pt metal stays in the first barrier layer, and the distance from the Pt metal to the channel layer is relatively stable. Therefore, the threshold voltage fluctuation of the device is relatively small. Description of the Drawings

[0020] Figure 1The structural schematic diagram of the semiconductor device structure provided by the embodiment of the present utility model;

[0021] Among them, the descriptions of each reference numeral are as follows:

[0022] 10 - Substrate; 11 - First electron supply layer; 12 - Channel layer; 13 - Second electron supply layer; 14 - First barrier layer; 15 - Second barrier layer; 16 - Capping layer; 17 - Gate; 18 - Source; 19 - Drain; 100 - Trench. Detailed implementation manners

[0023] To make the objectives, advantages and features of the present utility model clearer, the present utility model will be described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and use non - precise scales, only for facilitating and clearly assisting in explaining the objectives of the embodiments of the present utility model. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the emphases to be shown in each of the accompanying drawings are different, and sometimes different scales are used. It should be recognized that relative terms such as "above", "below", "top", "bottom", "upper" and "lower" shown in the accompanying drawings can be used to describe the relationships between various elements with respect to each other. These relative terms are intended to cover different orientations of the elements in addition to the orientations depicted in the accompanying drawings. For example, if the device is inverted relative to the view in the accompanying drawings, an element described as "above" another element will now be below that element. It should also be understood that unless otherwise specifically stated or indicated, the terms "first", "second", "third", etc. in the description are only used to distinguish each component, element, step, etc. in the description, rather than to represent the logical relationship or sequential relationship, etc. between each component, element, step.

[0024] As Figure 1 shown, the embodiment of the present utility model provides a semiconductor device structure, including:

[0025] A substrate 10, a first electron supply layer 11, a channel layer 12, a second electron supply layer 13, a first barrier layer 14, a second barrier layer 15 and a capping layer 16 stacked in sequence from bottom to top, the capping layer 16 has a trench 100 exposing the second barrier layer 15; and,

[0026] A gate 17, the gate 17 is located on the second barrier layer 15 and within the trench 100, the gate 17 includes a first metal layer, and the material of the first metal layer includes Pt metal;

[0027] Among them, the first barrier layer 14 is used to prevent the diffusion of Pt metal to the second electron supply layer 13. The first barrier layer 14 includes an AlAs barrier layer, and the second barrier layer 15 serves as an etch stop layer when etching the capping layer 16 to form the trench 100.

[0028] In the semiconductor device structure provided by the embodiment of the present invention, when the Pt metal of the gate 17 diffuses downward, since the Pt metal diffuses very slowly in AlAs, after the evaporation and alloying processes, the Pt metal stays in the first barrier layer 14, and the distance from the Pt metal to the channel layer 10 is relatively stable. Therefore, the threshold voltage fluctuation of the device is relatively small.

[0029] That is, the first barrier layer 14 functions to prevent the Pt metal from continuing to diffuse downward. If the thickness of the first barrier layer 14 is too small, it cannot play a better blocking role. If the thickness of the first barrier layer 14 is too large, it will affect the threshold voltage (Ron) of the device. Therefore, preferably, the thickness of the first barrier layer 14 is For example, it can be and so on.

[0030] Optionally, the gate 17 includes a first Pt metal layer, a first Ti metal layer, a second Pt metal layer, an Au metal layer, and a second Ti metal layer stacked in sequence from bottom to top, but the present application is not limited thereto.

[0031] Optionally, the capping layer 16 includes a GaAs layer, and this GaAs layer can specifically be a heavily doped n-type GaAs layer, that is, an n + -GaAs layer. The doping element of the capping layer 16 can be Si. The heavily doped capping layer 16 provides excellent ohmic contact for device fabrication, thereby improving the on-state resistance of the device and providing good power output for the device.

[0032] Optionally, the second barrier layer 15 includes an InGaP barrier layer. When etching the capping layer 16 to form the trench 100, the second barrier layer 15 plays an etching cutoff role, so that the capping layer 16 has a trench 100 exposing the first barrier layer 14.

[0033] Preferably, the thickness of the second barrier layer 15 is For example, it can be and so on, so that the total thickness of the second barrier layer 15 and the first barrier layer 14 is around to avoid the overall RF performance degradation caused by the excessive total thickness affecting electron transport.

[0034] Specifically, the first electron supply layer 11 may include a first barrier layer and a first planar doped layer covering the first barrier layer. Specifically, the second electron supply layer 13 may include a second planar doped layer and a second barrier layer covering the second planar doped layer.

[0035] The first barrier layer, the second barrier layer, and the channel layer 10 together form a heterojunction to confine two-dimensional electron gas (2DEG) in the channel. Optionally, both the first barrier layer and the second barrier layer include Al x Ga 1-x As layer, and this Al x Ga 1-x As layer may specifically be an n-type doped Al x Ga 1-x As layer, that is, an n-Al x Ga 1-x As layer.

[0036] Since the first blocking layer 14 is formed on the surface of the first barrier layer, and the lattices of AlAs and AlGaAs are relatively well-matched with small interface defects, it helps to improve the device performance.

[0037] The first planar doped layer and the second planar doped layer are respectively used to provide free electrons for the channel. Optionally, both the first planar doped layer and the second planar doped layer include Al-doped silicon layers. That is, the main materials of the first planar doped layer and the second planar doped layer are silicon materials, and the doping element is Al.

[0038] Optionally, the semiconductor device structure further includes a first spatial isolation layer and a second spatial isolation layer. The first spatial isolation layer is formed between the channel layer 10 and the first planar doped layer, and the second spatial isolation layer is formed between the second planar doped layer and the channel layer 10. The first spatial isolation layer and the second spatial isolation layer are respectively used to reduce the degree of scattering of impurities in the first planar doped layer and the second planar doped layer into the channel layer 10, thereby improving the electron mobility.

[0039] Optionally, both the first spatial isolation layer and the second spatial isolation layer include: Al x Ga 1-x As layer, and this Al x Ga 1-x As layer may specifically be an undoped Al x Ga 1-x As layer, that is, an i-Al x Ga 1-x As layer.

[0040] Optionally, the channel layer 10 includes a first GaAs layer, an InGaAs layer, and a second GaAs layer stacked in sequence from bottom to top, and specifically may include an undoped first GaAs layer, an InGaAs layer, and a second GaAs layer stacked in sequence from bottom to top.

[0041] Furthermore, the semiconductor device structure provided in this embodiment may further include: a substrate and a buffer layer grown on the substrate. The substrate may specifically be a GaAs substrate or other types of substrates. Correspondingly, the buffer layer may specifically be a GaAs buffer layer. The buffer layer is used to provide a flat crystal interface and eliminate the influence of substrate interface states.

[0042] In addition, as Figure 1 shown, the semiconductor device structure provided in this embodiment may further include: a source electrode 18 and a drain electrode 19, and the source electrode 18 and the drain electrode 19 are respectively formed on the surfaces of two regions where the capping layer 16 is separated by the trench 100.

[0043] The preparation process of the semiconductor device structure provided in this embodiment may include the following steps:

[0044] S1. Provide a substrate 10, and form the buffer layer, the first electron supply layer 11, the channel layer 12, the second electron supply layer 13, the first barrier layer 14, the second barrier layer 15, and the capping layer 16 stacked in sequence on the substrate 10;

[0045] S2. Prepare the source electrode 18 and the drain electrode 19 on the capping layer 16 through a yellow light and evaporation process;

[0046] S3. Prepare the trench 100 through a yellow light and etching process;

[0047] S4. Prepare the gate electrode 17 through an evaporation and stripping process, and then through a thermal process, make the underlying Pt metal fully diffuse.

[0048] Among them, the pre-treatment before photolithography in steps S1 to S3 includes but is not limited to plasma cleaning, ammonia water cleaning, dilute hydrochloric acid cleaning, etc.; in steps S1 and S4, the pre-treatment before metal evaporation includes photoresist ashing and dilute hydrochloric acid cleaning before evaporation; in steps S1 to S3, the photoresist is removed by soaking and rinsing with an NMP (N-methylpyrrolidone) solution, and then cleaned with IPA (isopropyl alcohol); in step S3, the etching process uses a wet etching process, and the etching solution includes but is not limited to citric acid, succinic acid, phosphoric acid, etc.; in step S4, the thermal process includes but is not limited to CVD (chemical vapor deposition), Alloy (alloying), Bake (baking), etc.

[0049] In summary, the semiconductor device structure provided by the embodiments of the present invention includes: a substrate, a first electron supply layer, a channel layer, a second electron supply layer, a first barrier layer, a second barrier layer, and a capping layer stacked in sequence from bottom to top. The capping layer has a trench exposing the second barrier layer; and a gate located on the second barrier layer and within the trench. The gate includes a first metal layer, and the material of the first metal layer includes Pt metal; wherein the first barrier layer is used to prevent the diffusion of Pt metal to the second electron supply layer, the first barrier layer includes an AlAs barrier layer, and the second barrier layer serves as an etch stop layer when etching the capping layer to form the trench. Since Pt metal diffuses very slowly in AlAs, after evaporation and alloying processes, Pt metal stays in the first barrier layer, and the distance from Pt metal to the channel layer is relatively stable. Therefore, the threshold voltage fluctuation of the device is relatively small.

[0050] In addition, it should also be recognized that although the present invention has been disclosed above with preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, many possible variations and modifications can be made to the technical solution of the present invention by using the technical content disclosed above, or modified into equivalent embodiments with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

Claims

1. A semiconductor device structure, characterized in that, The semiconductor device structure includes: A substrate, a first electron supply layer, a channel layer, a second electron supply layer, a first barrier layer, a second barrier layer, and a capping layer stacked in sequence from bottom to top. The capping layer has a trench exposing the second barrier layer; and, A gate located on the second barrier layer and within the trench. The gate includes a first metal layer, and the material of the first metal layer includes Pt metal; Wherein, the first barrier layer is used to prevent the diffusion of Pt metal to the second electron supply layer. The first barrier layer includes an AlAs barrier layer, and the second barrier layer serves as an etch stop layer when etching the capping layer to form the trench.

2. The semiconductor device structure according to claim 1, characterized in that, The thickness of the first barrier layer is 3. The semiconductor device structure according to claim 1, characterized in that, The capping layer includes a GaAs layer.

4. The semiconductor device structure according to claim 3, characterized in that, The material of the second barrier layer includes an InGaP barrier layer.

5. The semiconductor device structure according to claim 1, characterized in that, The thickness of the second barrier layer is 6. The semiconductor device structure according to claim 1, wherein, The first electron supply layer includes a first barrier layer and a first planar doped layer covering the first barrier layer; The second electron supply layer includes a second planar doped layer and a second barrier layer covering the second planar doped layer.

7. The semiconductor device structure according to claim 6, wherein, Both the first barrier layer and the second barrier layer include Al x Ga 1-x As layer, and both the first planar doping layer and the second planar doping layer include Al-doped silicon layer.

8. The semiconductor device structure according to claim 6, characterized in that, The semiconductor device structure further includes a first spacer layer and a second spacer layer. The first spacer layer is formed between the channel layer and the first planar doped layer, and the second spacer layer is formed between the second planar doped layer and the channel layer.

9. The semiconductor device structure according to claim 8, characterized in that, Both the first spatial isolation layer and the second spatial isolation layer include Al x Ga 1-x As layer.

10. The semiconductor device structure according to claim 1, wherein The channel layer includes a first GaAs layer, an InGaAs layer, and a second GaAs layer stacked in sequence from bottom to top.

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