Semiconductor device

Abstract

The utility model provides a semiconductor device, which comprises a substrate, a plurality of source lines, a plurality of channel material columns, a plurality of gate structures and a plurality of drain structures, and is characterized in that the plurality of source lines are positioned on the substrate, extend along a first direction and are arranged at intervals along a second direction; the plurality of channel material columns are positioned on the plurality of source lines and are connected with the source lines; the gate structure comprises a first part and a second part, the first part of the gate structure is arranged along the side wall of the channel material column, and the second part of the gate structure extends along the second direction, crosses the plurality of source lines and is connected with the first part; the plurality of drain electrode structures are positioned on the channel material column and are connected with the channel material column; according to the utility model, the influence of non-centered channel position can be avoided, so that the electrical performance of the semiconductor device is improved.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, and particularly relates to a semiconductor device. Background Art

[0002] Semiconductor transistors (such as metal-oxide-semiconductor transistors (MOS transistors)) have been used in various applications, such as power supplies, power converters, switches and other applications. Traditional MOS transistors adopt a planar structure. As the technology of semiconductor integrated circuits develops over time, MOS transistors adopt a stacked structure to realize the miniaturization of transistors. In the design of the stacked structure, generally, a plurality of strip-shaped gate structures are formed, a plurality of through holes are formed in the gate structures, and materials are filled in the through holes to form a channel structure. However, when preparing the through holes, it cannot be guaranteed that the positions of the through holes are on the center lines of the gate structures, resulting in the channels not being centered, thereby affecting the electrical performance of the semiconductor device. Summary of the Utility Model

[0003] The purpose of the utility model is to provide a semiconductor device to improve the electrical performance of the semiconductor device.

[0004] To achieve the above purpose, the utility model provides a semiconductor device, including:

[0005] A substrate;

[0006] A plurality of source lines, located on the substrate, and the plurality of source lines extend along a first direction and are arranged at intervals along a second direction;

[0007] A plurality of channel material columns, located on the plurality of source lines and connected to the source lines;

[0008] A plurality of gate structures, the gate structure includes a first part and a second part, the first part of the gate structure is arranged along the side wall of the channel material column, and the second part of the gate structure extends along the second direction across a plurality of the source lines and connects the first part;

[0009] A plurality of drain structures, located on the channel material columns and connected to the channel material columns.

[0010] Optionally, along the first direction, the first part of the gate structure has a first dimension, the second part of the gate structure has a second dimension, the channel material column has a third dimension, and the first dimension is greater than the second dimension, and the second dimension is greater than or equal to the third dimension.

[0011] Optionally, the first part and the second part of the gate structure are integrally formed, and the center lines of the first part and the second part of the gate structure do not overlap along the second direction.

[0012] Optionally, the first part of the gate structure is annular, and the second part of the gate structure is strip-shaped.

[0013] Optionally, a plurality of the channel material pillars are distributed in a matrix array, and the plurality of the channel material pillars are arranged in a plurality of rows extending in the first direction and a plurality of columns extending in the second direction, and the second part of the gate structure is connected to the channel material pillars located in the same column.

[0014] Optionally, the drain structure is connected to a plurality of adjacent channel material pillars located on the same row.

[0015] Optionally, the source line is connected to adjacent multiple rows of the channel material pillars.

[0016] Optionally, a plurality of the channel material pillars are distributed in a staggered array, and adjacent two columns of the channel material pillars are staggered in the second direction and arranged on different source lines.

[0017] Optionally, adjacent two columns of the channel material pillars are staggered on both sides of the second part of the gate structure.

[0018] In the semiconductor device provided by the present utility model, it includes: a substrate, a plurality of source lines, a plurality of channel material pillars, a plurality of gate structures and a plurality of drain structures, wherein the plurality of source lines are located on the substrate, the plurality of source lines extend in a first direction and are arranged at intervals in a second direction; the plurality of channel material pillars are located on the plurality of source lines and are connected to the source lines; the gate structure includes a first part and a second part, the first part of the gate structure is arranged along the side wall of the channel material pillar, the second part of the gate structure extends in the second direction across a plurality of source lines and is connected to the first part; the plurality of drain structures are located on the channel material pillars and are connected to the channel material pillars. In the present utility model, the gate structure is provided with a first part and a second part, the first part of the gate structure is arranged along the side wall of the channel material pillar, the second part of the gate structure extends in the second direction across a plurality of source lines and is connected to the first part, which can avoid the influence of the non-centered channel position, thereby improving the electrical performance of the semiconductor device. Description of the Drawings

[0019] Figure 1 It is a top view of the semiconductor device provided in the first embodiment of the present utility model.

[0020] Figure 2 It is a schematic cross-sectional view of the semiconductor device provided in the first embodiment of the present utility model.

[0021] Figures 3 to 23 It is a schematic diagram of the corresponding steps of the manufacturing method of the semiconductor device provided in the first embodiment of the present utility model.

[0022] Figure 24The top view of the semiconductor device provided in the second embodiment of the present utility model.

[0023] Figure 25 The schematic cross-sectional view of the semiconductor device provided in the second embodiment of the present utility model.

[0024] Figures 26 to 36 The schematic diagram of the corresponding steps of the manufacturing method of the semiconductor device provided in the second embodiment of the present utility model.

[0025] Figure 37 The top view of the semiconductor device provided in the third embodiment of the present utility model.

[0026] Figure 38 The top view of the semiconductor device provided in the fourth embodiment of the present utility model.

[0027] Figure 39 The top view of the semiconductor device provided in the fifth embodiment of the present utility model.

[0028] Among them, the reference numerals are:

[0029] 10 - Substrate; 20 - Source line; 30 - Channel material pillar; 41 - First oxide layer; 42 - Second oxide layer; 51 - Gate dielectric layer; 52 - Barrier layer; 53 - Sacrificial layer; 61 - First isolation material layer; 62 - Second isolation material layer; 63 - Third isolation material layer; 70 - Patterned mask layer; 71 - First opening; 72 - Second opening; 80 - Gate structure; 81 - First part; 82 - Second part; 90 - Drain structure; 100 - Sidewall. Detailed implementation manners

[0030] To make the objectives, advantages and features of the present utility model clearer, the present utility model will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be noted that the accompanying drawings are all in very simplified forms and are not drawn to scale, only for conveniently and clearly assisting in explaining the objectives of the embodiments of the present utility model. In addition, the structures shown in the accompanying drawings are often part of the actual structures. In particular, the accompanying drawings need to show different focuses and sometimes different scales are used.

[0031] As used in the present utility model, the singular forms "a", "an", and "the" include plural referents, the term "or" is generally used in the sense of including "and / or", the term "several" is generally used in the sense of including "at least one", the term "at least two" is generally used in the sense of including "two or more", and in addition, the terms "first", "second", "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. For those of ordinary skill in the art, the specific meanings of the above terms in the present utility model can be understood according to specific circumstances.

[0032] Embodiment 1

[0033] Figure 1 Top view of the semiconductor device provided in this embodiment; Figure 2 Cross-sectional schematic diagram of the semiconductor device provided in this embodiment, Figure 2 is Figure 1 Cross-sectional schematic diagram of the cross-section line A1A2 in Figure 1 In order to clearly show the key structures in Figure 1 part of the structures are omitted and transparency is set in Figure 1 and Figure 2 This embodiment provides a semiconductor device, including: a substrate 10, several source lines 20, several channel material pillars 30, several gate structures 80, and several drain structures 90. Among them, the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully depleted silicon-on-insulator substrate, etc., without limitation. In this embodiment, a dielectric layer (not shown in the figure) is further formed on the substrate 10, and an electrical connector is formed in the dielectric layer, and the electrical connector penetrates the dielectric layer and is electrically connected to the substrate 10 and the source line 20.

[0034] Several source lines 20 are located on the substrate 10 (specifically on the dielectric layer), several source lines 20 extend along the first direction D1 and are arranged at intervals along the second direction D2, and an isolation material layer is filled between adjacent source lines 20. In this embodiment, the source line 20 may include a first source blocking layer, a source metal layer, a second source blocking layer, and a source semiconductor layer (not shown separately in the figure) stacked in sequence from bottom to top. Among them, the materials of the first source blocking layer and the second source blocking layer may respectively include TiN, the material of the source metal layer may include W, and the material of the source semiconductor layer may include polysilicon, not limited to the above materials.

[0035] A plurality of channel material columns 30 are located on a plurality of source lines 20 and connected to the source lines 20. In this embodiment, the plurality of channel material columns 30 are arranged in a matrix array, and the plurality of channel material columns 30 are arranged in a plurality of rows extending in a first direction D1 and a plurality of columns extending in a second direction D2. In this embodiment, the material of the channel material columns 30 may include polysilicon (with doped ions), and may also include one or more combinations of metal silicide materials, ferroelectric materials, high-k dielectric materials, and indium gallium zinc oxide (IGZO).

[0036] The gate structure 80 includes a first portion 81 and a second portion 82. The first portion 81 of the gate structure 80 is disposed along the sidewalls of the channel material columns 30. The second portion 82 of the gate structure 80 extends in the second direction D2 across a plurality of source lines 20 and connects to the first portion 81, and the second portion 82 of the gate structure 80 connects the channel material columns 30 in the same column. In this embodiment, the first portion 81 of the gate structure 80 and the second portion 82 of the gate structure 80 are integrally formed (formed simultaneously in the manufacturing process), and the midline S1 of the first portion 81 of the gate structure 80 and the midline S2 of the second portion 82 of the gate structure 80 do not overlap along the second direction D2. The first portion 81 of the gate structure 80 is annular, and the second portion 82 of the gate structure 80 is strip-shaped.

[0037] In this embodiment, along the first direction D1, the first portion 81 of the gate structure 80 has a first dimension CD1, the second portion 82 of the gate structure 80 has a second dimension CD2, the channel material columns 30 have a third dimension CD3, and the first dimension CD1 is greater than the second dimension CD2, the second dimension CD2 is greater than or equal to the third dimension CD3, and the second dimension CD2 and the third dimension CD3 can be designed according to the minimum process dimension of the current process platform. In this embodiment, the gate structure 80 can be a metal stack, such as TiN, W, not limited to the above materials.

[0038] Furthermore, there is a gate dielectric layer 51 and a barrier layer 52 between the first portion 81 of the gate structure 80 and the channel material columns 30. The gate dielectric layer 51 and the barrier layer 52 are sequentially disposed along the sidewalls of the channel material columns 30, and the first portion 81 of the gate structure 80 is located on the gate dielectric layer 51 and the barrier layer 52; the material of the gate dielectric layer 51 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride, and the barrier layer 52 may include titanium nitride, not limited to the above materials. Further, there is also a first oxide layer 41 covering the source lines 20, and the gate dielectric layer 51 and the barrier layer 52 are located on the first oxide layer 41.

[0039] Further, it further includes a first isolation material layer 61 and a second isolation material layer 62. The first isolation material layer 61 is filled between adjacent gate structures 80, and the second portion 82 of the gate structure 80 is located on the first isolation material layer 61; the top of the gate structure 80 is lower than the top of the channel material pillar 30, and the second isolation material layer 62 is located on the gate structure 80, and the tops of the channel material pillar 30, the first isolation material layer 61, and the second isolation material layer 62 are flush. In this embodiment, the materials of the first isolation material layer 61 and the second isolation material layer 62 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon carbonitride oxides, not limited to the above materials.

[0040] A plurality of drain structures 90 are located on the channel material pillar 30 and connected to the channel material pillar 30. One drain structure 90 is connected to one channel material pillar 30. Along the first direction D1 and the second direction D2, the dimensions of the drain structure 90 may be similar to the dimensions of the first portion 81 of the gate structure 80. In this embodiment, the drain structure 90 includes a drain barrier layer and a drain metal layer (not shown in the figure) stacked in sequence from bottom to top. The material of the drain barrier layer may include TiN, and the material of the drain metal layer may include W, not limited to the above materials.

[0041] Further, it further includes sidewalls 100 and a third isolation material layer 63. The sidewalls 100 cover the sides of the drain structures 90; the third isolation material layer 63 is filled between adjacent drain structures 90; the materials of the sidewalls 100 and the third isolation material layer 63 are different. The material of the sidewalls 100 may include silicon nitride, and the material of the third isolation material layer 63 may include one of low-k dielectric materials, oxides, nitrides, oxynitrides, and silicon carbonitride oxides, not limited to the above materials.

[0042] In this embodiment, the gate structure 80 is provided to include a first portion 81 and a second portion 82. The first portion 81 of the gate structure 80 is disposed along the sidewall of the channel material pillar 30, and the second portion 82 of the gate structure 80 extends along the second direction D2 across a plurality of source lines 20 and connects to the first portion 81, which can avoid the influence of the non-centered position of the channel (channel material pillar 30), thereby improving the electrical performance of the semiconductor device.

[0043] This embodiment also provides a method for manufacturing a semiconductor device for manufacturing the above semiconductor device, including:

[0044] Step S1: Provide a substrate;

[0045] Step S2: Form a plurality of source lines on the substrate. The plurality of source lines extend along the first direction and are arranged at intervals from each other along the second direction;

[0046] Step S3: Form a plurality of channel material pillars on the plurality of source lines and connect them to the source lines;

[0047] Step S4: Form a plurality of gate structures, where the gate structure includes a first part and a second part. The first part of the gate structure is disposed along the sidewall of the channel material column, and the second part of the gate structure extends in a second direction across a plurality of source lines and connects to the first part;

[0048] Step S5: Form a plurality of drain structures on the channel material column and connect them to the channel material column.

[0049] Figures 3 to 23 Schematic diagrams of corresponding steps of the manufacturing method of the semiconductor device provided in this embodiment. The following combines Figures 3 to 23 to describe in detail the manufacturing method of the semiconductor device provided in this embodiment.

[0050] Please refer to Figure 3 and Figure 4 , Figure 4 which is Figure 3 a cross-sectional schematic diagram along the section line A1A2 in . Execute Step S1: Provide a substrate 10, and the substrate 10 can be a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium-silicon substrate, a fully depleted silicon-on-insulator substrate, etc., without limitation. In this embodiment, a dielectric layer (not shown in the figure) is further formed on the substrate 10, and an electrical connector is formed in the dielectric layer. The electrical connector penetrates the dielectric layer and is electrically connected to the substrate 10 and the source line 20.

[0051] Please refer to Figure 3 and Figure 4 , and execute Step S2: Form a plurality of source lines 20 on the substrate 10 (specifically on the dielectric layer). The plurality of source lines 20 extend in a first direction D1 and are arranged at intervals in a second direction D2. An isolation material layer (not shown in the figure) is filled between adjacent source lines 20, and the material of the source line 20 is as described above.

[0052] Please refer to Figure 3 and Figure 4 , and execute Step S3: Form a plurality of channel material columns 30 on the plurality of source lines 20 and connect them to the source lines 20. The channel material columns 30 can be designed according to the minimum process size of the current process platform, and the material of the channel material columns 30 is as described above. A first oxide layer 41 is formed on the source line 20, and the channel material column 30 passes through the first oxide layer 41 and is connected to the source line 20; a second oxide layer 42 is formed on the top of the channel material column 30 as a protective layer. In this embodiment, the plurality of channel material columns 30 are arranged in a matrix array, and the plurality of channel material columns 30 are arranged in a plurality of rows extending in the first direction D1 and a plurality of columns extending in the second direction D2.

[0053] The steps of executing Step S4 to form the gate structure include:

[0054] Please refer to Figure 5 andFigure 6 , Figure 6 is Figure 5 a schematic cross-sectional view along the section line A1A2 in Figure 5 In order to clearly show the source line and some structures in Figure 5 the top view is not fully shown, and in Figure 5 some structures are set with transparency. A sacrificial layer 53 is formed to cover the sidewalls of the channel material pillars 30 by using a self-alignment process. Before forming the sacrificial layer 53, a gate dielectric layer 51 and a barrier layer 52 are sequentially formed to cover the sidewalls of the channel material pillars 30, and the gate dielectric layer 51, the barrier layer 52, and the sacrificial layer 53 extend to cover the surface of the exposed first oxide layer 41 of the adjacent channel material pillars 30; the materials of the gate dielectric layer 51 and the barrier layer 52 are as described above, and the material of the sacrificial layer 53 may include silicon nitride, not limited to the above materials.

[0055] Please refer to Figure 7 and Figure 8 , Figure 8 is Figure 7 a schematic cross-sectional view along the section line A1A2 in Figure 7 the first oxide layer 41 is not shown. Part of the gate dielectric layer 51, the barrier layer 52, and the sacrificial layer 53 are etched to expose the first oxide layer 41 and the second oxide layer 42. After etching, the remaining gate dielectric layer 51, the barrier layer 52, and the sacrificial layer 53 are disposed along the sidewalls of the channel material pillars 30. The remaining gate dielectric layer 51 is annularly located on the sidewalls of the channel material pillars 30, and the remaining gate dielectric layer 51 is located on the remaining barrier layer 52 and the sacrificial layer 53.

[0056] Please refer to Figure 9 and Figure 10 , Figure 10 is Figure 9 a schematic cross-sectional view along the section line A1A2 in

[0057] Please refer to Figure 11 and Figure 12 , Figure 12 is Figure 11 a schematic cross-sectional view along the section line A1A2 in

[0058] Please refer to Figure 13 and Figure 14 , Figure 14 is Figure 13Schematic cross-sectional view along the section line A1A2. For clearly showing some structures, the top view is not fully shown in Figure 13 Using the patterned mask layer 70 as a mask, etch part of the first isolation material layer 61 to form a plurality of first openings 71 extending along the second direction D2; then, remove the patterned mask layer 70.

[0059] Please refer to Figure 15 and Figure 16 , Figure 16 is Figure 15 Schematic cross-sectional view along the section line A1A2. For clearly showing some structures, the top view is not fully shown in Figure 15 Remove the sacrificial layer 53. After removing the sacrificial layer 53, a second opening 72 is formed at the position where the sacrificial layer 53 is located, and the first opening 71 and the second opening 72 communicate with each other.

[0060] Please refer to Figure 17 and Figure 18 , Figure 18 is Figure 17 Schematic cross-sectional view along the section line A1A2. A gate structure 80 is formed in the first opening 71 and the second opening 72. The gate structure 80 in the first opening 71 serves as the second part 82, and the gate structure 80 in the second opening 72 serves as the first part 81. The first part 81 of the gate structure 80 is disposed along the sidewall of the channel material pillar 30, and the second part 82 of the gate structure 80 extends along the second direction D2 across multiple source lines 20 and connects to the first part 81. In this embodiment, the first part 81 of the gate structure 80 and the second part 82 of the gate structure 80 are integrally formed under the same process conditions.

[0061] Furthermore, please refer to Figure 19 , etch part of the gate structure 80 so that the top of the gate structure 80 is lower than the top of the channel material pillar 30, and etch part of the barrier layer 52 so that the top of the barrier layer 52 is flush with the top of the gate structure 80.

[0062] Please refer to Figure 20 and Figure 21 , Figure 21 is Figure 20 Schematic cross-sectional view along the section line A1A2. A second isolation material layer 62 is formed to cover the gate structure 80, the first isolation oxide layer 61, and the second oxide layer 42. The material of the second isolation material layer 62 is as described above.

[0063] Please refer to Figure 22 and Figure 23 , Figure 23 is Figure 22Schematic cross-sectional view along the section line A1A2. The second isolation material layer 62, part of the first isolation oxide layer 61 and the second oxide layer 42 are etched away to expose the top of the channel material column 30. After etching, the top of the second isolation material layer 62, the first isolation oxide layer 61 and the channel material column 30 are flush.

[0064] Please refer to Figure 1 and Figure 2 , perform step S5: form a plurality of drain structures 90 on the channel material column 30 and connected to the channel material column 30. Along the first direction D1 and the second direction D2, the dimensions of the drain structure 90 can be similar to those of the first part 81 of the gate structure 80, and the material of the drain structure 90 is as described above.

[0065] Furthermore, it further includes forming sidewalls 100 and a third isolation material layer 63. The sidewalls 100 cover the sides of the drain structures 90; the third isolation material layer 63 is filled between adjacent drain structures 90; the materials of the sidewalls 100 and the third isolation material layer 63 are as described above.

[0066] Embodiment 2

[0067] Figure 24 Top view of the semiconductor device provided in this embodiment, Figure 25 Cross-sectional schematic view of the semiconductor device provided in this embodiment, Figure 25 is Figure 24 Cross-sectional schematic view of the section line A1A2 in Figure 24 In order to clearly show the key structures, some structures are omitted and the transparency is set in Figure 24 . The difference between this embodiment and Embodiment 1 is that: the second part 82 of the gate structure 80 is connected to the channel material columns 30 located in adjacent two columns, and the drain structure 90 is connected to adjacent multiple channel material columns 30 located in the same row. In this embodiment, the drain structure 90 is connected to two adjacent channel material columns 30 located in the same row. Other structures in this embodiment are the same as those in Embodiment 1. For details, please refer to the description of Embodiment 1.

[0068] The preparation method of the semiconductor device provided in this embodiment is different from that of Embodiment 1 in that: the structures of the first opening and the second opening formed are different, and the structure of the drain structure formed is different.

[0069] Figures 26 to 36 Schematic diagram of the corresponding steps of the preparation method of the semiconductor device provided in this embodiment. The following combines Figures 26 to 36 to detail the differences between the preparation method of the semiconductor device provided in this embodiment and that of Embodiment 1.

[0070] Please refer to Figure 26 and Figure 27 , Figure 27 isFigure 26 A patterned mask layer 70 is formed to cover a portion of the first isolation material layer 61, a portion of the sacrificial layer 53 and the channel material pillars 30, which is different from the first embodiment in that the patterned mask layer 70 exposes the first isolation material layer 61 between portions of adjacent channel material pillars 30 along the first direction D1.

[0071] Please refer to Figure 28 and Figure 29 , Figure 29 for Figure 28 The cross-sectional diagram along the section line A1A2 in FIG. 1 is a cross-sectional diagram of the embodiment of the present invention. In order to clearly illustrate some structures, Figure 28 The top view is not fully shown in the figure. Using the patterned mask layer 70 as a mask, a portion of the first isolation material layer 61 is etched to form a plurality of first openings 71 extending along the second direction D2. The difference from the first embodiment is that both side walls of the first openings 71 expose the sacrificial layer 53. Then, the patterned mask layer 70 is removed.

[0072] Please refer to Figure 30 and Figure 31 , Figure 31 for Figure 30 The cross-sectional diagram along the section line A1A2 in FIG. 1 is a cross-sectional diagram of the embodiment of the present invention. In order to clearly illustrate some structures, Figure 30 The sacrificial layer 53 is removed, and after the sacrificial layer 53 is removed, a second opening 72 is formed at the location where the sacrificial layer 53 is located, and the first opening 71 and the second opening 72 are connected.

[0073] Please refer to Figure 32 and Figure 33 , Figure 33 for Figure 32 Schematic cross-sectional view along the section line A1A2 in FIG. A gate structure 80 is formed in the first opening 71 and the second opening 72, the gate structure 80 in the first opening 71 serves as the second portion 82, and the gate structure 80 in the second opening 72 serves as the first portion 81. The first portion 81 of the gate structure 80 is arranged along the sidewall of the channel material column 30, the second portion 82 of the gate structure 80 extends along the second direction D2 across multiple source lines 20 and connects the first portion 81, and the second portion 82 of the gate structure 80 connects the channel material columns 30 located in two adjacent columns. In the present embodiment, the first portion 81 of the gate structure 80 and the second portion 82 of the gate structure 80 are integrally formed under the same process conditions.

[0074] For further information, please refer to Figure 34 , a portion of the gate structure 80 is etched so that the top of the gate structure 80 is lower than the top of the channel material column 30 , and a portion of the barrier layer 52 is etched so that the top of the barrier layer 52 is flush with the top of the gate structure 80 .

[0075] Please refer toFigure 35 and Figure 36 , Figure 36 is Figure 35 a schematic cross-sectional view along the section line A1A2 in [the figure]. A second isolation material layer 62 is formed to cover the gate structure 80, the first isolation oxide layer 61 and the second oxide layer 42; further, a part of the second isolation material layer 62, a part of the first isolation oxide layer 61 and the second oxide layer 42 are etched away to expose the top of the channel material pillar 30, and after etching, the top of the second isolation material layer 62, the first isolation oxide layer 61 and the channel material pillar 30 are flush.

[0076] Please refer to Figure 24 and Figure 25 , and a plurality of drain structures 90 are formed on the channel material pillars 30 and connected to the channel material pillars 30. The drain structure 90 is connected to adjacent multiple channel material pillars 30 in the same row. In this embodiment, the drain structure 90 is connected to two adjacent channel material pillars 30 in the same row.

[0077] Furthermore, it further includes forming sidewalls 100 and a third isolation material layer 63. The sidewalls 100 cover the sides of the drain structures 90; the third isolation material layer 63 is filled between adjacent drain structures 90.

[0078] Embodiment Three

[0079] Figure 37 is a top view of the semiconductor device provided in this embodiment. The difference between this embodiment and Embodiment Two is that: the source line 20 is connected to adjacent multiple rows of channel material pillars 30. In this embodiment, the source line 20 is connected to two adjacent rows of channel material pillars 30, and the drain structure 90 is connected to two adjacent channel material pillars 30 in adjacent two rows; other structures in this embodiment are the same as those in Embodiment Two.

[0080] Embodiment Four

[0081] Figure 38 is a top view of the semiconductor device provided in this embodiment. The difference between this embodiment and Embodiment Three is that: the source line 20 is connected to adjacent three rows of channel material pillars 30, and the drain structure 90 is connected to two adjacent channel material pillars 30 in adjacent three rows; other structures in this embodiment are the same as those in Embodiment Three.

[0082] Embodiment Five

[0083] Figure 39This is a top view of the semiconductor device provided in this embodiment. The difference between this embodiment and the first embodiment lies in that: a plurality of channel material pillars 30 are arranged in a staggered array, and two adjacent columns of channel material pillars 30 are staggeredly arranged on different source lines 20 along the second direction D2, and two adjacent columns of channel material pillars 30 are staggeredly arranged on both sides of the second part 82 of the gate structure 80. Similarly, the first part 81 of the gate structure 80 is also staggeredly arranged on both sides of the second part 82 of the gate structure 80.

[0084] In summary, in the semiconductor device provided by the present invention, it includes: a substrate, a plurality of source lines, a plurality of channel material pillars, a plurality of gate structures and a plurality of drain structures. Among them, the plurality of source lines are located on the substrate, the plurality of source lines extend along the first direction and are arranged at intervals along the second direction; the plurality of channel material pillars are located on the plurality of source lines and are connected to the source lines; the gate structure includes a first part and a second part, the first part of the gate structure is arranged along the side wall of the channel material pillar, and the second part of the gate structure extends along the second direction across a plurality of source lines and is connected to the first part; the plurality of drain structures are located on the channel material pillars and are connected to the channel material pillars. In the present invention, the gate structure is provided with a first part and a second part. The first part of the gate structure is arranged along the side wall of the channel material pillar, and the second part of the gate structure extends along the second direction across a plurality of source lines and is connected to the first part, which can avoid the influence of the non-centered channel position, thereby improving the electrical performance of the semiconductor device.

[0085] The above is only the preferred embodiment of the present invention and does not play any limiting role on the present invention. Any person skilled in the art, within the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification and other changes to the technical solution and technical content disclosed by the present invention, all of which belong to the content within the scope of the technical solution of the present invention and still fall within the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate; A plurality of source lines located on the substrate, the plurality of source lines extending in a first direction and arranged at intervals from each other in a second direction; A plurality of channel material pillars located on the plurality of source lines and connected to the source lines; A plurality of gate structures, the gate structure including a first part and a second part, the first part of the gate structure being disposed along the sidewall of the channel material pillar, and the second part of the gate structure extending in the second direction across a plurality of the source lines and connecting the first part; A plurality of drain structures located on the channel material pillars and connected to the channel material pillars; 2. The semiconductor device according to claim 1, wherein Along the first direction, the first part of the gate structure has a first dimension, the second part of the gate structure has a second dimension, the channel material pillar has a third dimension, and the first dimension is greater than the second dimension, and the second dimension is greater than or equal to the third dimension; 3. The semiconductor device according to claim 1, wherein, The first part of the gate structure and the second part of the gate structure are integrally formed, and the midlines of the first part of the gate structure and the second part of the gate structure do not overlap along the second direction; 4. The semiconductor device according to claim 1, wherein, The first part of the gate structure is annular, and the second part of the gate structure is strip-shaped; 5. The semiconductor device according to claim 1, characterized in that, The plurality of channel material pillars are distributed in a matrix array, and the plurality of channel material pillars are arranged in a plurality of rows extending in the first direction and a plurality of columns extending in the second direction, and the second part of the gate structure connects the channel material pillars in the same column; 6. The semiconductor device according to claim 5, wherein, The drain structure is connected to a plurality of adjacent channel material pillars in the same row; 7. The semiconductor device according to claim 5, characterized in that, The source line is connected to adjacent multiple rows of the channel material pillars; 8. The semiconductor device according to claim 1, wherein, The plurality of channel material pillars are distributed in a staggered array, and two adjacent columns of the channel material pillars are staggered in the second direction on different source lines; 9. The semiconductor device according to claim 8, wherein, Two adjacent columns of the channel material pillars are staggered on both sides of the second part of the gate structure.

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