Trench gate silicon carbide VDMOS of deep base region
Through the deep-base trench gate silicon carbide VDMOS structure, combined with the N-type homogeneous layer and P-type base region design, the current concentration and gate unreliability of silicon carbide power devices are solved, and high reliability and low on-resistance are achieved.
Patent Information
- Application Number
- CN202422131464.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-07-08
- Estimated Expiration
- 2034-08-30
AI Technical Summary
The existing silicon carbide power devices have internal current concentration, resulting in the problem of unreliability of the gate, and it is difficult to achieve low on-resistance under high withstand voltage conditions.
Using a deep-base trench gate silicon carbide VDMOS structure, an N-type homogeneous layer is constructed under the P-type base region of the device, and a distance of P-type base region thickness is set at the bottom of the gate dielectric layer. Combined with the high doping concentration of the N-type homogeneous layer, the current concentration is suppressed and the electric field distribution is improved.
It effectively suppresses the concentration of electric field at the corner of the device trench gate, improves the reliability of the device, and reduces the on-resistance, achieving the lateral distribution of current and the uniformity of thermal distribution.
Smart Images
Figure CN223080390U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to a trench-gate silicon carbide VDMOS with a deep base region. Background Art
[0002] Silicon carbide MOSFET is a typical representative of silicon carbide power devices and has a wide range of applications in fields such as electric vehicles, aerospace, and power conversion. The device has achieved good characteristics within 1200V and has completed the replacement of silicon MOSFET and IGBT within 1200V. With the improvement of the device's breakdown voltage and the reduction of on-resistance, achieving high reliability and low on-resistance under high breakdown voltage has become a new requirement for the development of device technology; however, the existing silicon carbide power devices still have the technical problem of internal current concentration, resulting in unreliable gates. Summary of the Utility Model
[0003] The technical problem to be solved by the utility model is to provide a trench-gate silicon carbide VDMOS with a deep base region, which improves the gate reliability of the device, reduces the internal current concentration problem of the device, and achieves both low on-resistance and high reliability.
[0004] The utility model is realized as follows: A trench-gate silicon carbide VDMOS with a deep base region, comprising:
[0005] A silicon carbide substrate,
[0006] A first drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate;
[0007] A current-sharing layer, the lower side of which is connected to the upper side of the first drift layer;
[0008] A second drift layer, the lower side of which is connected to the upper side of the current-sharing layer;
[0009] A base region, the lower side of which is connected to the upper side of the current-sharing layer, the inner side of which is connected to the outer side of the second drift layer, and a P-type source region is provided in the base region;
[0010] A P-type well region, the lower side of which is connected to the upper side of the base region and the upper side of the second drift layer;
[0011] An N-type source region, the lower side of which is connected to the upper side of the P-type well region;
[0012] A gate dielectric layer, the lower side of which is connected to the upper side of the second drift layer, the outer side of which is connected to the inner side of the P-type well region and the inner side of the N-type source region, and a trench is provided in the gate dielectric layer;
[0013] A gate metal layer, which is provided in the trench;
[0014] A source metal layer, the source metal layer is respectively connected to a P-type source region, a P-type well region, and an N-type source region;
[0015] And, a drain metal layer, the drain metal layer is connected to the lower side of the silicon carbide substrate.
[0016] The advantages of the present utility model are as follows:
[0017] First, the device adopts a deep-base trench-gate VDMOS device structure, and effectively suppresses the reliability problems caused by the electric field concentration at the corner of the trench gate of the silicon carbide VDMOS device through the deep-base structure;
[0018] Second, an N-type current-sharing layer is constructed below the P-type base region of the device. There is a distance equal to the thickness of the P-type base region at the bottom of the gate dielectric in the N-type current-sharing layer, which does not affect the protection of the gate dielectric by the P-type base region of the device;
[0019] Third, the N-type current-sharing layer has a high doping concentration, which can effectively suppress the depth of the space charge region formed by the P-type base region and the N-type drift layer in the direction of the drain of the device, and avoid the influence of the deep base region on the on-resistance of the device;
[0020] Fourth, the N-type current-sharing layer can realize the lateral distribution of the current below the gate structure, thereby reducing the overall on-resistance of the device, and at the same time suppressing the concentration of internal heat generation of the device caused by current concentration, so that the heat distribution is uniform;
[0021] Fifth, the distance between the deep well and the corner of the gate dielectric layer of the device does not affect the on-resistance of the device, that is, the N-type drift layer above the N-type current-sharing layer is compressed by the gate to form a space charge region during the conduction of the device, so that this part of the conduction channel is not affected by the P-type base region. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] The present utility model will be further described below with reference to the accompanying drawings in conjunction with embodiments.
[0023] Figure 1 FIG. is a schematic diagram of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model.
[0024] Figure 2 FIG. is a flowchart of a manufacturing method of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model.
[0025] Figure 3 FIG. is a process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 1 .
[0026] Figure 4 FIG. is a process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 2 .
[0027] Figure 5 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 3 。
[0028] Figure 6 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 4 。
[0029] Figure 7 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 5 。
[0030] Figure 8 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 6 。
[0031] Figure 9 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 7 。
[0032] Figure 10 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 8 。
[0033] Figure 11 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 9 。
[0034] Figure 12 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 10 。
[0035] Figure 13 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 10 One.
[0036] Figure 14 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 10 Two.
[0037] Figure 15 Process cross-section of a trench-gate silicon carbide VDMOS with a deep base region of the present utility model Figure 10 Three. Specific embodiments
[0038] To facilitate an understanding of the present application, the present application will be described more fully hereinafter with reference to the accompanying drawings. Embodiments of the present application are shown in the drawings. However, the present application may be embodied in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided so that the disclosure of the present application will be thorough and complete.
[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terms used in the description of this application herein are for the purpose of describing particular embodiments only and are not intended to limit this application.
[0040] It should be understood that when an element or layer is referred to as being "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on", "in contact with", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or portions, these elements, components, regions, layers, doping types and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or portion from another element, component, region, layer, doping type or portion. Thus, a first element, component, region, layer, doping type or portion discussed below may be denoted as a second element, component, region, layer or portion without departing from the teachings of the present invention.
[0041] Spatial relationship terms such as "under", "below", "beneath", "underneath", "above", "over", etc. may be used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "over" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an orientation of above and below. In addition, the device may also include additional orientations (such as, rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.
[0042] As used herein, the singular forms "a", "an" and "the" may also include the plural forms unless the context clearly dictates otherwise. It should also be understood that the terms "comprises / comprising" or "has / including" etc. specify the presence of the stated features, integers, steps, operations, components, parts or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the related listed items.
[0043] As Figure 1 shown, an embodiment of the present application provides a trench-gate silicon carbide VDMOS with a deep base region, including:
[0044] A silicon carbide substrate 101,
[0045] A first drift layer 102, the lower side of the first drift layer 102 being connected to the upper side of the silicon carbide substrate 101;
[0046] A current-sharing layer 103, the lower side of the current-sharing layer 103 being connected to the upper side of the first drift layer 102;
[0047] A second drift layer 104, the lower side of the second drift layer 104 being connected to the upper side of the current-sharing layer 103;
[0048] A base region 105, the lower side of the base region 105 being connected to the upper side of the current-sharing layer 103, the inner side of the base region 105 being connected to the outer side of the second drift layer 104, and a P-type source region 1051 being provided in the base region 105;
[0049] A P-type well region 106, the lower side of the P-type well region 106 being connected to the upper side of the base region 105 and the upper side of the second drift layer 104;
[0050] An N-type source region 107, the lower side of the N-type source region 107 being connected to the upper side of the P-type well region 106;
[0051] A gate dielectric layer 108, the lower side of the gate dielectric layer 108 being connected to the upper side of the second drift layer 104, the outer side of the gate dielectric layer 108 being connected to the inner side of the P-type well region 106 and the inner side of the N-type source region 107, and a trench 1081 being provided in the gate dielectric layer 108;
[0052] A gate metal layer 109, the gate metal layer 109 being disposed in the trench 1081;
[0053] A source metal layer 110, the source metal layer 110 being connected to the P-type source region 1051, the P-type well region 106 and the N-type source region 107 respectively;
[0054] And, a drain metal layer 111, the drain metal layer 111 being connected to the lower side surface of the silicon carbide substrate 101.
[0055] As Figures 2 to 15 shown, the method for manufacturing the above-mentioned silicon carbide VDMOS includes the following steps:
[0056] Step 1: Deposit metal on the lower side surface of the silicon carbide substrate 101 to form a drain metal layer 111, and epitaxially grow on the upper side surface of the silicon carbide substrate 101 to form a drift region a;
[0057] Step 2: Perform ion implantation on the drift region a to form a first drift layer 102, a current sharing layer 103, and a second drift layer 104, and the ion implantation energy is 500 - 600 kev;
[0058] Step 3: Form a blocking layer b on the second drift layer 104, etch the blocking layer b to form a through hole, perform ion implantation on the second drift layer 104, and form a base region 105 in the second drift layer 104, the lower side surface of the base region 105 being connected to the current sharing layer 103, and the ion implantation energy is 300 - 500 kev;
[0059] Step 4: Remove the original blocking layer b, reform the blocking layer b, etch the blocking layer b to form a through hole, perform ion implantation on the second drift layer 104, and form a P-type source region 1051 on the base region 105, and the ion implantation energy is 300 - 400 kev;
[0060] Step 5: Remove the original blocking layer b, reform the blocking layer b, etch the blocking layer b to form a through hole, perform ion implantation on the second drift layer 104, and form a P-type well region 106 in the second drift layer 104, and the ion implantation energy is 200 - 300 kev;
[0061] Step 6: Remove the original blocking layer b, reform the blocking layer b, etch the blocking layer b to form a through hole, perform ion implantation on the second drift layer 104, and form an N-type source region 107 in the second drift layer 104, and the ion implantation energy is 100 - 200 kev;
[0062] Step 7: Remove the original blocking layer b, form the blocking layer b, etch the blocking layer b to form a through hole, etch the second drift layer 104 and the P-type well region 106 to form a groove 112, and perform dry oxidation in the groove 112 to form a gate dielectric layer 108, and a groove 1081 is provided in the gate dielectric layer 108;
[0063] Step 8: Remove the original blocking layer b, form the blocking layer b, etch the blocking layer b to form a through hole, deposit metal, and form a gate metal layer 109;
[0064] Step 9: Remove the original barrier layer b, reform the barrier layer b, etch the barrier layer b to form a through hole, etch the second drift layer 104 with an etching depth of 900 nm, deposit metal, and form the first source metal region 1101;
[0065] Step 10: Remove the original barrier layer b, reform the barrier layer b, etch the barrier layer b to form a through hole, etch the second drift layer 104 with an etching depth of 300 nm, deposit metal, and form the second source metal region 1102; The source metal layer 110 includes the first source metal layer 1101 and the second source metal region 1102. Remove the barrier layer b to complete the preparation.
[0066] The doping concentration of the silicon carbide substrate 101 is 5e18 cm -3 , the doping concentrations of the first drift layer 102 and the second drift layer 104 are 2e17 cm -3 , the doping concentration of the current sharing layer 103 is 1e18 cm -3 , the doping concentration of the base region 105 is 1e18 cm -3 , the doping concentration of the P-type source region 1051 is 4e19 cm -3 , the doping concentration of the P-type well region 106 is 5e17 cm -3 , the doping concentration of the N-type source region 107 is 8e18 cm -3 , the silicon carbide substrate 101, the drift layer 102, and the current sharing layer 103 are all N-type, the base region 105 is P-type, the thickness of the current sharing layer 103 is 300 nm, the width L1 of the second drift layer 104 is 1 μm - 1.5 μm, the width L2 of the gate dielectric layer 108 is 600 nm - 1100 nm; The thickness of the P-type base region 105 is 600 nm, the thickness of the P-type source region 1051 is 300 nm, the thickness of the P-type well region 106 is 300 nm, the thickness of the N-type source region 107 is 300 nm, the sidewall and bottom thickness of the gate dielectric layer 108 is 30 nm, the thickness of the N-type current sharing layer 103 is 300 nm, the thickness from the top of the source metal layer 110 to the top of the N-type source region 107 is 300 nm, the device breakdown voltage is 1200 - 3000 V, and the distance between the P-type base region 105 and the nearest gate corner is controlled within 200 nm;
[0067] The concentration of the N-type silicon carbide substrate 101 is for forming a low-resistance ohmic contact with the drain metal layer 111 to reduce the on-resistance of the device. Its thickness is for ensuring support during device epitaxy and improving process stability. The thickness and concentration of the N-type current-sharing layer 103 are for ensuring the internal current-sharing effect while reducing the impact on the breakdown voltage of the device. The doping concentration and thickness design of the P-type well region 106 are for ensuring the gate control ability of the device for the P-type well region 106. The doping concentrations of the first drift layer 102 and the second drift layer 104 are for achieving a trade-off between the breakdown voltage and on-resistance of the device. The P-type source region 1051 and the N-type source region 107 are for achieving an ohmic contact with the source metal layer 110. The thickness of the gate dielectric layer 108 is a trade-off between the gate control ability and gate reliability of the device.
[0068] The base region 105 of the device and the second drift layer 104 above the N-type current-sharing layer 103 form a lateral space charge region. The distribution of this space charge region covers the corner of the device gate dielectric layer 108, achieving the effect of protecting the dielectric at the corner of the device gate. The lateral distance from the P-type base region 105 to the corner of the gate and the device gate width are considered in view of the influence of the space charge region in the second drift layer 104 above the N-type current-sharing layer 103 on its on-resistance, so as to avoid the influence of this structure on the on-resistance of the device.
[0069] An N-type current-sharing layer 103 is constructed below the P-type base region 105 of the device. In addition to the functions of current-sharing and suppressing current concentration, there is a distance equal to the thickness of the P-type base region 105 between the bottom of the device gate dielectric layer 108 and the N-type current-sharing layer 103, which does not affect the protection of the gate dielectric layer 108 by the P-type base region 105 of the device. The N-type current-sharing layer 103 has a high doping concentration, which can effectively suppress the depth of the space charge region formed by the P-type base region 105 and the first drift layer 102 in the direction of the device drain, avoiding the influence of the deep base region 105 on the on-resistance of the device.
[0070] Although the specific embodiments of the present invention have been described above, those skilled in the art should understand that the specific embodiments we described are illustrative rather than used to limit the scope of the present invention. Equivalent modifications and variations made by those skilled in the art in accordance with the spirit of the present invention should all be covered by the scope protected by the claims of the present invention.
Claims
1. A trench-gate silicon carbide VDMOS with a deep base region, characterized in that, Comprising: A silicon carbide substrate, A first drift layer, the lower side of which is connected to the upper side of the silicon carbide substrate; A current-sharing layer, the lower side of which is connected to the upper side of the first drift layer; A second drift layer, the lower side of which is connected to the upper side of the current-sharing layer; A base region, the lower side of which is connected to the upper side of the current-sharing layer, the inner side of which is connected to the outer side of the second drift layer, and a P-type source region is provided in the base region; A P-type well region, the lower side of which is connected to the upper side of the base region and the upper side of the second drift layer; An N-type source region, the lower side of which is connected to the upper side of the P-type well region; A gate dielectric layer, the lower side of which is connected to the upper side of the second drift layer, the outer side of which is connected to the inner side of the P-type well region and the inner side of the N-type source region, and a trench is provided in the gate dielectric layer; A gate metal layer provided in the trench; A source metal layer that is respectively connected to the P-type source region, the P-type well region, and the N-type source region; And a drain metal layer connected to the lower side of the silicon carbide substrate.
2. The trench-gate silicon carbide VDMOS with a deep base region as claimed in claim 1, wherein, The silicon carbide substrate, the drift layer, and the current-sharing layer are all N-type, and the base region is P-type.
3. The trench-gate silicon carbide VDMOS with a deep base region as claimed in claim 1, wherein The thickness of the current-sharing layer is 300 nm.
4. The trench-gate silicon carbide VDMOS with a deep base region according to claim 1, wherein, The width of the second drift layer is 1 μm - 1.5 μm, and the width of the gate dielectric layer is 600 nm - 1100 nm.
5. The trench-gate silicon carbide VDMOS with a deep base region according to claim 1, wherein, The thickness of the base region is 600 nm, and the thickness of the P-type source region is 300 nm.