MOS transistor for improving reverse recovery speed

Abstract

The utility model relates to the technical field of MOS semiconductors, and discloses an MOS transistor for improving reverse recovery speed, which comprises an MOS transistor consisting of a plurality of VDMOS cells, and is characterized in that each VDMOS cell comprises a drain electrode, a semiconductor epitaxial layer, a metal source electrode and a grid electrode; the semiconductor epitaxial layer comprises a sinking layer, a diffusion layer, a suppression P body region, a P well layer and an N well layer; the N well layer and the diffusion layer are separated through the P well layer; the P well layer comprises a lightly doped P well layer I, a lightly doped P well layer II and a heavily doped P well layer I; the N-well layer comprises a lightly doped N-well layer and a heavily doped N-well layer; only the heavily-doped N-well layer in the N-well layer is in ohmic short circuit with the metal source electrode. According to the utility model, the suppression P body region is in ohmic short circuit with the drain electrode, so that in the stage of reverse recovery current decline, due to the intervention of the electric field of the suppression P body region, the decline speed of the charge of the diffusion layer is increased, the reverse recovery current is rapidly attenuated, and the reverse recovery speed is accelerated.

Description

Technical Field

[0001] The utility model relates to the technical field of MOS semiconductors, and more specifically, to a MOS transistor for improving the reverse recovery speed. Background Art

[0002] MOS transistors are widely used in various power electronic systems because of their advantages such as fast switching speed, low switching loss, easy gate driving, small driving power, high input impedance, good frequency response, and being conducive to large-scale integration.

[0003] A prior patent discloses a depletion-type VDMOS (publication number CN202758891U), wherein the depletion-type VDMOS includes: a doped substrate of a first doping type; an epitaxial layer of the first doping type formed on one surface of the substrate; at least two deep wells of a second doping type formed in the epitaxial layer; and two ion-implanted channel regions of the first doping type formed on both sides of each of the deep wells. Among them, the length range of the channel regions is 1μm to 3μm, and the channel regions are separated from each other. In the technology disclosed in this patent, during the operation of the device, charge cross-diffusion and mutual interference will occur between its own MOS cells, thereby increasing the on-resistance of the MOS transistor. And when the reverse recovery current decreases, the MOS transistor is extremely prone to device damage due to current overshoot. Summary of the Invention

[0004] The main technical problem to be solved by the utility model is to provide a MOS transistor for improving the reverse recovery speed, which solves the problems in the above background art.

[0005] To solve the above technical problem, according to one aspect of the utility model, more specifically, a MOS transistor for improving the reverse recovery speed includes a MOS transistor composed of a plurality of VDMOS cells, wherein each VDMOS cell includes a drain, a semiconductor epitaxial layer, a metal source, and a gate;

[0006] The semiconductor epitaxial layer includes a sinker layer, a diffusion layer, a suppression P body region, a P well layer, and an N well layer; the N well layer is blocked from the diffusion layer by the P well layer;

[0007] The P well layer includes a lightly doped P well layer 1, a lightly doped P well layer 2, and a heavily doped P well layer 1;

[0008] The N well layer includes a lightly doped N well layer and a heavily doped N well layer; among them, only the heavily doped N well layer in the N well layer is ohmically short-circuited with the metal source;

[0009] When a positive gate voltage is applied to the gate, a reverse depletion layer is formed in the JFET region inside the drift layer, where the JFET region is located between two adjacent lightly doped P-well layers I.

[0010] Furthermore, the suppressing P-body region and the heavily doped P-well layer I are ion-implanted with a high concentration of boron ions; the lightly doped P-well layer II is ion-implanted with a low concentration of boron ions.

[0011] Furthermore, the drift layer, the first diffusion layer, and the second diffusion layer are ion-implanted with a low concentration of phosphorus ions; the heavily doped N-well layer and the suppression layer are ion-implanted with a high concentration of phosphorus ions.

[0012] Furthermore, the heavily doped P-well layer I, the suppression layer, and the suppressing P-body region between adjacent VDMOS cells are integrated as a whole.

[0013] Furthermore, the suppressing P-body region is ohmically shorted to the drain, and the heavily doped P-well layer I is ohmically shorted to the metal source.

[0014] Furthermore, the second diffusion layer is located between two adjacent suppressing P-body regions.

[0015] Furthermore, a gate oxide layer is deposited between the surface of the gate, the metal source, and the semiconductor epitaxial layer.

[0016] Furthermore, the N-well layer is divided into two equal parts by implanting different concentrations of phosphorus elements, and the lightly doped N-well layer suppresses the diffusion of free charges into the lightly doped N-well layer.

[0017] Furthermore, when the gate voltage is applied to the gate, the charges inside the lightly doped P-well layer I gather towards the gate under the intervention of the gate electric field and form a charge channel.

[0018] Furthermore, the charge channel connects the diffusion layer and the N-well layer, and the drain and the metal source are restored to the conducting state.

[0019] The beneficial effects of the MOS transistor for improving the reverse recovery speed of the present utility model are as follows:

[0020] 1. By commonly providing the suppressing P-body region between adjacent VDMOS cells, the present utility model can avoid the mutual interference between cells when the MOS transistor is in the conducting state.

[0021] 2. By ohmically shorting the suppressing P-body region to the drain, in the stage of the reverse recovery current decline, due to the intervention of the electric field of the suppressing P-body region itself, the decline speed of the charges in the diffusion layer increases, and the reverse recovery current decays rapidly, thereby accelerating the reverse recovery speed.

[0022] 3. By dividing the diffusion layer into multiple levels, the present utility model can avoid the gate electric field from breaking down the semiconductor epitaxial layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present utility model will be further described in detail below with reference to the drawings and specific implementation methods.

[0024] Figure 1 is a schematic structural diagram of the MOS transistor in the present utility model;

[0025] Figure 2 is a schematic structural diagram of a single VDMOS cell in the present utility model.

[0026] In the figure: 1, drain; 2, substrate layer; 3, metal source; 4, gate; 5, gate oxide layer; 6, lightly doped P-well layer 1; 7, lightly doped P-well layer 2; 8, heavily doped P-well layer 1; 9, diffusion layer; 10, suppression P body region; 11, lightly doped N-well layer; 12, heavily doped N-well layer; 901, drift layer; 902, suppression layer; 903, diffusion layer 1; 904, diffusion layer 2. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0027] The present utility model will be described in detail below with reference to the drawings and embodiments. It should be noted that, without conflict, the embodiments in the present application and the features in the embodiments can be combined with each other.

[0028] As Figure 1-2 shown, according to one aspect of the present utility model, a MOS transistor for improving the reverse recovery speed is provided, including a MOS transistor composed of a plurality of VDMOS cells, wherein the VDMOS cell includes a drain 1, a semiconductor epitaxial layer, a metal source 3, and a gate 4, and the semiconductor epitaxial layer includes a sink layer 2, a diffusion layer 9, a suppression P body region 10, a P-well layer, and an N-well layer; the N-well layer and the diffusion layer 9 are blocked by the P-well layer 10 (as Figure 1 shown), after the gate 4 is connected to the gate voltage, a charge channel will be formed inside the lightly doped P-well layer 1, and the charge channel connects the N-well layer and the diffusion layer 9, so that a path is formed between the drain 1 and the metal source 3.

[0029] The P-well layer includes a lightly doped P-well layer 1, a lightly doped P-well layer 2, and a heavily doped P-well layer 1, and the N-well layer includes a lightly doped N-well layer 11 and a heavily doped N-well layer 12; wherein, only the heavily doped N-well layer 12 in the N-well layer is ohmically short-circuited with the metal source 3 (as Figure 1 shown), and the heavily doped P-well layer 1 can avoid the charge mutual conduction phenomenon between the N-well layers of adjacent VDMOS cells, thereby improving the conduction stability of the MOS transistor.

[0030] In this embodiment, the doping concentration of the suppression P body region 10 is 6.3 - 8.7×10 18 mol / cm 3 ;

[0031] The doping concentration of the lightly doped P well layer two 7 is 5.7 - 7×10 16 mol / cm 3 ;

[0032] The doping concentration of the heavily doped P well layer one 8 is 2 - 3.5×10 18 mol / cm 3 ;

[0033] The doping concentration of the drift layer 901 is 7.4 - 9×10 16 mol / cm 3 ;

[0034] The doping concentration of the diffusion layer one 903 is 4.3 - 7×10 16 mol / cm 3 ;

[0035] The doping concentration of the diffusion layer two 904 is 1.8 - 3.5×10 16 mol / cm 3 ;

[0036] The doping concentrations of the heavily doped N well layer 12 and the suppression layer 902 are both 4 - 7×10 18 mol / cm 3 .

[0037] In this embodiment, the heavily doped P well layer one 8, the suppression layer 902, and the suppression P body region 10 between adjacent VDMOS cells are of the same body. The suppression P body region 10 is short-circuited to the drain 1 ohm, and the heavily doped P well layer one 8 is short-circuited to the metal source 3 ohm. By short-circuiting the suppression P body region 10 to the drain 1 ohm, in the reverse recovery current decline stage, due to the intervention of the electric field of the suppression P body region 10 itself, the decline speed of the charge in the diffusion layer 9 increases, and the reverse recovery current decays rapidly, thus accelerating the reverse recovery speed.

[0038] In this embodiment, the second diffusion layer 902 is located between two adjacent P suppression regions 10. A gate oxide layer 5 is deposited between the surface of the gate 4, the metal source electrode 3, and the semiconductor epitaxial layer. The gate oxide layer 5 is used to ensure the formation of the gate electric field and prevent charge carriers from entering the gate 4. The N-well layer is formed by implanting phosphorus atoms with different concentrations and divided into two equal parts. The lightly doped N-well layer 11 suppresses the diffusion of free charge carriers into the lightly doped N-well layer 11. By designing the N-well layer to have multiple levels, the doping concentration of the lightly doped N-well layer 11 is relatively low, which results in a lower charge conduction property of the lightly doped N-well layer 11, thus avoiding the phenomenon of charge parasitism inside the N-well layer.

[0039] In this embodiment, when a positive gate voltage is applied to the gate 4, a reverse depletion layer is formed in the JFET region inside the drift layer 901, and the JFET region is located between two adjacent lightly doped P-well layers 6. When the gate voltage is applied to the gate 4, the charge carriers inside the lightly doped P-well layer 6 gather towards the gate 4 under the intervention of the gate electric field and form a charge channel. The charge channel connects the diffusion layer 9 and the N-well layer, and the drain 1 and the metal source electrode 3 resume the conducting state. The characteristics of the JFET region depend on the action of the gate electric field, and the conductivity of the JFET region can be adjusted by controlling the gate voltage.

[0040] Of course, the above description is not a limitation of the present invention, and the present invention is not limited to the above examples. Changes, modifications, additions, or substitutions made by those of ordinary skill in the art within the scope of the essence of the present invention also fall within the protection scope of the present invention.

Claims

1. A MOS transistor for improving reverse recovery speed, characterized in that, It includes a MOS transistor composed of a number of VDMOS cells, where each VDMOS cell includes a drain (1), a semiconductor epitaxial layer, a metal source (3), and a gate (4); The semiconductor epitaxial layer includes a sinker layer (2), a diffusion layer (9), a suppression P body region (10), a P well layer, and an N well layer; the N well layer is blocked from the diffusion layer (9) by the P well layer; The P well layer includes a lightly doped P well layer 1 (6), a lightly doped P well layer 2 (7), and a heavily doped P well layer 1 (8); The N well layer includes a lightly doped N well layer (11) and a heavily doped N well layer (12); among them, only the heavily doped N well layer (12) in the N well layer is ohmically shorted to the metal source (3); The diffusion layer (9) includes a drift layer (901), a suppression layer (902), a diffusion layer 1 (903), and a diffusion layer 2 (904); When a positive gate voltage is applied to the gate (4), a reverse depletion layer is formed in the JFET region inside the drift layer (901), where the JFET region is located between two adjacent lightly doped P well layers 1 (6).

2. The MOS transistor for improving the reverse recovery speed according to claim 1, wherein: The suppression P body region (10) and the heavily doped P well layer 1 (8) are ion-implanted with a high concentration of boron ions; The lightly doped P well layer 2 (7) is ion-implanted with a low concentration of boron ions.

3. The MOS transistor for enhancing reverse recovery speed according to claim 1, wherein: The drift layer (901), the diffusion layer 1 (903), and the diffusion layer 2 (904) are ion-implanted with a low concentration of phosphorus ions; The heavily doped N well layer (12) and the suppression layer (902) are ion-implanted with a high concentration of phosphorus ions.

4. The MOS transistor for improving reverse recovery speed according to claim 1, wherein: The heavily doped P well layer 1 (8), the suppression layer (902), and the suppression P body region (10) between adjacent VDMOS cells are of the same body.

5. The MOS transistor for enhancing reverse recovery speed according to claim 4, wherein: The suppression P body region (10) is ohmically shorted to the drain (1), and the heavily doped P well layer 1 (8) is ohmically shorted to the metal source (3).

6. The MOS transistor for improving reverse recovery speed according to claim 1, wherein: The diffusion layer 2 (904) is located between two adjacent suppression P body regions (10).

7. The MOS transistor for enhancing reverse recovery speed according to claim 1, characterized in that: A gate oxide layer (5) is deposited between the surface of the gate (4), the metal source (3), and the semiconductor epitaxial layer.

8. The MOS transistor for enhancing reverse recovery speed according to claim 1, wherein: The N well layer is divided into two equal parts by implanting different concentrations of phosphorus elements, where the lightly doped N well layer (11) suppresses the diffusion of free charges into the lightly doped N well layer (11).

9. The MOS transistor for improving reverse recovery speed according to claim 1, wherein: When the gate (4) is under the application of a gate voltage, the charges inside the lightly doped P well layer 1 (6) gather towards the gate (4) under the intervention of the gate electric field and form a charge channel.

10. The MOS transistor for enhancing reverse recovery speed according to claim 9, wherein: The charge channel connects the diffusion layer (9) and the N well layer, and the drain (1) and the metal source (3) resume the conducting state.

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