Terminal structure of semiconductor device and semiconductor device

Abstract

The utility model relates to the field of semiconductors, and discloses a terminal structure of a semiconductor device and the semiconductor device.The terminal structure of the semiconductor device comprises a main junction which comprises a first surface and an opposite second surface, and the first surface is in contact with an epitaxial layer; the main junctions and the cut-off rings are arranged at intervals; the junction terminal expansion structure is arranged between the main junction and the cut-off ring and is connected with the main junction, the junction terminal expansion structure comprises a first expansion part and a second expansion part in the direction from the main junction to the cut-off ring, a fourth surface corresponding to the first expansion part is coplanar with the second surface, and a fourth surface corresponding to the second expansion part is in a step shape with a gradually decreasing trend. The junction terminal structure is used for solving the problems that an existing terminal structure needs to be long and miniaturization packaging cannot be achieved, electric charge concentration changes in the direction from a main junction to a cut-off ring are gradually and evenly decreased in a gradient mode, the phenomenon of electric field concentration can be effectively relieved, the reverse blocking capacity of a power device is improved, and the length of the junction terminal expansion structure is reduced.

Description

Technical Field

[0001] This application belongs to the field of semiconductors, and particularly relates to a terminal structure of a semiconductor device and a semiconductor device. Background Art

[0002] The terminal structure of a semiconductor device includes various structural elements such as P-N junctions, metal-semiconductor contacts, MOS junctions, PIN junctions, etc., as well as special structures designed to improve device performance such as field limiting rings, trenches, junction termination extension structures, etc. The terminal structure can realize the gradual release of electric field peaks, reduce the local electric field, and improve the device reliability. The design of the terminal structure of a device has a significant impact on the improvement of breakdown voltage parameters and cost.

[0003] Among them, the junction termination extension (JTE) is to set a lightly doped P-type region outside the main junction (such as a P-N junction), and by adjusting the doping concentration and distribution of this region, additional charges are introduced to modulate the semiconductor surface electric field, thereby reducing the curvature effect at the main junction boundary and improving the breakdown voltage capability of the device.

[0004] However, in order to achieve a high blocking voltage, the existing terminal structure needs to be long and has a large manufacturing area, and miniaturized packaging cannot be achieved. Summary of the Utility Model

[0005] Embodiments of this application provide a terminal structure of a semiconductor device and a semiconductor device, which can improve the breakdown voltage capability of the terminal structure and reduce the length of the terminal structure.

[0006] On the one hand, embodiments of this application provide a terminal structure of a semiconductor device, including: a substrate; an epitaxial layer formed on the substrate; a main junction formed on a side of the epitaxial layer facing away from the substrate, the main junction including a first surface and an opposite second surface, the first surface being in contact with the epitaxial layer; a cut-off ring formed on the side of the epitaxial layer facing away from the substrate, the main junction and the cut-off ring being spaced apart; a junction termination extension structure formed on the side of the epitaxial layer facing away from the substrate, the junction termination extension structure being disposed between the main junction and the cut-off ring and connected to the main junction, the junction termination extension structure including a third surface and an opposite fourth surface, the third surface being in contact with the epitaxial layer, from the main junction to the cut-off ring direction, the junction termination extension structure includes a first extension part and a second extension part, the fourth surface corresponding to the first extension part is coplanar with the second surface, from the main junction to the cut-off ring direction, the fourth surface corresponding to the second extension part is in a stepped shape with a gradually decreasing trend.

[0007] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, the second extension part includes at least one stepped part, the stepped part is connected to the first extension part, and in the direction from the main junction to the cutoff ring, the fourth surface corresponding to the stepped part sequentially includes a ramp section and a flat section, the flat section is parallel to the second surface, and the included angle between the ramp section and the flat section is greater than 90 degrees and less than 180 degrees.

[0008] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, along the direction of the main junction and the cutoff ring, the length of the stepped part corresponding to the ramp section is less than the length of the stepped part corresponding to the flat section.

[0009] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, in the direction from the main junction to the cutoff ring, the second extension part sequentially includes a connected first stepped part and a second stepped part;

[0010] The fourth surface corresponding to the first stepped part sequentially includes a first ramp section and a first flat section, the first flat section is parallel to the second surface, and the included angle between the first ramp section and the first flat section is 135 degrees;

[0011] The fourth surface corresponding to the second stepped part sequentially includes a second ramp section and a second flat section, the second flat section is parallel to the second surface, and the included angle between the second ramp section and the second flat section is 135 degrees.

[0012] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, the surface of the epitaxial layer between the junction terminal extension structure and the cutoff ring facing away from the substrate is coplanar with the fourth surface corresponding to the second flat section.

[0013] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, the surface of the cutoff ring facing away from the substrate is coplanar with the fourth surface corresponding to the second flat section.

[0014] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, the third surface of the junction terminal extension structure is a flat surface and is parallel to the fourth surface corresponding to the first extension part.

[0015] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, the maximum distance between the third surface and the fourth surface of the junction terminal extension structure is less than the distance between the first surface and the second surface of the main junction.

[0016] According to the terminal structure of the semiconductor device provided by the embodiment of the present application, it further includes:

[0017] A dielectric layer is disposed on the side of the epitaxial layer facing away from the substrate. The dielectric layer covers a part of the main junction, the junction termination extension structure, the epitaxial layer between the junction termination extension structure and the cutoff ring, and the cutoff ring.

[0018] A source electrode is disposed on the side of the epitaxial layer facing away from the substrate. The source electrode is connected to the main junction.

[0019] A drain electrode is disposed on the side of the substrate facing away from the epitaxial layer.

[0020] On the other hand, an embodiment of the present application further provides a semiconductor device, including: a cell region and a terminal structure of the semiconductor device. The terminal structure of the semiconductor device is disposed at the edge of the cell region.

[0021] In the terminal structure of the semiconductor device and the semiconductor device according to the embodiment of the present application, a junction termination extension structure is disposed between the main junction and the cutoff ring. From the main junction to the cutoff ring direction, the junction termination extension structure includes a first extension part and a second extension part. The fourth surface corresponding to the first extension part is coplanar with the second surface of the main junction. The fourth surface corresponding to the second extension part is in a stepped shape with a gradually decreasing trend, realizing the change of the charge quantity concentration from the main junction to the cutoff ring direction, gradually decreasing uniformly in a gradient, which can effectively relieve the electric field concentration phenomenon, improve the reverse blocking ability of the power device, and reduce the length of the junction termination extension structure. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required to be used in the embodiments of the present application. For those of ordinary skill in the art, other drawings can also be obtained according to these drawings without creative efforts.

[0023] Figure 1 Shows a schematic structural diagram of a terminal structure of a semiconductor device provided by some embodiments of the present application;

[0024] Figure 2 Shows a schematic diagram of an exemplary junction termination extension structure;

[0025] Figure 3 Shows one of the schematic diagrams of a method for manufacturing a terminal structure of a semiconductor device provided by some embodiments of the present application;

[0026] Figure 4 Shows another schematic diagram of a method for manufacturing a terminal structure of a semiconductor device provided by some embodiments of the present application;

[0027] Figure 5 Shows a third schematic diagram of a method for manufacturing a terminal structure of a semiconductor device provided by some embodiments of the present application;

[0028] Figure 6 Figure 4 shows a schematic diagram of a method for preparing a terminal structure of a semiconductor device provided by some embodiments of the present application;

[0029] Figure 7 Figure 5 shows a schematic diagram of a method for preparing a terminal structure of a semiconductor device provided by some embodiments of the present application;

[0030] Figure 8 Figure shows a TCAD simulation diagram of a conventional field limiting ring terminal structure;

[0031] Figure 9 Figure shows a TCAD simulation diagram of a terminal structure provided by some embodiments of the present application;

[0032] Figure 10 Figure shows a comparison of breakdown voltages between a conventional field limiting ring terminal structure and the terminal structure of the present application.

[0033] Reference numerals:

[0034] 100: Junction terminal extension structure; 110: First extension part; 120: Second extension part; 130: Third surface; 131: Fourth surface; 121: First step part; 122: Second step part; 105: First ramp segment; 106: First straight segment; 107: Second ramp segment; 108: Second straight segment;

[0035] 200: Substrate; 201: Epitaxial layer; 202: Main junction; 205: Cut-off ring; 210: First surface; 211: Second surface. Detailed implementation manners

[0036] The features and exemplary embodiments of various aspects of the present application will be described in detail below. In order to make the objectives, technical solutions and advantages of the present application clearer and more understandable, the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, rather than limiting the present application. For those skilled in the art, the present application can be implemented without some of these specific details. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0037] It should be noted that in this article, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device comprising a series of elements not only includes those elements, but also includes other elements not expressly listed, or also includes elements inherent to such process, method, article or device. Without further limitation, an element defined by the statement "comprising..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the said element.

[0038] Power semiconductor devices are semiconductor devices for electric energy conversion and processing, such as diodes, field effect transistors, thyristors, etc. Their main feature is the ability to block high voltages, that is, the breakdown voltage or withstand voltage is one of the most important electrical parameters of power semiconductor devices. To obtain a larger breakdown voltage, a terminal structure is usually introduced at the end of the power semiconductor device. The terminal structure can achieve a gradual release of the electric field peak, reduce the local electric field and improve the device reliability. The design of the terminal structure of the device has a significant impact on the improvement of the withstand voltage parameter and the cost. The breakdown voltage of the terminal structure is mainly limited by the maximum electric field not exceeding the critical electric field Ec of the material itself. Therefore, the goal of the design of various terminals is to obtain as uniform an electric field distribution as possible to increase the overall breakdown voltage value. Common terminal structures include field plates, field limiting rings, junction termination extensions, bevel terminals, lateral variable doping, trenches, chamfered corners, etc., or composite terminals using the above technologies. The commonly used field limiting ring technology is to form one or more ring structures with the same type of doping near the main junction while forming the main junction on the substrate. The field limiting ring is used to reduce the high electric field caused by the curvature effect on the surface of the PN junction and at the same time expand the depletion region width to increase the breakdown voltage.

[0039] The bottom end of the common field limiting ring terminal structure is the drain of the device. An epitaxial layer is formed on the substrate, and ion implantation processes are sequentially performed on the surface of the epitaxial layer to form the main junction and the field limiting ring. Then, high-concentration N-type implantation is performed at the outermost end of the device to form a cut-off ring region, a dielectric layer is deposited to form a thick oxide layer region, and the oxide layer is etched to fabricate the source and drain. The field limiting ring forms multiple PN junctions by diffusion. By reasonably optimizing the number of field limiting rings and the spacing between field limiting rings, the withstand voltage of the terminal structure can be achieved. In theory, as the number of field rings increases, the withstand voltage of the terminal structure will increase. However, as the voltage increases, especially in the high-voltage field, a larger number of field limiting rings are required. Moreover, as the number increases, the change in the breakdown voltage may only be slightly changed, seriously occupying the chip area and resulting in high manufacturing costs, making it impossible to achieve miniaturized chip packaging.

[0040] In addition, the common field limiting ring terminal structure is the field plate technology. By using metal or polycrystalline that contacts the main junction to extend the depletion layer, the surface electric field distribution of the substrate is balanced to achieve the purpose of increasing the breakdown voltage. It is usually used in combination with the field limiting ring technology to effectively increase the breakdown voltage. There are mainly metal field plates, resistive field plates, ramp field plates, stepped field plates, etc. However, there will be a large electric field intensity at the end of the field plate, resulting in the inability to achieve a high breakdown voltage. The stepped field plate can reduce the surface electric field peak at the edge of the field plate, but the thickness of the oxide layer needs to be precisely controlled to avoid the peak electric field at the oxide layer step, which is difficult to implement and has a complex process. Moreover, the field plate is sensitive to interface charges.

[0041] In the field of high-voltage devices, when a higher blocking voltage needs to be achieved, if the conventional field limiting ring and field plate structures are used, the length of the terminal structure is longer, which means a larger manufacturing area, and miniaturized packaging cannot be achieved. Moreover, the design and process flow are complex, and the implementation cost is high. Therefore, reducing the length of the terminal structure as much as possible while achieving the breakdown voltage is crucial for reducing the chip area and cost.

[0042] To solve the problems of the existing technology, the embodiments of the present application provide a terminal structure of a semiconductor device and a semiconductor device. First, the terminal structure of the semiconductor device provided by the embodiments of the present application will be introduced below.

[0043] Figure 1 The structural schematic diagram of the terminal structure of the semiconductor device provided by some embodiments of the present application is shown. Figure 2 A schematic diagram of an exemplary junction terminal extension structure is shown.

[0044] As Figure 1 and Figure 2As shown in the figure, an embodiment of the present application provides a terminal structure of a semiconductor device, including: a substrate 200, an epitaxial layer 201, a main junction 202, a cut-off ring 205, and a junction termination extension structure 100. The epitaxial layer 201 is formed on the substrate 200; the main junction 202 is formed on a side of the epitaxial layer 201 facing away from the substrate 200. The main junction 202 includes a first surface 210 and an opposite second surface 211, and the first surface 210 is in contact with the epitaxial layer 201; the cut-off ring 205 is formed on a side of the epitaxial layer 201 facing away from the substrate 200, and the main junction 202 and the cut-off ring 205 are spaced apart; the junction termination extension structure 100 is formed on a side of the epitaxial layer 201 facing away from the substrate 200. The junction termination extension structure 100 is disposed between the main junction 202 and the cut-off ring 205 and is connected to the main junction 202. The junction termination extension structure 100 includes a third surface 130 and an opposite fourth surface 131, and the third surface 130 is in contact with the epitaxial layer 201. From the main junction 202 to the cut-off ring 205 direction, the junction termination extension structure 100 includes a first extension portion 110 and a second extension portion 120. The fourth surface 131 corresponding to the first extension portion 110 is coplanar with the second surface 211. From the main junction 202 to the cut-off ring 205 direction, the fourth surface 131 corresponding to the second extension portion 120 is in a stepped shape with a gradually decreasing trend.

[0045] The substrate 200 and the epitaxial layer 201 are made of semiconductor materials of a first conductivity type. The main junction 202 and the junction termination extension structure 100 are made of semiconductor materials of a second conductivity type. The cut-off ring 205 is a semiconductor material of the first conductivity type. Among them, the conductivity types of the semiconductor materials of the first conductivity type and the second conductivity type are different. For example, when the semiconductor material of the first conductivity type is a P-type semiconductor material, the semiconductor material of the second conductivity type is an N-type semiconductor material; when the semiconductor material of the first conductivity type is an N-type semiconductor material, the semiconductor material of the second conductivity type is a P-type semiconductor material. Among them, the doping concentration of the substrate 200 is greater than the doping concentration of the epitaxial layer 201.

[0046] In addition, the material of the substrate 200 may be silicon (Si), germanium (Ge), and compound semiconductors such as gallium arsenide (GaAs), etc. The main junction 202 is the core part of the terminal structure of the semiconductor device and is used to control the on-off of the current. The cut-off ring 205 is also called a field limiting ring or a field plate, and its function is to diffuse and dissipate the electric field to prevent the electric field from concentrating at the edge of the device, thereby improving the breakdown voltage of the device. The junction termination extension structure 100 is located between the main junction 202 and the cut-off ring 205 and plays a role in further dispersing the electric field and improving the edge breakdown voltage.

[0047] The junction terminal extension structure 100 includes a first extension part 110 and a second extension part 120. The fourth surface 131 of the first extension part 110 is coplanar with the second surface 211 of the main junction 202. That is, in the vertical direction, the first extension part 110 and the main junction 202 maintain the same height, which helps to maintain a smooth transition of the electric field. The second extension part 120 extends from the main junction 202 towards the cutoff ring 205, and its corresponding fourth surface 131 is in a stepped shape with a gradually decreasing trend, which can more effectively disperse and dissipate the electric field. Especially in the area near the cutoff ring 205, the electric field intensity is further dispersed through the change of the charge concentration, thereby improving the breakdown voltage capability of the device.

[0048] In addition, in the terminal structure of the semiconductor device in the embodiment of the present application, it further includes: a dielectric layer, a source electrode, and a drain electrode. The dielectric layer is disposed on the side of the epitaxial layer 201 facing away from the substrate 200, and the dielectric layer covers a part of the main junction 202, the junction terminal extension structure 100, the epitaxial layer 201 between the junction terminal extension structure 100 and the cutoff ring 205, and the cutoff ring 205; the source electrode is disposed on the side of the epitaxial layer 201 facing away from the substrate 200, and the source electrode is connected to the main junction 202; the drain electrode is disposed on the side of the substrate 200 facing away from the epitaxial layer 201.

[0049] The dielectric layer is disposed on the side of the epitaxial layer 201 facing away from the substrate 200, mainly playing the roles of insulation and protection. The dielectric layer is usually made of an oxide (such as silicon dioxide SiO2) or other high-K materials to improve the insulation performance and reduce the capacitance effect. The dielectric layer covering the junction terminal extension structure 100 follows the stepped shape of the junction terminal extension structure 100. Among them, a part of the main junction 202 is covered by the dielectric layer, and the other part is covered by the source electrode. The source electrode is an important electrode of the device. In a MOSFET, the source electrode is the injection end of electrons or holes. For an N-channel MOSFET, the source electrode is N-type doped; for a P-channel MOSFET, the source electrode is P-type doped. The drain electrode is another important electrode of the device. In a MOSFET, the drain electrode is the collection end of electrons or holes, and its doping type is the same as that of the source electrode but the area is larger.

[0050] As Figure 2 shown, in an embodiment of the present application, the second extension part 120 includes at least one stepped part. The stepped part is connected to the first extension part 110. Extending from the main junction 202 towards the cutoff ring 205, the fourth surface 131 corresponding to the stepped part sequentially includes a ramp section and a flat section. The flat section is parallel to the second surface 211, and the included angle between the ramp section and the flat section is greater than 90 degrees and less than 180 degrees.

[0051] For example, the second extension portion 120 includes a stepped portion. The intersection position of the ramp section with the first extension portion 110 and the straight section divides the junction terminal extension structure 100 into three regions with different charge concentration levels, and the charge concentration gradually decreases from the main junction 202 towards the cutoff ring 205. An angle greater than 90 degrees and less than 180 degrees is formed between the ramp section and the straight section, which helps to form a gradually changing electric field distribution on the ramp section and slow down the sharp change in the electric field intensity.

[0052] Continuing to refer to Figure 2 , in another embodiment of the present application, from the main junction 202 towards the cutoff ring 205, the second extension portion 120 sequentially includes a connected first stepped portion 121 and a second stepped portion 122; the fourth surface 131 corresponding to the first stepped portion 121 sequentially includes a first ramp section 105 and a first straight section 106, the first straight section 106 is parallel to the second surface 211, and the angle between the first ramp section 105 and the first straight section 106 is 135 degrees; the fourth surface 131 corresponding to the second stepped portion 122 sequentially includes a second ramp section 107 and a second straight section 108, the second straight section 108 is parallel to the second surface 211, and the angle between the second ramp section 107 and the second straight section 108 is 135 degrees.

[0053] To achieve the best matching effect of the stepped portion of the junction terminal extension structure, taking the terminal structure of a 1200V silicon carbide MOSFET device as an example, the number of steps, the step angle, and the etching depth all have an optimal state. For example: the number of steps is two, namely the first stepped portion 121 and the second stepped portion 122, the etching inclination angle is 135°, that is, the angle between the first ramp section 105 and the first straight section 106 is 135 degrees, and the angle between the second ramp section 107 and the second straight section 108 is 135 degrees. Compared with a right-angle etching angle of 90° between the ramp section and the straight section, the 135-degree angle can achieve the effect of gradually buffering the electric field and effectively slow down the electric field concentration effect at the corner of the ramp section and the straight section.

[0054] For example, the etching depth of the first straight section 106 relative to the second surface 211 can be 0.2um, and the etching depth of the second straight section 108 relative to the second surface 211 can be 0.3um.

[0055] In other embodiments of the present application, along the direction of the main junction 202 and the cutoff ring 205, the length of the stepped portion corresponding to the ramp section is less than the length of the stepped portion corresponding to the straight section.

[0056] For example, the first ramp segment 105 corresponds to the first terminal portion, the first straight segment 106 corresponds to the second terminal portion, the second ramp segment 107 corresponds to the third terminal portion, and the second straight segment 108 corresponds to the fourth terminal portion; the lengths of the first terminal portion and the third terminal portion may be the same, the length of the second terminal portion may be greater than the length of the fourth terminal portion, and the first terminal portion makes the transition between the first extended portion and the second extended portion slower, achieving the effect of a uniform decreasing charge concentration gradient. The third terminal portion makes the charge concentration gradients of the second terminal portion and the fourth terminal portion decrease uniformly.

[0057] Further, in an alternative embodiment of the present application, the third surface 130 of the junction termination extension structure 100 is a flat surface and is parallel to the fourth surface 131 corresponding to the first extended portion 110. That is to say, the third surface 130 may be parallel to the first surface 210.

[0058] Alternatively, a stepped structure corresponding to the stepped portion of the third surface 130 is provided on the fourth surface 131. The stepped structure may be the same as the stepped portion of the third surface 130, and along the direction of the main junction 202 towards the cutoff ring 205, the stepped structure of the fourth surface 131 has a gradually decreasing trend.

[0059] In addition, in another alternative embodiment of the present application, the maximum distance between the third surface 130 and the fourth surface 131 of the junction termination extension structure 100 is less than the distance between the first surface 210 and the second surface 211 of the main junction 202. That is to say, the junction termination extension structure 100 and the main junction 202 form a stepped shape, such that a charge concentration gradient decreasing trend is formed from the main junction 202 towards the junction termination extension structure 100.

[0060] In addition, in some embodiments of the present application, the surface of the epitaxial layer 201 between the junction termination extension structure 100 and the cutoff ring 205 facing away from the substrate 200 is coplanar with the fourth surface 131 corresponding to the second straight segment 108.

[0061] In other embodiments of the present application, the surface of the cutoff ring 205 facing away from the substrate 200 is coplanar with the fourth surface 131 corresponding to the second straight segment 108.

[0062] Figure 3 FIG. 19 shows one of the schematic diagrams of the method for preparing the terminal structure of a semiconductor device provided by some embodiments of the present application; Figure 4 FIG. 20 shows another schematic diagram of the method for preparing the terminal structure of a semiconductor device provided by some embodiments of the present application; Figure 5 FIG. 21 shows another schematic diagram of the method for preparing the terminal structure of a semiconductor device provided by some embodiments of the present application; Figure 6 FIG. 22 shows another schematic diagram of the method for preparing the terminal structure of a semiconductor device provided by some embodiments of the present application; Figure 7FIG. 5 shows a schematic diagram of a method for preparing a terminal structure of a semiconductor device provided by some embodiments of the present application.

[0063] As Figures 3 to 7 shown, the method for preparing the terminal structure of the semiconductor device includes:

[0064] Step a: As Figure 3 shown, an epitaxial layer 201 is grown on a heavily doped N-type semiconductor substrate 200. The epitaxial layer 201 can be an N-drift region, and then P-type ion implantation is performed to form a main junction 202.

[0065] Step b: As Figure 4 shown, P-type ion implantation is performed on one side of the P-type main junction 202 to form a junction termination extension structure. The junction depth of the junction termination extension structure needs to be lower than that of the main junction 202.

[0066] Step c: As Figure 5 shown, high-temperature annealing is performed to activate impurities, and a stepped shape is etched on the upper surface of the junction termination extension structure.

[0067] Step d: As Figure 6 shown, a cutoff ring 205 is formed by N-type ion implantation. The cutoff ring 205 is disposed opposite to the main junction 202; then, a dielectric layer is deposited on the side of the epitaxial layer 201 facing away from the substrate 200. Since the stepped shape is etched first and the epitaxial layer 201 is parallel to the end step surface of the stepped shape, that is, the epitaxial layer 201 is etched simultaneously, and the cutoff ring 205 is formed by ion implantation, the surface of the cutoff ring 205 facing away from the substrate 200 is coplanar with the fourth surface 131 corresponding to the second straight section 108. The process is simple, the steps are simplified, and the preparation effect is improved.

[0068] Step e: As Figure 7 shown, the isolation dielectric layer is etched to form a source contact region, the front metal is fabricated to form a source, and the back contact electrode is processed to form a drain.

[0069] In an embodiment of the present application, a semiconductor device is provided, including: a cell region and the terminal structure of the semiconductor device described above. The terminal structure of the semiconductor device is disposed at the edge of the cell region. The cell region and the terminal structure of the semiconductor device share the substrate 200, the epitaxial layer 201, the source, and the drain.

[0070] By using the junction termination extension technology, a multi-level stepped ramp structure is etched on the junction termination extension structure at the same time to modulate the electric field distribution. While significantly reducing the terminal length, a high breakdown voltage can still be achieved.

[0071] Figure 8 FIG. shows a TCAD simulation diagram of a traditional field limiting ring terminal structure; Figure 9 FIG. shows a TCAD simulation diagram of the terminal structure provided by some embodiments of the present application;Figure 10 The breakdown voltage comparison between the traditional field limiting ring terminal structure and the terminal structure of the present application is shown.

[0072] TCAD simulation verification was carried out on the terminal structure of the semiconductor device of the present application. Taking the terminal structure of a silicon carbide power device as an example, the target design is to meet the terminal structure with a breakdown voltage above 1200V. The field limiting ring implementation method and the junction terminal extension structure implementation method of the present application were compared. The simulation results are as Figure 8 and Figure 9 shown. When the breakdown voltage above 1200V is satisfied, taking the outermost ring on the right end as the cut-off point, the length of the traditional field limiting ring terminal structure is 100um, and the length of the terminal structure of the present application is 50um. The length can be reduced by 50%, effectively saving the terminal area and reducing the chip manufacturing cost. Moreover, under the same epitaxial thickness and concentration conditions, the breakdown voltage of the terminal structure of the present application is 1571V, and the breakdown voltage of the traditional field limiting ring terminal structure is 1424V. Compared with the field limiting ring structure, the breakdown voltage of the terminal structure of the present application is increased by 10%, and the terminal efficiency is higher. The breakdown voltage comparison is as Figure 10 shown. Among them, Figure 10 A represents the traditional field limiting ring terminal structure, and B represents the terminal structure of the present application.

[0073] A multi-level stepped structure is formed on the upper surface of the junction terminal extension structure. While greatly reducing the terminal length, the withstand voltage requirement is effectively achieved. Moreover, according to different voltage levels, junction terminal extension structures, implantation concentrations, etc., the number and angle of the steps can be designed and a reasonable number of steps and ramp angles can be matched to achieve the required withstand voltage value.

[0074] As described above, it is only the specific implementation manner of the present application. Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, modules, and units described above can refer to the corresponding processes in the foregoing method embodiments and will not be repeated here. It should be understood that the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application.

Claims

1. A terminal structure of a semiconductor device, characterized in that, Comprising: A substrate; An epitaxial layer formed on the substrate; A main junction formed on a side of the epitaxial layer facing away from the substrate, the main junction including a first surface and an opposite second surface, the first surface being in contact with the epitaxial layer; A cutoff ring formed on a side of the epitaxial layer facing away from the substrate, the main junction and the cutoff ring being spaced apart; A junction termination extension structure formed on a side of the epitaxial layer facing away from the substrate, the junction termination extension structure being disposed between the main junction and the cutoff ring and connected to the main junction, the junction termination extension structure including a third surface and an opposite fourth surface, the third surface being in contact with the epitaxial layer, from the main junction towards the cutoff ring direction, the junction termination extension structure includes a first extension portion and a second extension portion, the fourth surface corresponding to the first extension portion is coplanar with the second surface, from the main junction towards the cutoff ring direction, the fourth surface corresponding to the second extension portion is in a stepped shape with a gradually decreasing trend; 2. The terminal structure of the semiconductor device according to claim 1, wherein, The second extension portion includes at least one stepped portion connected to the first extension portion, from the main junction towards the cutoff ring direction, the fourth surface corresponding to the stepped portion sequentially includes a ramp segment and a flat segment, the flat segment is parallel to the second surface, and the included angle between the ramp segment and the flat segment is greater than 90 degrees and less than 180 degrees; 3. The terminal structure of the semiconductor device according to claim 2, characterized in that, Along the direction of the main junction and the cutoff ring, the length of the stepped portion corresponding to the ramp segment is less than the length of the stepped portion corresponding to the flat segment; 4. The terminal structure of the semiconductor device according to claim 2, characterized in that, From the main junction towards the cutoff ring direction, the second extension portion sequentially includes a connected first stepped portion and a second stepped portion; The fourth surface corresponding to the first stepped portion sequentially includes a first ramp segment and a first flat segment, the first flat segment is parallel to the second surface, and the included angle between the first ramp segment and the first flat segment is 135 degrees; The fourth surface corresponding to the second stepped portion sequentially includes a second ramp segment and a second flat segment, the second flat segment is parallel to the second surface, and the included angle between the second ramp segment and the second flat segment is 135 degrees; 5. The terminal structure of the semiconductor device according to claim 4, characterized in that, The surface of the epitaxial layer facing away from the substrate between the junction termination extension structure and the cutoff ring is coplanar with the fourth surface corresponding to the second flat segment; 6. The terminal structure of the semiconductor device according to claim 4 or 5, characterized in that, The surface of the cutoff ring facing away from the substrate is coplanar with the fourth surface corresponding to the second flat segment; 7. The terminal structure of the semiconductor device according to claim 1, wherein The third surface of the junction termination extension structure is a flat surface and is parallel to the fourth surface corresponding to the first extension portion; 8. The terminal structure of the semiconductor device according to claim 1, characterized in that, The maximum distance between the third surface and the fourth surface of the junction termination extension structure is less than the distance between the first surface and the second surface of the main junction; 9. The terminal structure of the semiconductor device according to any one of claims 1, characterized in that Further comprising: A dielectric layer disposed on the surface of the epitaxial layer facing away from the substrate, the dielectric layer covering part of the main junction, the junction termination extension structure, the epitaxial layer between the junction termination extension structure and the cutoff ring, and the cutoff ring; A source electrode, which is disposed on a side of the epitaxial layer facing away from the substrate, and the source electrode is connected to the main junction; A drain electrode, which is disposed on a side of the substrate facing away from the epitaxial layer.

10. A semiconductor device, characterized in that, Comprising: A cell region and a terminal structure of the semiconductor device according to claims 1 to 9, and the terminal structure of the semiconductor device is disposed at an edge of the cell region.

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