Semiconductor device with step structure

Abstract

The embodiment of the utility model provides a semiconductor device with a step structure. The semiconductor device comprises a substrate, an epitaxial layer on the substrate, source metal and drain metal arranged on the epitaxial layer, and a dielectric layer arranged on the epitaxial layer, the source metal and the drain metal, wherein the dielectric layer comprises a plurality of step structures with different depths, the gate metal is arranged on the step structure with the maximum depth, and the metal field plate structure is arranged on other step structures except the step structure with the maximum depth; according to the scheme, multiple layers of field plates can be formed at a time only by arranging the metal field plate structures on the step structures with different depths, so that the process cost and time can be greatly reduced, and the manufacturing efficiency and the reliability of the device are improved.

Description

Technical Field

[0001] This application relates to the field of semiconductors, and particularly to a semiconductor device with a stepped structure. Background Art

[0002] With the development of science and technology, semiconductor devices are increasingly widely used in various fields. Among them, gallium nitride high electron mobility transistors (GaN HEMT, GaN High Electron Mobility Transistors, hereinafter referred to as gallium nitride power devices), as representatives of wide bandgap (WBG, Wide Bandgap) power semiconductor devices, have great potential in high-frequency power applications.

[0003] In the design of gallium nitride power devices, the breakdown voltage of the device is a very important performance parameter. To improve the breakdown voltage of the device, the prior art generally weakens the electric field peaks originally present near the gate and modulates the electric field distribution by setting multiple field plates in the device, thereby improving the breakdown voltage of the device.

[0004] However, in the process of researching and practicing the prior art, the inventors of this application found that in the process of manufacturing the device, in order to implement multiple field plates, it is often necessary to perform etching of multiple dielectrics and metals and perform multiple photolithographies. For example, in some common structures in the industry, for each additional field plate, at least one additional photolithography and etching step are required. Therefore, as the number of field plate layers increases, the process cost and time cost will also increase significantly. That is, the prior art not only has a high process cost but also a low manufacturing efficiency. Summary of the Invention

[0005] An embodiment of this application provides a semiconductor device with a stepped structure, which can reduce the process cost and time of manufacturing multiple field plates and improve the manufacturing efficiency.

[0006] The semiconductor device includes:

[0007] A substrate;

[0008] An epitaxial layer, disposed on the substrate;

[0009] A source metal and a drain metal, disposed on the epitaxial layer;

[0010] A dielectric layer, disposed on the epitaxial layer, the source metal, and the drain metal; wherein, the dielectric layer includes multiple stepped structures with different depths;

[0011] A gate metal, disposed on the stepped structure with the maximum depth;

[0012] A metal field plate structure, disposed on the other stepped structures except the stepped structure with the maximum depth.

[0013] In addition, an embodiment of the present application further provides another semiconductor device with a stepped structure, including:

[0014] A substrate;

[0015] An epitaxial layer disposed on the substrate;

[0016] A source metal, a drain metal, and a gate metal disposed on the epitaxial layer;

[0017] A dielectric layer disposed on the epitaxial layer, the source metal, the drain metal, and the gate metal; wherein, the dielectric layer includes a plurality of stepped structures with different depths;

[0018] A metal field plate structure disposed on the stepped structure.

[0019] Since the dielectric layer of the semiconductor device with a stepped structure in the embodiment of the present application includes a plurality of stepped structures with different depths, therefore, by simply disposing a metal field plate structure on these stepped structures with different depths, a multi-layer field plate can be formed at one time. That is to say, by simply adjusting the depth and number of the stepped structures, the effect of an arbitrary multi-layer field plate can be achieved, without the need for layer-by-layer processing of the field plate. Compared with the existing solution where at least one more photolithography and etching step is required for each additional layer of the field plate, the process cost and time can be greatly reduced, and the manufacturing efficiency can be improved; moreover, since the multi-layer field plate is formed at one time, the number of depositions and etching of the dielectric and metal can also be reduced, greatly reducing the possibility of etching damage, making the quality of the dielectric under the field plate higher, which is beneficial to improving the reliability of the device. Description of the Drawings

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0021] Figure 1 is a schematic structural diagram of the semiconductor device with a stepped structure provided by the embodiment of the present application;

[0022] Figure 2 is another schematic structural diagram of the semiconductor device with a stepped structure provided by the embodiment of the present application;

[0023] Figure 3 is a process example diagram of the semiconductor device with a stepped structure provided by the embodiment of the present application;

[0024] Figure 4 It is another schematic structural diagram of the semiconductor device with a stepped structure provided by the embodiment of the present application;

[0025] Figure 5 It is another schematic structural diagram of the semiconductor device with a stepped structure provided by the embodiment of the present application. Detailed implementation manners

[0026] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present application.

[0027] The embodiment of the present application provides a semiconductor device with a stepped structure. The following will be described in detail respectively.

[0028] A semiconductor device with a stepped structure includes a substrate, an epitaxial layer, a source ohmic metal, a drain ohmic metal, a dielectric layer (also referred to as a dielectric layer), a gate ohmic metal, and a metal field plate structure; wherein:

[0029] The epitaxial layer is disposed on the substrate; the source ohmic metal and the drain ohmic metal are disposed on the epitaxial layer, and the dielectric layer is disposed on the epitaxial layer, the source ohmic metal, and the drain ohmic metal (the dielectric layer may include a gate dielectric layer 109, a first dielectric layer 108, and a second dielectric layer 105, wherein the material of the gate dielectric layer 109 is denser than the materials of the first dielectric layer 108 and the second dielectric layer 105); wherein, the dielectric layer includes a plurality of stepped structures with different depths, the gate ohmic metal is disposed on the stepped structure with the maximum depth, and the metal field plate structure is disposed on the other stepped structures except the stepped structure with the maximum depth.

[0030] For example, specifically, the gate ohmic metal can be deposited on the deepest stepped structure, and the field plate metal can be deposited on the other stepped structures except the stepped structure with the maximum depth, so that the field plate metals deposited on the stepped structures with different heights can be used as field plates of different layers (that is, the field plate metals deposited on the adjacent stepped structures with the same height are used as the metal field plate structure of the same layer, and the field plate metals deposited on the stepped structures with different heights are used as the metal field plate structures of different layers). Then, lithography and metal etching are performed on the field plate metal, and a multi-layer metal field plate structure can be obtained.

[0031] Among them, the material selection of the gate metal and the metal field plate structure can be determined according to the requirements of the actual device and process conditions. For example, metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or nickel (Ni) can be used, or their alloys or compounds can also be used, etc., which are not limited herein.

[0032] Among them, the depth of the step structure closest to the gate metal is the deepest, and the depth of the step structure farther away from the gate metal is shallower; the width of the step structure closest to the gate metal is the smallest, and the width of the step structure farther away from the gate metal is larger.

[0033] For example, as Figure 1 shown, taking the fabrication of the gate metal at the step structure S03 as an example, the depth of the step structure S03 is the deepest. On the right side of S03, the depth of the step structure S04 is the second deepest, the step structure S05 is shallower than S04, the step structure S06 is shallower than S05, and since the step structure S07 is the farthest from S03, its depth is the shallowest; similarly, on the left side of S03, the step structures are arranged in descending order of depth as S02 and S01.

[0034] Optionally, the substrate material of the semiconductor device can be selected according to the required semiconductor material and device performance. For example, the substrate material can include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or gallium oxide (GaO), etc.

[0035] Optionally, the metal field plate structure can be disposed on both sides of the gate metal, or the metal field plate structure can also be disposed between the gate metal and the source metal.

[0036] For example, as Figure 1 shown, the semiconductor device can include a substrate 101, an epitaxial layer 102 disposed on the substrate 101, a source metal 103 and a drain metal 104 disposed on the epitaxial layer 102, and a dielectric layer disposed on the epitaxial layer 102, the source metal 103, and the drain metal 104. Among them, the dielectric layer includes a plurality of step structures with different depths. The gate metal 106 is disposed on the step structure with the largest depth, while the metal field plate structure 107 is disposed on the other step structures except the step structure with the largest depth and on both sides of the gate metal 106.

[0037] Another example, as Figure 2As shown, the semiconductor device may include a substrate 101, an epitaxial layer 102 disposed on the substrate 101, a source metal 103 and a drain metal 104 disposed on the epitaxial layer 102, and a dielectric layer disposed on the epitaxial layer 102, the source metal 103, and the drain metal 104. Among them, the dielectric layer includes a plurality of stepped structures with different depths. The gate metal 106 is disposed on the stepped structure with the maximum depth, while the metal field plate structure 107 is disposed on the other stepped structures except the stepped structure with the maximum depth and is disposed between the gate metal 106 and the source metal 103.

[0038] Optionally, whether the gate metal 106 and the metal field plate structure 107 are connected can be determined according to the requirements of actual applications.

[0039] For example, if a gate field plate is required, the gate metal 106 can be connected to the metal field plate structure 107.

[0040] Among them, there are various ways to connect the gate metal 106 and the metal field plate structure 107. For example, as Figure 1 shown, during deposition, the gate metal 106 and the metal field plate structure 107 can be directly connected through a deposited metal layer; or, as Figure 2 shown, if the gate metal 106 and the metal field plate structure 107 are not connected through a deposited metal layer, the gate metal 106 and the metal field plate structure 107 can be connected through an interconnect metal; that is to say, the semiconductor device may further include a first interconnect metal, where the first interconnect metal is used to connect to the gate metal 106 and the metal field plate structure 107 respectively.

[0041] Similarly, if a source field plate is required, the source metal 103 can be connected to the metal field plate structure 107.

[0042] Among them, there are also various ways to connect the source metal 103 and the metal field plate structure 107. For example, as Figure 1 shown, if the gate metal 106 and the metal field plate structure 107 are connected through a deposited metal layer during deposition, the gate metal 106 and the metal field plate structure 107 can be disconnected during metal etching, and then an interconnect metal connecting the source metal 103 and the metal field plate structure 107 can be fabricated on the dielectric layer; or, as Figure 2 shown, if the gate metal 106 and the metal field plate structure 107 are not connected through a deposited metal layer during deposition, at this time, an interconnect metal connecting the source metal 103 and the metal field plate structure 107 can be directly fabricated on the dielectric layer. That is to say, the semiconductor device may further include a second interconnect metal, where the second interconnect metal is used to connect to the source metal 103 and the metal field plate structure 107 respectively.

[0043] Optionally, the source metal 103 of the semiconductor device may be disposed in a preset first region on the epitaxial layer. For example, see Figure 1 and Figure 2 , specifically, the source metal 103 can be obtained by fabricating a metal electrode on the first region of the epitaxial layer 102 such that the metal electrode forms an ohmic contact with the epitaxial layer 102.

[0044] Similarly, the drain metal 104 can be disposed in a preset second region on the epitaxial layer 102. For example, specifically, the drain metal 104 can be obtained by fabricating a metal electrode on the second region of the epitaxial layer 102 such that the metal electrode forms an ohmic contact with the epitaxial layer 102.

[0045] Herein, an ohmic contact refers to a contact resistance between a metal and a semiconductor that is very small and can be almost ignored, thereby ensuring that there is no significant voltage drop in the current at the contact surface. The process of fabricating a metal electrode in a specific region (such as the source, drain, or gate) to form an ohmic contact is called the ohmic metal process.

[0046] After the ohmic metal process is completed, specifically, a second dielectric layer 105 can be formed by depositing a dielectric on the epitaxial layer 102, the source metal 103, and the drain metal 104. The first dielectric layer 108 is formed before fabricating the metal electrode.

[0047] Optionally, the stepped structure in the dielectric layer may be composed of a groove structure. For example, taking the case where the dielectric layer has a plurality of connected groove structures with various depths and widths, at this time, the adjacent groove structures with the same depth can be regarded as the stepped structures of the same layer. That is, "the dielectric layer includes a plurality of stepped structures with different depths" may include:

[0048] The dielectric layer has a plurality of connected groove structures with various depths and widths, and the adjacent groove structures with the same depth form the stepped structures of the same layer.

[0049] Optionally, the load effect of dry etching and wet etching can be utilized to fabricate groove structures with different depths and widths and that are connected by setting photolithography windows with different widths. For example, specifically, a photolithography mask can be set on a dielectric layer. Among them, the photolithography mask has photolithography windows with various widths. Then, the dielectric layer provided with the photolithography mask is dry-etched, and corresponding groove structures can be formed at the photolithography windows. Then, the dielectric layer is wet-etched to connect adjacent groove structures, and multiple connected groove structures with various depths and widths can be obtained (due to the isotropic property of wet etching, after the etching solution enters the groove structure, it will corrode the medium between adjacent groove structures, making the adjacent groove structures connected, further deepening the depth of each groove structure, and making the side walls of the groove structures smoother, thereby forming multiple stepped structures with different depths).

[0050] Among them, the pattern of the photolithography mask can be determined according to the requirements of actual applications. For example, the pattern of the photolithography mask can be: between the source metal and the drain metal, photolithography windows with various widths are set. Among them, the width of the middle photolithography window is the largest, and the widths on both sides gradually become narrower in turn.

[0051] Optionally, the width size and arrangement of the photolithography windows can also be set according to the requirements of actual applications. For example, see Figure 3 , the photolithography window with the largest width can also be set at a position closer to the source metal, and the widths of other photolithography windows gradually become narrower as the distance from this "photolithography window with the largest width" increases. For example, in Figure 3 , the width of the photolithography window W3 is the largest, and the widths of the photolithography windows on both sides of the photolithography window W3 gradually decrease. For example, their width sizes are: W3>W2>W1, W3>"W4 and W5""W6, W7 and W8">W9, and so on.

[0052] Among them, due to the load effect of dry etching, the depth and width of the groove structure are proportional to the width of the corresponding photolithography window. That is to say, at the position of the wider photolithography window, the etching width is wider and the etching depth is deeper, while at the position of the narrower photolithography window, the etching width is narrower and the etching depth is shallower. For example, specifically, see Figure 3 , from Figure 3 it can be seen that as the width of the photolithography window gradually decreases, the width and depth of the corresponding groove structure also gradually become smaller. Specifically as follows:

[0053] Since the width of the lithography window W3 is the largest, the width of the corresponding groove structure G3 is the largest and the depth is the deepest. Among the other lithography windows on the right side of W3, since the widths of the lithography windows W4 and W5 are narrower than that of W3, the widths of the groove structures G4 and G5 corresponding to the lithography windows W4 and W5 are also narrower than G3 and the depth is shallower than G3; similarly, since the widths of the lithography windows W6, W7 and W8 are narrower than those of W4 and W5, the widths of the groove structures G6, G7 and G8 corresponding to the lithography windows W6, W7 and W8 are also narrower than G4 and G5 and the depth is shallower than G4 and G5; and so on. Since the width of the lithography window W9 is the narrowest, the width of the groove structure G9 corresponding to the lithography window W9 is the narrowest and the depth is also the shallowest. Similarly, among the other lithography windows on the left side of W3, the width of the groove structure G1 corresponding to W1 is less than that of the groove structure G2 corresponding to W2, and G2 is less than G3, and so on.

[0054] Optionally, in addition to setting the widths of the lithography windows to be different from each other, two or more adjacent lithography windows can also be set to have the same or similar widths. For example, see Figure 3 , where the widths of the lithography window W4 and the lithography window W5 are the same, and the widths of the lithography window W6, the lithography window W7 and the lithography window W8 are also the same, and so on.

[0055] By setting multiple adjacent lithography windows to have the same or similar widths, the adjacent grooves obtained after subsequent etching can have the same or similar depths. In this way, these grooves with the same or similar depths can be used as the same layer of step structure, and this layer of step structure can be equivalently regarded as a longer field plate in terms of effect. And in this way, by arranging and combining the groove structure sizes, any required combination of field plate depth and length can be obtained.

[0056] For example, since the widths of the lithography windows W4 and W5 are the same, the widths and depths of the corresponding groove structures G4 and G5 are also approximately the same. Furthermore, the heights of the step structures S4 and S5 corresponding to the groove structures G4 and G5 are also approximately the same. Therefore, the step structures S4 and S5 can be equivalently regarded as a longer step structure in terms of effect (a layer of metal field plate structure can be fabricated subsequently); similarly, since the widths of the lithography windows W6, W7 and W8 are the same, the widths and depths of the corresponding groove structures G6, G7 and G8 are also generally consistent. Furthermore, the heights of the step structures S6, S7 and S8 corresponding to them are also approximately the same. Therefore, the step structures S6, S7 and S8 can be equivalently regarded as a longer step structure in terms of effect (a layer of metal field plate structure can be fabricated subsequently), and so on, which will not be elaborated here.

[0057] Optionally, a dielectric layer with a certain thickness can be reserved between the bottom of the deepest step structure and the epitaxial layer as the gate dielectric (which can be referred to as the gate dielectric layer) for subsequent fabrication of the gate metal. The material of the gate dielectric layer is denser than that of the upper dielectric layers (the first dielectric layer and the second dielectric layer), so the wet etching rate on the gate dielectric layer can be effectively slowed down.

[0058] Through wet etching, the morphology of the groove structure can be made continuous and smooth, so as to ensure better filling effect and better modulation effect on the electric field during subsequent fabrication of the gate metal.

[0059] The so-called loading effect of dry etching refers to the phenomenon that when the size or shape of the etching area changes, the etching rate also changes accordingly, that is, the etching rate depends on the amount of the material on the etched surface. This loading effect generally includes three types: macroloading, microloading, and aspect ratio dependent etching (ARDE). Among them, ARDE mainly appears in the etching of high aspect ratio structures, such as deep holes or deep grooves. In these structures, it is difficult for the etching material to enter the deep part, and at the same time, the reaction products are difficult to overflow, resulting in a decrease in the etching rate at the bottom. The loading effect will affect the accuracy of the shape and size of the structure, so it is generally suppressed as much as possible. However, this application precisely utilizes this characteristic to fabricate groove structures with different widths and depths, and then form step structures with different depths, making the originally harmful phenomenon become a factor beneficial to the process.

[0060] Optionally, the semiconductor device fabricated in this embodiment can be a MIS-HEMT, a P-GaN HEMT (P-type gate enhanced GaN HEMT), or a recessed gate HEMT (High Electron Mobility Transistors). The materials of the semiconductor device include but are not limited to GaN, SiC, GaAs, or GaO, which will not be elaborated here.

[0061] As can be seen from the above, since there are multiple stepped structures with different depths on the dielectric layer of the semiconductor device of this embodiment, therefore, by simply setting up a metal field plate structure on these stepped structures with different depths, the gate metal and multiple layers of field plates can be formed at one time. That is to say, by simply adjusting the depth and quantity of the stepped structures, the effect of any multi-layer field plates can be achieved without the need for layer-by-layer processing of the field plates. Compared with the existing solution where at least one additional photolithography and etching step is required for each additional layer of field plate, this can greatly reduce the process cost and time and improve the manufacturing efficiency. Moreover, since the multi-layer field plates are formed at one time, the number of depositions and etching of the dielectric and metal can also be reduced, greatly reducing the possibility of etching damage, making the quality of the dielectric under the field plate higher, which is conducive to improving the reliability of the device.

[0062] Optionally, in some embodiments of the present application, the gate metal and the metal field plate structure can be fabricated together or separately. That is, the embodiments of the present application also provide another semiconductor device with a stepped structure, which includes a substrate, an epitaxial layer, a source metal, a drain metal, a gate metal, a dielectric layer, and a metal field plate structure; wherein:

[0063] The epitaxial layer is disposed on the substrate; the source metal, the drain metal, and the gate metal are disposed on the epitaxial layer; and the dielectric layer is disposed on the epitaxial layer, the source metal, the drain metal, and the gate metal. Wherein, the dielectric layer includes multiple stepped structures with different depths, and the metal field plate structure is disposed on the stepped structures.

[0064] For example, specifically, a field plate metal can be deposited on each stepped structure, such that the field plate metals deposited on the stepped structures with different heights can serve as different layers of field plates (i.e., the field plate metals deposited on the stepped structures at the same adjacent height serve as the metal field plate structure of the same layer, and the field plate metals deposited on the stepped structures with different heights serve as the metal field plate structures of different layers). Then, photolithography and metal etching are performed on the field plate metal to obtain a multi-layer metal field plate structure.

[0065] Among them, the selection of the field plate metal can be determined according to the requirements of the actual device and the process conditions. For example, metals such as aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), or nickel (Ni) can be used, or their alloys or compounds can also be used, etc., which are not limited herein.

[0066] Among them, the depth of the stepped structure closest to the gate metal is the deepest, and the depth of the stepped structure farther away from the gate metal is shallower. The width of the stepped structure closest to the gate metal is the smallest, and the width of the stepped structure farther away from the gate metal is larger; for example, specifically, reference can be made to Figure 5 .

[0067] Optionally, the substrate material of the semiconductor device can be selected according to the desired semiconductor material and device performance. For example, the substrate material can include silicon (Si), silicon carbide (SiC), gallium nitride (GaN), gallium arsenide (GaAs), or gallium oxide (GaO), etc.

[0068] Optionally, the metal field plate structure can be disposed on both sides of the gate metal, or the metal field plate structure can also be disposed between the gate metal and the source metal.

[0069] For example, taking the case of being disposed between the gate metal and the source metal as an example, refer to Figure 5 , the semiconductor device can include a substrate 201, an epitaxial layer 202 disposed on the substrate 201, a source metal 203, a drain metal 204, and a gate metal 206 disposed on the epitaxial layer 202, and a dielectric layer (including a second dielectric layer 205 and a first dielectric layer 209) disposed on the epitaxial layer 202, the source metal 203, the drain metal 204, and the gate metal 206. Among them, the dielectric layer includes a plurality of stepped structures with different depths, the stepped structure is located between the gate metal 206 and the source metal 203, and the metal field plate structure 207 is disposed on the stepped structure.

[0070] Optionally, whether to connect between the gate metal 206 and the metal field plate structure 207 can be determined according to the actual application requirements.

[0071] For example, if a gate field plate is required, the gate metal 206 can be connected to the metal field plate structure 207.

[0072] Among them, there are various ways to connect the gate metal 206 to the metal field plate structure 207. For example, the gate metal 206 and the metal field plate structure 207 can be connected through an interconnect metal; that is, the semiconductor device can further include a third interconnect metal, where the third interconnect metal is used to connect to the gate metal 206 and the metal field plate structure 207 respectively.

[0073] Similarly, if a source field plate is required, the source metal 203 can be connected to the metal field plate structure 207. For example, the source metal 203 and the metal field plate structure 207 can be connected through an interconnect metal; that is, the semiconductor device can further include a fourth interconnect metal, where the fourth interconnect metal is used to connect to the source metal 203 and the metal field plate structure 207 respectively.

[0074] Optionally, the source metal 203 of the semiconductor device can be disposed in a preset first region on the epitaxial layer. For example, refer to Figure 5, specifically, the source metal 203 can be obtained by fabricating a metal electrode on the first region of the epitaxial layer 202 such that the metal electrode forms an ohmic contact with the epitaxial layer 202.

[0075] Similarly, the drain metal 204 can be disposed in a preset second region on the epitaxial layer 202. For example, specifically, the drain metal 204 can be obtained by fabricating a metal electrode on the second region of the epitaxial layer 202 such that the metal electrode forms an ohmic contact with the epitaxial layer 202.

[0076] Similarly, the gate metal 206 can be disposed in a preset third region on the epitaxial layer 202. For example, specifically, the drain metal 206 can be obtained by fabricating a metal electrode on the third region of the epitaxial layer 202 such that the metal electrode forms an ohmic contact with the epitaxial layer 202.

[0077] Similar to the previous embodiments, optionally, the step structure in the dielectric layer can also be composed of a groove structure. For example, taking the dielectric layer having a plurality of connected groove structures with various depths and widths as an example, at this time, the adjacent groove structures having the same depth can be regarded as the step structures of the same layer. That is, "the dielectric layer includes a plurality of step structures with different depths" can include:

[0078] The dielectric layer has a plurality of connected groove structures with various depths and widths, and the adjacent groove structures having the same depth form the step structures of the same layer.

[0079] Optionally, the load effect of dry etching and wet etching can be utilized to fabricate groove structures with different depths and widths and connected by setting photolithography windows with different widths. For details, please refer to the previous embodiments and will not be elaborated here.

[0080] Optionally, the semiconductor device with a step structure fabricated in this embodiment can be a MIS-HEMT, P-GaN HEMT, or a grooved-gate HEMT. The materials of the semiconductor device include but are not limited to GaN, SiC, GaAs, or GaO, which will not be elaborated here.

[0081] As can be seen from the above, since there are multiple stepped structures with different depths on the dielectric layer of the semiconductor device with a stepped structure in this embodiment, therefore, by simply setting a metal field plate structure on these stepped structures with different depths, multiple layers of field plates can be formed at one time. That is to say, by simply adjusting the depth and number of the stepped structures, the effect of any number of layers of field plates can be achieved, without the need for layer-by-layer processing of the field plates. Compared with the existing solution where at least one additional photolithography and etching step is required for each additional layer of the field plate, the process cost and time can be greatly reduced, and the production efficiency can be improved; moreover, since the multiple layers of field plates are formed at one time, the number of depositions and etching of the dielectric and metal can also be reduced, greatly reducing the possibility of etching damage, making the quality of the dielectric under the field plate higher, which is beneficial to improving the reliability of the device.

[0082] The above has introduced in detail a semiconductor device with a stepped structure provided by an embodiment of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A semiconductor device having a stepped structure, characterized in that, Comprising: A substrate; An epitaxial layer disposed on the substrate; A source metal and a drain metal disposed on the epitaxial layer; A dielectric layer disposed on the epitaxial layer, the source metal, and the drain metal; wherein, the dielectric layer includes a plurality of stepped structures with different depths; A gate metal disposed on the stepped structure with the maximum depth; A metal field plate structure disposed on the other stepped structures except the stepped structure with the maximum depth.

2. The semiconductor device with a stepped structure according to claim 1, characterized in that, The dielectric layer includes a plurality of stepped structures with different depths, including: The dielectric layer has a plurality of connected groove structures with various depths and widths, wherein the adjacent groove structures with the same depth form the stepped structures of the same layer.

3. The semiconductor device with a stepped structure according to claim 1, wherein The metal field plate structure is disposed on both sides of the gate metal; or, The metal field plate structure is disposed between the gate metal and the drain metal.

4. The semiconductor device with a stepped structure according to any one of claims 1 to 3, wherein The metal field plate structure is connected to the gate metal.

5. The semiconductor device with a stepped structure according to any one of claims 1 to 3, wherein The stepped structure closest to the gate metal has the deepest depth, and the stepped structures farther away from the gate metal have shallower depths; The stepped structure closest to the gate metal has the smallest width, and the stepped structures farther away from the gate metal have larger widths.

6. The semiconductor device with a stepped structure according to any one of claims 1 to 3, characterized in that, It further includes a second interconnection metal; The second interconnection metal is respectively connected to the metal field plate and the source metal.

7. The semiconductor device with a stepped structure according to any one of claims 1 to 3, characterized in that, The semiconductor device is a MIS-HEMT, P-GaN HEMT, or a grooved gate HEMT, and the materials of the semiconductor device include, but are not limited to, GaN, SiC, GaAs, or GaO.

8. A semiconductor device with a stepped structure, characterized in that Comprising: A substrate; An epitaxial layer disposed on the substrate; A source metal, a drain metal, and a gate metal disposed on the epitaxial layer; A dielectric layer disposed on the epitaxial layer, the source metal, the drain metal, and the gate metal; wherein, the dielectric layer includes a plurality of stepped structures with different depths; A metal field plate structure disposed on the stepped structure.

9. The semiconductor device with a stepped structure according to claim 8, characterized in that, It further includes a fourth interconnection metal; The fourth interconnection metal is respectively connected to the metal field plate and the source metal.

10. The semiconductor device with a stepped structure according to claim 8 or 9, wherein The stepped structure closest to the gate metal has the deepest depth, and the stepped structures farther away from the gate metal have shallower depths; The stepped structure closest to the gate metal has the smallest width, and the stepped structures farther away from the gate metal have larger widths.

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