Integrated circuit device

Abstract

An integrated circuit device includes a semiconductor substrate, a plurality of multi-bit cells over the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit units includes a first bit and a second bit. The first bit cell includes a first electrostatic discharge (ESD) protection circuit and a first band region in the semiconductor substrate. The second bit cell includes a second ESD protection circuit and a second band region in the semiconductor substrate. In a top view, the first band region of the first bit and the second band region of the second bit are symmetric with respect to a boundary between the first bit and the second bit, and the first p-type band region of the first bit and the second band region of the second bit have a first conductivity type. The first pad and the second pad are respectively connected to the first ESD protection circuit and the second ESD protection circuit.

Description

Technical Field

[0001] Some embodiments of the present disclosure relate to integrated circuit devices. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced rapid growth. Technological advances in IC materials and design have produced several generations of ICs, each having smaller and more complex circuits than the previous generation. However, these advances have increased the complexity of processing and manufacturing ICs, and similar developments in IC processing and manufacturing are required to achieve these advances.

[0003] During the evolution of ICs, the functional density (i.e., the number of interconnect devices per wafer area) generally increases, while the geometric size (i.e., the smallest component (or wiring) that can be produced using a manufacturing process) decreases. This scaling process generally provides benefits by increasing production efficiency and reducing associated costs. Such scaling also results in relatively high power dissipation values, which can be addressed by using low-power dissipation devices such as complementary metal-oxide-semiconductor (CMOS) devices. Summary of the Utility Model

[0004] According to some embodiments of the present utility model, an integrated circuit device includes a semiconductor substrate, a plurality of multi-bit units above the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit units includes a first bit and a second bit. The first bit includes a first electrostatic discharge (ESD) protection circuit and a first doped band region in the semiconductor substrate. The second bit includes a second ESD protection circuit and a second doped band region in the semiconductor substrate. In a top view, the first doped band region of the first bit is symmetric with respect to the second doped band region of the second bit relative to the boundary between the first bit and the second bit. The first pad is connected to the first ESD protection circuit. The second pad is connected to the second ESD protection circuit.

[0005] According to some embodiments of the present utility model, an integrated circuit device includes a semiconductor substrate, a plurality of multi-bit units above the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit units includes a first bit and a second bit. The first bit includes a first ESD protection circuit. The second bit includes a second ESD protection circuit. In a top view, the first ESD protection circuit of the first bit is substantially symmetric with respect to the second ESD protection circuit of the second bit relative to the boundary between the first bit and the second bit. The first pad is connected to the first ESD protection circuit. The second pad is connected to the second ESD protection circuit.

[0006] According to some embodiments of the present invention, an integrated circuit device includes a first bit, a second bit, a first pad, and a second pad. The first bit includes a first electrostatic discharge (ESD) protection circuit, wherein the first ESD protection circuit includes a first n-type device and a first p-type device in a first region of a semiconductor substrate. The second bit includes a second ESD protection circuit, wherein the second ESD protection circuit includes a second n-type device and a second p-type device in a second region of the semiconductor substrate. The first n-type device and the first p-type device are symmetric to the second n-type device and the second p-type device with respect to a boundary between the first region and the second region. The first pad is located above an interconnect structure and electrically connected to the first n-type device and the first p-type device of the first ESD protection circuit. The second pad is located above the interconnect structure and electrically connected to the second n-type device and the second p-type device of the second ESD protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

[0008] Figure 1A is a schematic diagram of a stacked integrated circuit (IC) device according to some embodiments of the present disclosure;

[0009] Figure 1B FIG. Figure 1A is a schematic block diagram of the stacked IC device of

[0010] Figure 1C is Figure 1A a cross-sectional view of the stacked IC device of

[0011] Figure 2A FIG. shows a schematic block diagram illustrating the operation of the ESD protection circuit;

[0012] Figure 2B FIG. Figure 2A is a circuit diagram of the ESD protection circuit in

[0013] Figure 2C is Figure 2B a cross-sectional view of a part of the ESD protection circuit of

[0014] Figure 2D is Figure 2B a cross-sectional view of a part of the ESD protection circuit of

[0015] Figure 3A is a schematic diagram of an IC device according to some embodiments of the present disclosure;

[0016] Figure 3B Schematic diagram Figure 3A of the schematic configuration of multiple bits in an IC device;

[0017] Figure 3C Show Figure 3A the layout of the IC device;

[0018] Figure 3D Is Figure 3C an enlarged view of the n-type region in the ESD protection circuit in;

[0019] Figure 3E Is Figure 3C an enlarged view of the p-type region in the ESD protection circuit in;

[0020] Figure 3F Is Figure 3C an enlarged view of the n-type device in the ESD protection circuit in;

[0021] Figure 3G Is Figure 3C an enlarged view of the p-type device in the ESD protection circuit in;

[0022] Figure 4 is a schematic diagram of an IC device according to some embodiments of the present disclosure;

[0023] Figure 5A is a schematic diagram of an IC device according to some embodiments of the present disclosure;

[0024] Figure 5B Schematic diagram Figure 5A of the schematic configuration of multiple bits in the IC device;

[0025] Figure 5C Schematic diagram Figure 5A of the layout of the IC device;

[0026] Figure 6A is a schematic diagram of an IC device according to some embodiments of the present disclosure;

[0027] Figure 6B Schematic diagram Figure 6A of the schematic configuration of multiple bits in the IC device;

[0028] Figure 6C Show Figure 6A the layout of the IC device;

[0029] Figure 7 Schematic diagram showing the schematic configuration of multiple bits in an IC device according to some embodiments of the present disclosure;

[0030] Figure 8 Schematic diagram showing the schematic configuration of multiple bits in an IC device according to some embodiments of the present disclosure;

[0031] Figure 9 Schematic configuration of multiple bits in an IC device according to some embodiments of the present disclosure;

[0032] Figure 10 Schematic configuration of multiple bits in an IC device according to some embodiments of the present disclosure;

[0033] Figures 11A to 15B Layout and cross-sectional views of an integrated circuit structure at an intermediate stage of a manufacturing process according to some embodiments of the present disclosure;

[0034] Figure 16 Schematic diagram of an electronic design automation (EDA) system according to some embodiments of the present disclosure;

[0035] Figure 17 Block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments of the present disclosure.

[0036]

Symbol description

[0037] 100: IC device

[0038] 100a: Die

[0039] 100b: Die

[0040] 101: I / O circuit

[0041] 101a~101d: I / O circuit

[0042] 102: Logic circuit

[0043] 102a~102b: Logic circuit

[0044] 103: Buffer circuit

[0045] 103a~103b: Buffer circuit

[0046] 104: ESD protection circuit

[0047] 104a~104b: ESD protection circuit

[0048] 105: Pad

[0049] 105a~105b: Pad

[0050] 106: ESD power clamping circuit

[0051] 110: Substrate

[0052] 120: Isolation structure

[0053] 130: Gate structure

[0054] 132: Gate dielectric

[0055] 134: dummy gate

[0056] 140: Gate spacer

[0057] 160: ILD

[0058] 170: High-k / metal gate structure

[0059] 172: Gate dielectric layer

[0060] 174: Metal-containing layer

[0061] 180: ILD

[0062] 190: ILD

[0063] 200: Interconnection structure

[0064] 202: IMD layer

[0065] 204: Metal wiring

[0066] 206: Via

[0067] 1600: EDA system

[0068] 1602: Processor

[0069] 1604: Computer-readable storage medium

[0070] 1606: Instruction

[0071] 1607: Design layout

[0072] 1608: Bus

[0073] 1609: DRC group

[0074] 1610: I / O interface

[0075] 1612: Network interface

[0076] 1614: Network

[0077] 1616: UI

[0078] 1620: Semiconductor foundry

[0079] 1622: IC manufacturing tool

[0080] 1630: Mask room

[0081] 1632: Mask Manufacturing Tool

[0082] 1700: Manufacturing System

[0083] 1720: Design Office

[0084] 1722: Design Layout

[0085] 1730: Mask Room

[0086] 1732: Data Preparation

[0087] 1744: Mask Manufacturing

[0088] 1745: Reticle

[0089] 1750: Wafer Fab

[0090] 1752: Wafer Fabrication

[0091] 1753: Wafer

[0092] 1760: IC

[0093] BR1~BR6: Boundary

[0094] BT: Bit

[0095] BT1~BT8: Bit

[0096] CP: Contact Pad

[0097] CPP: Cell Poly Pitch

[0098] D1~D2: Diode

[0099] DE: Device

[0100] G: Gate Structure

[0101] LY: Length

[0102] L1: Length

[0103] L2: Length

[0104] L3: Length

[0105] MBC: Multi - Bit Cell

[0106] ML: Metal Line

[0107] M1: Metallization Layer

[0108] NDE: n - type Device

[0109] NStrap: n - type Strap

[0110] NW: n - type Well

[0111] N+: n-type heavily doped region

[0112] OD: Active region

[0113] PDE: p-type device

[0114] PODE: Auxiliary structure

[0115] PP: Region

[0116] PrB: Boundary

[0117] PStrap: p-type strip region

[0118] P+: p-type heavily doped region

[0119] RA~RD: Region

[0120] RX: Receiving circuit

[0121] SD: Source / drain region

[0122] TX: Transfer circuit

[0123] WR: Well

[0124] VD: Conductive structure

[0125] VDD: High-power voltage line / high-power guide rail

[0126] VDR: Conductive structure

[0127] VSS: Low-power voltage line / low-power guide rail

[0128] X: Direction

[0129] Y: Direction

[0130] Y-Y: Line Detailed implementation manners

[0131] The following disclosure provides many different embodiments, or examples, for implementing the different features of the provided subject matter. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first feature above or on a second feature may include embodiments in which the first feature and the second feature are formed in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature such that the first feature and the second feature are not in direct contact. In addition, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not in itself indicate the relationship between the various embodiments and / or configurations discussed.

[0132] In addition, for ease of description, spatial relative terms, such as "below", "beneath", "lower", "above", "upper", and the like, may be used herein to describe the relationship of one element or feature illustrated in the figures to another element or feature. Spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein may be correspondingly interpreted. As used herein, "about", "approximately", "substantially", or "essentially" may generally mean within 20% of a given value or range, or within 10%, or within 5%. The quantities given herein are approximate values, such that the terms "about", "approximately", "substantially", or "essentially" may be inferred where not expressly stated. However, those skilled in the art will recognize that the values or ranges mentioned throughout the specification are merely examples and may decrease or change as the scale of the integrated circuit is reduced.

[0133] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will be further understood that terms, such as those defined in a commonly used dictionary, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0134] Figure 1A is a schematic diagram of a stacked integrated circuit (IC) device according to some embodiments of the present disclosure. The IC device 100 includes a first die 100a and a second die 100b that are electrically coupled and / or physically coupled to each other. In some embodiments, the first die 100a and the second die 100b are stacked on top of each other and are physically and electrically coupled to each other through their pads 105a and 105b in a 3D IC. In some embodiments, the first die 100a and the second die 100b are arranged side by side on another substrate or die (not shown) and are physically coupled to the other substrate or die and are electrically coupled to each other through the other substrate and die. In some embodiments, the IC device 100 includes more than two dies that are electrically coupled and / or physically coupled to each other. In some embodiments, the IC device 100 has one die, e.g., the first die 100a, while omitting the other die, e.g., the second die 100b. In Figure 1A In the example configuration of, the second die 100b is configured similarly to the first die 100a. The first die 100a is described in detail herein, and the detailed description of the second die 100b is omitted.

[0135] Figure 1B IllustrationFigure 1A Schematic block diagram of a stacked IC device. Refer to Figure 1A and Figure 1B . The first die 100a may include one or more logic circuits 102a and one or more input / output (I / O) circuits 101a electrically coupled between the one or more logic circuits 102a and the pads 105a. In Figure 1B , a representative I / O circuit 101a and a representative logic circuit 102a of the first die 100a are illustrated. In some embodiments, the I / O circuits 101b and the logic circuits 102b of the second die 100b may correspond to the I / O circuits 101 and the logic circuits 102a of the first die 100a. In Figure 1A , a plurality of bits BT are repeated, and each of the bits BT includes an I / O circuit 101a connected to the pad 105a. Adjacent bits BT may be configured in a manner that saves the area of the I / O circuit 101a and meets the design rule check (DRC), which will be described later in terms of layout.

[0136] In some embodiments, the logic circuit 102a can be used to perform the intended functions of the IC device 100, such as data processing or data storage. Examples of one or more circuits, logics, or units included in the logic circuit 102a include, but are not limited to, AND, OR, NAND, NOR, XOR, INV, OR-AND-Invert (OAI), multiplexer (MUX), flip-flop, buffer (BUFF), latch, delay, clock, memory, or the like. The circuits, logics, or units included in the logic circuit 102a include functional transistors or core transistors that are to be protected from antenna effects during the manufacture of the IC device 100. Examples of transistors in the logic circuit 102a and in other circuits described herein include, but are not limited to, metal oxide semiconductor field effect transistor (MOSFET), complementary metal-oxide-semiconductor (CMOS) transistor, P-channel metal-oxide semiconductor (PMOS), N-channel metal-oxide semiconductor (NMOS), bipolar junction transistor (BJT), high-voltage transistor, high-frequency transistor, P-channel and / or N-channel field effect transistor (PFET / NFET), FinFET, planar MOS transistor with raised source / drain, nanosheet FET, nanowire FET, or the like.

[0137] In some embodiments, the I / O circuit 101a can be electrically coupled to the logic circuit 102a and can be configured as an interface between the logic circuit 102a on the first die 100a and external circuitry outside the first die 100a. In Figure 1AIn the example configuration of [the device], the I / O circuit 101a may include a buffer circuit 103a and an ESD protection circuit 104a. The buffer circuit 103a may include a receive circuit RX (also referred to as an "input circuit") and a transfer circuit TX (also referred to as an "output circuit"), and all of these circuits are electrically coupled to a pad 105a, which may be an I / O pin. In some embodiments, the buffer circuit 103b, the ESD protection circuit 104b, and the pad 105b of the second die 100b may correspond to the buffer circuit 103a, the ESD protection circuit 104a, and the pad 105a of the first die 100a. In some embodiments, the pad 105a may be interchangeable and is referred to as a metal pad, a pad pin, a bump pad, or a die-to-die pad.

[0138] The buffer circuit 103a may be used to strengthen and stabilize signals transmitted in and out of the die 100a. In some embodiments, the buffer circuit 103a may condition the signal, such as inverting it (e.g., an inverter buffer) or providing multiple states (e.g., a tri-state buffer). In some embodiments, the buffer circuit 103a may provide isolation between circuits, protecting the circuit from potential harmful effects of the connected circuits. In some embodiments, the buffer circuit 103a may be variable and is referred to as an ESD victim.

[0139] In some embodiments, the receive circuit RX in the buffer circuit 103a may be used to send the signal on the pad 105a to the logic circuit 102a. The receive circuit RX may be used to receive an input enable signal IE. The receive circuit RX may be enabled in response to the logic state of the input enable signal IE to send the signal on the pad 105a to the logic circuit 102a, and may be disabled in response to different logic states of the input enable signal IE to not send the signal on the pad 105a to the logic circuit 102a. The transfer circuit TX in the buffer circuit 103a may be used to send the signal output by the logic circuit 102a to the pad 105a. The transfer circuit TX may be used to receive an output enable signal OE. The transfer circuit TX may be enabled in response to the logic state of the output enable signal OE to send the signal output by the logic circuit 102a to the pad 105a, and may be disabled in response to different logic states of the output enable signal OE to not send the signal output by the logic circuit 102 to the pad 105a. Examples of the (multiple) signals input from or output to the pad 105a include, but are not limited to, data, power, clock, control, or the like. Examples of one or more circuits in at least one of the receive circuit RX or the transfer circuit TX include, but are not limited to, buffers, latches, level shifters, or the like.

[0140] In some embodiments, the ESD protection circuit 104a can be used to protect other circuits, including the logic circuit 102a electrically coupled to the pad 105a, from ESD events occurring on the pad 105a during the operation or processing of the first die 100a or the IC device 100. By way of example and not limitation, when an ESD event occurs, the ESD protection circuit 104a can employ diode-like components to clamp the voltage to a safe level, thereby preventing voltage spikes from reaching and damaging sensitive portions within the die 100a. In some embodiments, the ESD protection circuit 104a can be used to divert excessive current away from sensitive circuit components. Examples of the ESD protection circuit 104a include, but are not limited to, diodes, grounded-gate NMOS (ggNMOS), silicon-controlled rectifier (SCR), or the like. In some embodiments, the transistors in the ESD protection circuit 104a can be larger and / or have a different configuration than the functional or core transistors of the logic circuit 102a, enabling them to withstand and handle the high voltage and / or high current of an ESD event.

[0141] In some embodiments, the first die 100a is electrically coupled to the second die 100b at one or more die-to-die interconnects. Figure 1A Shown therein is a representative die-to-die interconnect that is electrically coupled to the pad 105a of the first die 100a and the corresponding pad 105b of the second die 100b. As a result, the pad 105a of the first die 100a is electrically coupled to the corresponding pad 105b of the second die 100b through the die-to-die interconnect. In some embodiments, the die-to-die interconnect can be a TSV in one or more of the dies in the IC device 100.

[0142] Figure 1C is Figure 1ACross-sectional view of a stacked IC device. Each of the first die 100a and the second die 100b may include a substrate 110, one or more devices DE above the substrate 110, a contact socket CP, a multi-level interconnect structure 200, and pads 105a / 105b. The substrate 110 may include wells WR (e.g., n-type wells or p-type wells). The device DE may include a gate structure G and source / drain regions SD on opposite sides of the gate structure. The device DE may be located above the well WR. The contact socket CP may land on the gate structure G and the source / drain regions SD of the device DE. The multi-level interconnect structure 200 may be formed above the contact socket CP. The multi-level interconnect structure 200 may include a plurality of metallization layers (or interconnect layers) stacked one above the other. Each of the metallization layers may include horizontally extending metal wires 204 and / or metal vias 206 extending vertically between the metal wires 204. The pads 105a / 105b are above the multi-level interconnect structure 200. The metallization layer (or interconnect layer) may include a dielectric layer surrounding the metal wires 204 and the metal vias 206. In some embodiments, the device DE is configured to form buffer circuits 103a / 103b and ESD protection circuits 104a / 104b, and the multi-level interconnect structure 200 may electrically connect the buffer circuits 103a~103b and the ESD protection circuits 104a / 104b to the pads 105a / 105b through the contact socket CP.

[0143] Figure 2AThe figure is a schematic block diagram showing the operation of the ESD protection circuit 104. The I / O circuit 101, the logic circuit 102, the buffer circuit 103, the ESD protection circuit 104, and the pad 105 may correspond to the I / O circuit 101a / 101b, the logic circuit 102a / 102b, the buffer circuit 103a / 103b, the ESD protection circuit 104a / 104b, and the pad 105a / 105b in the die 100a / 100b. The ESD protection circuit 104 may be formed by the diodes D1 and D2. The diode D1 is connected between the pad 105 and the low-power voltage line VSS, and the diode D2 is connected between the pad 105 and the high-power voltage line VDD, where the voltage of the high-power voltage line VDD is higher than the voltage of the low-power voltage line VSS. In some embodiments, the ESD power clamping circuit 106 is placed between the low-power voltage line VSS and the high-power voltage line VDD to provide a low-resistance path during an ESD event when needed. In some embodiments, the ESD power clamping circuit 106 is composed of an RC inverter and a BigFET. Through the ESD power clamping circuit 106, ESD protection can be achieved under ESD stresses from VDD to VSS (or VSS to VDD), as well as different ESD stress conditions from input / output to VDD / VSS, including the positive-to-VSS (PS) mode, the negative-to-VSS (NS) mode, the positive-to-VDD (PD) mode, and the negative-to-VDD (ND) mode. The PS mode, the NS mode, the PD mode, and the ND mode are respectively indicated by the paths PS, NS, PD, and ND. Therefore, the ESD protection circuit 104 and the ESD power clamping circuit 106 can provide effective protection for the logic circuit 102. In context, the logic circuits 102a, 102b, the buffer circuits 103a, 103b, the ESD protection circuits 104a, 104b, and the pads 105a, 105b in the first die 100a and the second die 100b (refer to Figures 1A to 1C ) may be respectively referred to as the logic circuit 102, the buffer circuit 103, the ESD protection circuit 104, and the pad 105. In some embodiments, both the first die 100a and the second die 100b (refer to Figures 1A to 1C ) may include the ESD power clamping circuit 106.

[0144] Figure 2B The figure Figure 2A shows the circuit diagram of the ESD protection circuit 104a. Figure 2C is Figure 2B a cross-sectional view of a part of the ESD protection circuit 104a. Figure 2D is Figure 2BCross-sectional view of another part of the ESD protection circuit 104a. Diode D1 can be the n-type device NDE in device DE (refer to Figure 1C ), where the gate structure G and the source / drain region SD of the n-type device NDE are connected to the pad 105, as shown in Figure 2C . Diode D2 can be the p-type device PDE in device DE (refer to Figure 1C ), where the gate structure G and the source / drain region SD of the p-type device are connected to the pad 105, as shown in Figure 2D .

[0145] In Figure 2C , an n-type heavily doped region N+ is formed in the substrate 110 and used as the source / drain region SD of the n-type device NDE. Also, a p-type heavily doped region P+ is formed in the substrate 110 and used as the p-type strap region PStrap that connects the p-type substrate 110 (or the p-type well region if present) to the low-power voltage line VSS.

[0146] In Figure 2D , an n-type well region NW is formed in the substrate 110. A p-type heavily doped region P+ is formed in the substrate 110 and used as the source / drain region SD of the p-type device PDE. Also, an n-type heavily doped region N+ is formed in the n-type well region NW and used as the n-type strap region Nstrap that connects the n-type well region NW to the high-power voltage line VDD.

[0147] Figure 3A is a schematic diagram of the IC device 100a according to some embodiments of the present disclosure. Figure 3B Illustrated Figure 3ASchematic configuration of multiple bits BT in an IC device. The annotation "F" in bit BT indicates the orientation of bit BT. Each of the bits BT bounded by boundary PrB includes substantially the same configuration. In some embodiments of the present disclosure, for the purpose of depicting the layout, some groupings / combinations of bits BT are multi-bit cells MBC, and the layout can be depicted by repeating the multi-bit cell MBC. In this embodiment, the multi-bit cell MBC includes a dual-bit BT, which for better illustration is annotated as bit BT1 and BT2. The annotation "F" in bit BT1 is opposite to the annotation "F" in bit BT2. This indicates that bit BT1 and bit BT2 are mirror-symmetrical, for example, along the boundary BR1 between bit BT1 and bit BT2. In other words, the layout of bit BT2 can be obtained by flipping the layout of bit BT1. With this symmetrical configuration, elements (e.g., n-type device NDE and p-type strap Pstrap) in the I / O circuits 101a of adjacent bits BT1 and BT2 can be closely arranged, thus saving the area of the I / O circuits 101a. Moreover, elements (e.g., n-type device NDE and p-type strap Pstrap) in the I / O circuits 101a of the two bits BT1 and BT2 can share an active region (e.g., fin), thus meeting the fin number of the ESC circuit according to the design rule check (DRC), while reducing the area of the I / O circuits 101a.

[0148] In this embodiment, the mirror-symmetrical bits BT1 and BT2 are arranged and aligned with each other along direction X, the pads 105a connected to the mirror-symmetrical bits BT1 and BT2 are arranged and aligned with each other along direction X, and are spaced apart from each other along direction X. In various embodiments, the pads 105a can have any suitable configuration embodiment. In some embodiments, the length L1 of the multi-bit cell MBC measured along a direction (e.g., direction X) substantially perpendicular to the extension direction of the boundary BR1 is greater than the length LY of the multi-bit cell MBC measured along a direction (e.g., direction Y) substantially parallel to the extension direction of the boundary BR1.

[0149] Figure 3C Illustration Figure 3A Layout of the IC device 100a. The layout of the IC device 100a may include an active region OD, an n-type well region NW, source / drain conductive structures VD, and an auxiliary structure PODE on the edge of the active region OD. In this layout, each of the p-type devices PDE includes an active region OD in the n-type well region NW and region PP, and each of the n-type devices NDE includes an active region OD outside the n-type well region NW and outside region PP. Region PP indicates a p-type heavily doped region P+ (refer to Figure 2C and Figure 2D ) and an n-type heavily doped region N+ (refer to Figure 2D andFigure 2C )'s position. For example, the p-type heavily doped region P+ will be located on the active region OD in the region PP, while the n-type heavily doped region N+ (refer to Figure 2C and Figure 2D ) will be located on the active region OD outside the region PP.

[0150] In Figure 3C , each of the bits BT1 and BT2 includes a transfer circuit TX, a receiving circuit RX, and an ESD protection circuit 104a. The transfer circuit TX, the receiving circuit RX, and the ESD protection circuit 104a are indicated by dashed boxes in Figure 3C . The transfer circuit TX may include at least one n-type device NDE and at least one p-type device PDE. The receiving circuit RX may include at least one n-type device NDE and at least one p-type device PDE. Also, the ESD protection circuit 104a may include at least one n-type device NDE and at least one p-type device PDE. In this embodiment, the n-type device NDE of the ESD protection circuit 104 of the bit BT1 may be placed adjacent to the n-type device NDE of the ESD protection circuit 104a of the bit BT2. With this configuration, the area of the ESD protection circuit 104a can be reduced, thereby saving the area of the I / O circuit 101a.

[0151] In Figure 3C , each of the bits BT (bits BT1 / BT2) may include at least one n-type strap Nstrap and at least one p-type strap PStrap. In the layout, each of the n-type straps Nstrap includes the active region OD in the n-type well region NW and outside the region PP, and each of the p-type straps PStrap includes the active region OD outside the n-type well region NW and in the region PP. In this embodiment, the p-type strap PStrap of the bit BT1 may be placed adjacent to the p-type strap PStrap of the bit BT2. With this configuration, the area of the p-type strap PStrap can be reduced, thereby saving the area of the entire circuit.

[0152] In Figure 3C , the areas of the transfer circuit TX, the receiving circuit RX, and the ESD protection circuit 104a are indicated by squares with dotted thick lines. The areas of the p-type strap PStrap, the n-type strap Nstrap, the p-type device PDE, and the n-type device NDE are indicated by squares with dotted lines. The horizontal strip with a dotted line extending across the entire multi-bit cell MBC may indicate the areas of the high-power rail VDD and the low-power rail VSS. The horizontal strip with a thick dotted line can be regarded as the actual metal wiring ML of the metallization layer M1 similar to the high-power rail VDD and the lower-power rail VSS.

[0153] Figure 3D is Figure 3CAn enlarged view of the n-type region NStrap in the ESD protection circuit 104a. Figure 3E Is Figure 3C An enlarged view of the p-type region Pstarp in the ESD protection circuit 104a. Figure 3F Is Figure 3C An enlarged view of the n-type device NDE in the ESD protection circuit 104a. Figure 3G Is Figure 3C An enlarged view of the p-type device PDE in the ESD protection circuit 104a. The layout of the IC device 100a may include contacts MD on the heavily doped regions P+ / N+ above the active region OD, a conductive structure VDR on the contacts MD, and power rails VSS and VDD above the conductive structure VDR. The layout of the IC device 100a may further include a gate structure G (corresponding to the patterns of the gate structures 130 and 170) and a gate via VG above the gate structure G. In this embodiment, the power rails VSS and VDD are some of the metal wirings 204 in the bottom metallization layer of the MLI structure 200. As Figure 3D shown, the n-type region NStrap (e.g., the heavily doped region N+) may be connected to the high power rail VDD, for example, through the contacts MD and the conductive structure VDR. Figure 3D The arrow in Figure 3D indicates the current from the high power rail VDD to the n-type region NStrap. As Figure 3E shown, the p-type region Pstarp (e.g., the heavily doped region P+) may be connected to the low power rail VSS, for example, through the contacts MD and the conductive structure VDR.

[0154] The auxiliary structure PODE may also be referred to as a polysilicon structure on the diffusion edge. The auxiliary structure PODE may be formed above the edge of the active region OD. In some embodiments, the auxiliary structure PODE does not constitute any functional features in one or more active devices formed in the corresponding active region OD. In Figure 3D and Figure 3E , by using the configuration of the auxiliary structure PODE, there may be no functional gate structure G adjacent to the n-type region NStrap (e.g., the heavily doped region N+) and the p-type region Pstarp (e.g., the heavily doped region P+) above the active region OD. In Figure 3F , the n-type device NDE may include a gate structure G and a heavily doped region N+ above the active region OD. In Figure 3G , the p-type device PDE may include a gate structure G and a heavily doped region P+ above the active region OD.

[0155] Figure 4 Is a schematic diagram of an IC device according to some embodiments of the present disclosure. The details of this embodiment are similar to Figures 3A to 3CThe details shown in the embodiments are different in that the mirror-symmetric bits BT1 and BT2 are arranged and aligned with each other along the direction X, the pads 105a connected to the mirror-symmetric bits BT1 and BT2 are arranged and aligned with each other along the direction Y, and are spaced apart from each other along the direction Y. The direction Y may be substantially perpendicular to the direction X. Other details of this embodiment are similar to Figures 3A to 3C the details, and thus will not be repeated here.

[0156] Figure 5A is a schematic diagram of an IC device according to some embodiments of the present disclosure. Figure 5B Illustration Figure 5A The schematic configuration of multiple bits in the IC device of. The details of this embodiment are similar to Figures 3A to 3C the details shown in the embodiments of. The difference is that, in this embodiment, the multi-bit unit MBC includes four bits BT. For better illustration, the four bits BT are annotated as bits BT1 to BT4. The annotation "F" in bit BT1 is opposite to the annotation "F" in bit BT2, the annotation "F" in bit BT2 is opposite to the annotation "F" in bit BT3, and the annotation "F" in bit BT3 is opposite to the annotation "F" in bit BT4. This indicates that bit BT1 and bit BT2 are mirror-symmetric along the boundary BR1 between bit BT1 and bit BT2, for example; bit BT2 and bit BT3 are mirror-symmetric along the boundary BR2 between bit BT2 and bit BT3, for example; and bit BT3 and bit BT4 are mirror-symmetric along the boundary BR3 between bit BT3 and bit BT4, for example. Through this symmetric configuration, the components (e.g., n-type device NDE and p-type region Pstrap) in the I / O circuit 101a of adjacent bits BT1 and BT2 can be closely arranged, the components (e.g., transfer circuit TX, receive circuit RX, and p-type region Pstrap) in the I / O circuit 101a of adjacent bits BT2 and BT3 can be closely arranged, and the components (e.g., n-type device NDE and p-type region Pstrap) in the I / O circuit 101a of adjacent bits BT3 and BT4 can be closely arranged, thereby saving the area of the I / O circuit 101a. In this embodiment, the mirror-symmetric bits BT1 to BT4 are arranged and aligned with each other along the direction X, and the pads 105a connected to the mirror-symmetric bits BT1 to BT4 are arranged spaced apart from each other. In various embodiments, the pads 105a may have any suitable configuration embodiment.

[0157] Figure 5C Shows Figure 5A the layout of the IC device of. In Figure 5C each of bits BT1 to BT4 includes a transfer circuit TX, a receive circuit RX, and an ESD protection circuit 104a. The transfer circuit TX, the receive circuit RX, and the ESD protection circuit 104a are in Figure 5CIn the figure, it is represented by a dashed square. The transfer circuit TX may include at least one n-type device NDE and at least one p-type device PDE. The receiving circuit RX may include at least one n-type device NDE and at least one p-type device PDE. Also, the ESD protection circuit 104a may include at least one n-type device NDE and at least one p-type device PDE. In this embodiment, the n-type device NDE of the ESD protection circuit 104a of bit BT1 may be placed adjacent to the n-type device NDE of the ESD protection circuit 104a of bit BT2. The n-type device NDE of the ESD protection circuit 104a of bit BT3 may be placed adjacent to the n-type device NDE of the ESD protection circuit 104a of bit BT4. Through this configuration, the area of the ESD protection circuit 104a can be reduced, thereby saving the area of the I / O circuit 101a.

[0158] In Figure 5C each of bits BT1 to BT4 may include a plurality of n-type stripes Nstrap and a plurality of p-type stripes PStrap. In the layout, each of the n-type stripes Nstrap includes an active region OD in the n-type well region NW and outside the region PP, and each of the p-type stripes PStrap includes an active region OD outside the n-type well region NW and in the region PP. In this embodiment, one of the p-type stripes PStrap of bit BT1 may be placed adjacent to one of the p-type stripes of bit BT2. One of the p-type stripes PStrap of bit BT3 may be placed adjacent to one of the p-type stripes PStrap of bit BT4. One of the p-type stripes PStrap of bit BT2 may be placed adjacent to one of the p-type stripes PStrap of bit BT3. Through this configuration, the area of the p-type stripes PStrap can be reduced, thereby saving the area of the entire circuit.

[0159] Figure 6A is a schematic diagram of an IC device 100a according to some embodiments of the present disclosure. Figure 6B The figure shows Figure 6A a schematic configuration of multiple bits in the IC device shown. The details of this embodiment are similar to Figures 3A to 3CThe details shown in the embodiments are different in that, in this embodiment, the multi-bit cell MBC includes four bits BT. For better illustration, the four bits BT are annotated as bits BT1 to BT4. The annotation "F" in bit BT1 is opposite to the annotation "F" in bit BT2, and the annotation "F" in bit BT3 is opposite to the annotation "F" in bit BT4. This indicates that bit BT1 and bit BT2 are mirror-symmetrical, for example, along the boundary BR1 between bit BT1 and bit BT2; and bit BT3 and bit BT4 are mirror-symmetrical, for example, along the boundary BR2 between bit BT3 and bit BT4. Through this symmetrical configuration, the components (e.g., n-type device NDE and p-type region Pstrap) in the I / O circuit 101a of adjacent bits BT1 and BT2 can be closely arranged, and the components (e.g., n-type device NDE and p-type region Pstrap) in the I / O circuit 101a of adjacent bits BT3 and BT4 can be closely arranged, thereby saving the area of the I / O circuit 101a. In this embodiment, the mirror-symmetrical bits BT1 and BT2 are arranged along the direction X and aligned with each other, the mirror-symmetrical bits BT3 and BT4 are arranged along the direction X and aligned with each other, bit BT1 and bit BT3 are arranged along the direction Y and aligned with each other, and bit BT2 and bit BT4 are arranged along the direction Y and aligned with each other. The pads 105a connected to the mirror-symmetrical bits BT1 to BT4 are arranged at intervals from each other. In various embodiments, the pads 105a can have any suitable configuration embodiment.

[0160] Figure 6C Show Figure 6A The layout of the IC device 100a of. In Figure 6C Among them, each of the bits BT1 to BT4 includes a transfer circuit TX, a receiving circuit RX, and an ESD protection circuit 104a. The transfer circuit TX, the receiving circuit RX, and the ESD protection circuit 104a are indicated by dashed boxes in Figure 6C Among them. The transfer circuit TX may include at least one n-type device NDE and at least one p-type device PDE. The receiving circuit RX may include at least one n-type device NDE and at least one p-type device PDE. And, the ESD protection circuit 104a may include at least one n-type device NDE and at least one p-type device PDE. In this embodiment, the n-type device NDE of the ESD protection circuit 104a of bit BT1 can be placed adjacent to the n-type device NDE of the ESD protection circuit 104a of bit BT2. The n-type device NDE of the ESD protection circuit 104a of bit BT3 can be placed adjacent to the n-type device NDE of the ESD protection circuit 104a of bit BT4. Through this configuration, the area of the ESD protection circuit 104a can be reduced, thereby saving the area of the I / O circuit 101a.

[0161] In Figure 6CAmong them, each of the bits BT1 to BT4 may include a plurality of n-type strap regions Nstrap and a plurality of p-type strap regions PStrap. In the layout, each of the n-type strap regions Nstrap includes an active region OD in the n-type well region NW and outside the region PP, and each of the p-type strap regions PStrap includes an active region OD outside the n-type well region NW and in the region PP. In this embodiment, one of the p-type strap regions PStrap of bit BT1 may be placed adjacent to one of the p-type strap regions of bit BT2. One of the p-type strap regions PStrap of bit BT3 may be placed adjacent to one of the p-type strap regions PStrap of bit BT4. Through this configuration, the area of the p-type strap region PStrap can be reduced, thereby saving the area of the entire circuit.

[0162] Compare Figure 3C , Figure 5C , and Figure 6C in the multi-bit cell MBC in Figure 5C the length L2 of the four-bit cell MBC in is less than Figure 3C twice the length L1 of the two-bit cell in Figure 6C And the length L3 of the four-bit cell MBC in is less than Figure 3C the length L1 of the two-bit cell MBC in. Configuring more bits (e.g., four bits) with repeating units can save more length / space per bit than configuring fewer bits (e.g., two bits) with repeating units.

[0163] Figure 7 FIG. shows a schematic configuration of a plurality of bits in an IC device according to some embodiments of the present disclosure. The details of this embodiment are similar to Figures 6A to 6CThe details shown in the embodiment of [description of related embodiment] are different in that, in this embodiment, the multi-bit cell MBC includes six bits BT. For better illustration, the six bits BT are annotated as bits BT1 to BT6. In this embodiment, bits BT1, BT2, and BT5 are arranged and aligned with each other along the X direction, bits BT3, BT4, and BT6 are arranged and aligned with each other along the X direction, bit BT1 and BT3 are arranged and aligned with each other along the Y direction, bit BT2 and BT4 are arranged and aligned with each other along the Y direction, and bit BT5 and BT6 are arranged and aligned with each other along the Y direction. The annotation "F" in BT2 is opposite to the annotation "F" in bits BT1 and BT5, and the annotation "F" in BT4 is opposite to the annotation "F" in bits BT3 and BT6. This indicates that bit BT2 is mirror-symmetric with bits BT1 and BT5, for example, along the boundary BR1 between bit BT1 and BT2 and the boundary BR3 between bit BT2 and BT5; and bit BT4 is mirror-symmetric with bits BT3 and BT6, for example, along the boundary BR2 between bit BT3 and BT4 and the boundary BR4 between bit BT4 and BT6. Through this symmetric configuration, the components in the I / O circuit 101a of adjacent two-bit cells can be closely arranged, thus saving the area of the I / O circuit 101a. Other details of this embodiment are similar to those described above, so they will not be repeated here.

[0164] Figure 8 Schematic configurations of multiple bits in an IC device according to some embodiments of the present disclosure. The details of this embodiment are similar to Figures 6A to 6CThe details shown in the embodiments of [reference] are different in that, in this embodiment, the multi-bit unit MBC includes six bits BT. For better illustration, the six bits BT are annotated as bits BT1 to BT6. In this embodiment, bits BT1 and BT2 are arranged along the X direction and aligned with each other, bits BT3 and BT4 are arranged along the X direction and aligned with each other, bits BT5 and BT6 are arranged along the X direction and aligned with each other, bits BT1, BT3, and BT5 are arranged along the Y direction and aligned with each other, and bits BT2, BT4, and BT6 are arranged along the Y direction and aligned with each other. The annotation "F" in bit BT1 is opposite to the annotation "F" in bit BT2, the annotation "F" in bit BT3 is opposite to the annotation "F" in bit BT4, and the annotation "F" in bit BT5 is opposite to the annotation "F" in bit BT6. This indicates that bit BT1 and bit BT2 are mirror symmetric along the boundary BR1 between bit BT1 and bit BT2, for example; bit BT3 and bit BT4 are mirror symmetric along the boundary BR2 between bit BT3 and bit BT4, for example; bit BT5 and bit BT6 are mirror symmetric along the boundary BR3 between bit BT5 and bit BT6, for example. With this symmetric configuration, the components in the I / O circuits 101a of adjacent double bits can be closely arranged, thus saving the area of the I / O circuits 101a. Other details of this embodiment are similar to those described above, so they will not be repeated here.

[0165] Figure 9 FIG. shows a schematic configuration of multiple bits in an IC device according to some embodiments of the present disclosure. The details of this embodiment are similar to Figures 6A to 6C the details shown in the embodiments of [reference], different in that, in this embodiment, the multi-bit unit MBC includes eight bits BT. For better illustration, the eight bits BT are annotated as bits BT1 to BT8. In this embodiment, bits BT1, BT2, BT5, and BT6 are arranged along the direction X and aligned with each other, bits BT3, BT4, BT7, and BT8 are arranged along the direction X and aligned with each other; bit BT1 and bit BT3 are arranged along the direction Y and aligned with each other, bit BT2 and bit BT4 are arranged along the direction Y and aligned with each other, bit BT5 and bit BT7 are arranged along the direction Y and aligned with each other, and bit BT6 and bit BT8 are arranged along the direction Y and aligned with each other. The annotation "F" in bits BT1 to BT8 indicates that two adjacent ones among bits BT1 to BT8 are mirror symmetric to each other along one of the boundaries BR1 to BR6 between the two. With this symmetric configuration, the components in the I / O circuits 101a of adjacent double bits can be closely arranged, thus saving the area of the I / O circuits 101a. Other details of this embodiment are similar to those described above, so they will not be repeated here.

[0166] Figure 10Schematic configuration of multiple bits in an IC device according to some embodiments of the present disclosure. Details of this embodiment are similar to Figures 6A to 6C the details shown in the embodiment of, except that, in this embodiment, the multi-bit cell MBC includes eight bits BT. For better illustration, the eight bits BT are annotated as bits BT1 to BT8. In this embodiment, bits BT1 and BT2 are arranged along the X direction and aligned with each other, bits BT3 and BT4 are arranged along the X direction and aligned with each other, bits BT5 and BT6 are arranged along the X direction and aligned with each other, and bits BT7 and BT8 are arranged along the X direction and aligned with each other; bits BT1, BT3, BT5, BT7 are arranged along the Y direction and aligned with each other, and bits BT2, BT4, BT6, BT8 are arranged along the Y direction and aligned with each other. The annotation "F" in bits BT1 to BT8 indicates that bits BT1 / BT3 / BT5 / BT7 and bits BT2 / BT4 / BT6 / BT8 are mirror symmetric to each other along the boundaries BR1 / BR2 / BR3 / BR4 between bits BT1 / BT3 / BT5 / BT7 and bits BT2 / BT4 / BT6 / BT8. Through this symmetric configuration, the components in the I / O circuit 101a of adjacent double bits can be closely arranged, thereby saving the area of the I / O circuit 101a. Other details of this embodiment are similar to those described above, so they will not be repeated here.

[0167] Figures 11A to 15B Schematic layout and cross-sectional view of an integrated circuit structure at an intermediate stage of the manufacturing process according to some embodiments of the present disclosure. Figure 11A , Figure 12A , Figure 13A , Figure 14A , and Figure 15A are layouts of an integrated circuit structure at an intermediate stage of the manufacturing process according to some embodiments of the present disclosure. Figure 11A , Figure 12A , Figure 13A , Figure 14A , and Figure 15A The layout corresponds to the layout of the multi-bit cell MBC as shown in Figure 3C . In some embodiments, Figure 11A , Figure 12A , Figure 13A , Figure 14A , and Figure 15A The layout can be regarded as a top view of the integrated circuit structure. Figure 11B , Figure 12B , Figure 13B , Figure 14B , and Figure 15B Illustrations include respectively along Figure 11A , Figure 12A , Figure 13A , Figure 14A , andFigure 15A Cross-sectional views of regions RA, RB, RC, and RD taken along lines A-A, B-B, C-C, and D-D in Figure 12C and Figure 14C respectively illustrate cross-sectional views taken along line Y-Y in Figure 12C , Figure 14C It is understood that additional steps may be provided before, during, and after the steps shown in Figures 11A to 15B , and for additional embodiments of the method, some of the following steps may be replaced or eliminated. The order of operations / processes may be interchanged. Regions RA, RB, RC, and RD respectively correspond to regions of p-type device PDE, p-type strap PStrap, n-type device NDE in the ESD protection circuit, and n-type strap NStrap, as shown in Figure 15A .

[0168] Refer to Figure 11A and Figure 11B . A substrate 110 is provided, and an isolation structure 120 is formed in the substrate 110. In some embodiments, the substrate 110 may be a semiconductor substrate, such as a bulk silicon substrate, a germanium substrate, a compound semiconductor substrate, or other suitable substrates. The substrate 110 may include an epitaxial layer overlying a bulk semiconductor, a silicon-germanium layer overlying bulk silicon, a silicon layer overlying silicon-germanium, or a semiconductor-on-insulator (SOI) structure. The substrate 110 may be doped with impurity ions as appropriate such that it is lightly n-type or lightly p-type. For example, an n-type well region NW is formed in the substrate 110.

[0169] An isolation structure 120 is formed in the substrate 110 to separate and electrically isolate a plurality of active regions OD in the substrate 110 from each other. As shown in Figure 11A , the active regions OD extend along the X direction, and the isolation structure 120 surrounds the active regions OD. The isolation structure 120 may include a shallow trench isolation (STI) region, as shown. For example, the formation of the isolation structure 120 may include etching trenches in the substrate 110 and then filling the trenches with a dielectric material (such as an oxide). A planarization process may then be used to remove the excess dielectric, thereby confining this dielectric to the trench boundaries. In this embodiment, the isolation structure 120 may have a top surface flush with the top surface of the active regions OD. In some other embodiments, the active regions OD may extend above the top surface of the isolation structure 120, and the active regions OD may be referred to as semiconductor fins surrounded by the isolation structure 120.

[0170] Refer to Figures 12A to 12C . A plurality of dummy gate structures 130 are formed around the active regions OD of the substrate 110. As shown in Figure 12AAs shown, dummy gate structure 130 extends along the Y direction across the active region OD and the isolation structure 120. In some embodiments, each of the dummy gate structures 130 includes a dummy gate 134 and a gate dielectric 132 underlying the dummy gate 134. The dummy gate 134 may include polysilicon (poly-Si) or polysilicon germanium (poly-SiGe). Additionally, the dummy gate 134 may be doped polysilicon with uniform or non-uniform doping. The gate dielectric 132 may include, for example, high-k dielectric data such as metal oxides, metal nitrides, metal silicates, transition metal oxides, transition metal nitrides, transition metal silicates, oxynitrides of metals, metal aluminates, zirconium silicate, zirconium aluminate, or a combination thereof.

[0171] In some embodiments, the dummy gate structure 130 may be formed by, for example, forming a stack of a gate dielectric layer and a dummy gate material layer over the substrate 110. A patterned mask is formed over the stack of the gate dielectric layer and the dummy gate material layer. The patterned mask may be a hard mask (HM) layer patterned by a suitable optical lithography process. For example, the patterned mask may include silicon nitride, silicon oxynitride, analogs, or a combination thereof. Subsequently, one or more etching processes, such as one or more dry plasma etching processes or one or more wet etching processes, may be used to pattern the gate dielectric layer and the dummy gate material layer. During the etching process, the patterned mask may act as an etching mask. At least one parameter in the tunable patterning (or etching) recipe, such as the etchant, etching temperature, etching solution concentration, etching pressure, source power, radio frequency (RF) bias voltage, etchant flow rate. For example, a dry etching process such as plasma etching may be used to etch the dummy gate material layer and the gate dielectric layer until the active region OD and the isolation structure 120 are exposed.

[0172] Gate spacers 140 are formed on opposite sidewalls of the dummy gate structure 130. The formation of the gate spacers 140 may include conformally depositing a spacer material layer on the top wall and sidewalls of the dummy gate structure 130, followed by an anisotropic etching process. The spacer material layer may include a dielectric material such as silicon oxide, silicon nitride, silicon oxynitride, SiCN film, silicon oxycarbide, SiOCN film, and / or a combination thereof. The portion of the spacer material layer directly over the dummy gate structure 130 may be completely removed by this anisotropic etching process. For simplicity, the portion of the spacer material layer on the sidewalls of the dummy gate structure 130 may be retained, thereby forming gate spacers denoted as gate spacers 140.

[0173] Reference Figure 13A and Figure 13BAbove the active region OD, a p-type heavily doped region P+ and an n-type heavily doped region N+ are formed. In some embodiments, a second portion of the active region OD not covered by the gate spacer 140 and the dummy gate structure 130 may be doped with a p-type dopant, such as boron; an n-type dopant, such as phosphorus or arsenic; and / or other suitable dopants including compositions thereof, for example, by a suitable ion implantation process, to form the p-type heavily doped region P+ and the n-type heavily doped region N+. The n-type heavily doped region N+ in the substrate 110 may be used as the source / drain region SD of an n-type device. The p-type heavily doped region P+ in the n-well region NW may be used as the source / drain region SD of a p-type device. The n-type heavily doped region N+ in the n-well region NW may be used as an n-type band region NStrap to bias the n-well region NW. The p-type heavily doped region P+ in the substrate 110 may be used as a p-type band region PStrap to bias the substrate 110.

[0174] In some embodiments, the p-type heavily doped region P+ and the n-type heavily doped region N+ are source / drain epitaxial structures formed on opposite sides of the dummy gate structure 130. The source / drain epitaxial structures may include Ge, Si, GaAs, AlGaAs, SiGe, GaAsP, SiP, or other suitable materials. The source / drain epitaxial structures may be in-situ doped during the epitaxial process by introducing doping species including: a p-type dopant, such as boron or BF2; an n-type dopant, such as phosphorus or arsenic; and / or other suitable dopants including compositions thereof. If the source / drain epitaxial structures are not in-situ doped, an implantation process (i.e., a junction implantation process) is performed to dope the source / drain epitaxial structures. The source / drain epitaxial structures may be formed by performing an epitaxial growth process that provides epitaxial data on the exposed surface of the active region OD. Suitable epitaxial processes include CVD deposition techniques (e.g., vapor-phase epitaxy (VPE) and / or ultra-high vacuum CVD (UHV-CVD)), molecular beam epitaxy, and / or other suitable processes. The epitaxial growth process may use gases and / or liquid precursors that interact with the composition of the semiconductor material of the active region OD.

[0175] After forming the p-type heavily doped region P+ and the n-type heavily doped region P+ (e.g., source / drain regions SD, n-type strap region NStrap, and p-type strap region PStrap), an interlayer dielectric (ILD) 160 is formed above the substrate 110 and around the source / drain regions SD. The ILD 160 may include silicon oxide, silicon oxynitride, or other suitable materials. The ILD 160 includes a single layer or multiple layers. The ILD 160 can be formed by suitable techniques such as CVD or ALD. A chemical mechanical polishing (CMP) process can be performed to remove the excess portion of the ILD 160 until reaching the dummy gate structure 130. After the chemical mechanical polishing (CMP) process, the dummy gate structure 130 is exposed from the ILD 160. In some embodiments, a contact etch stop layer (CESL) can be formed blanketly above the substrate 110 before forming the ILD 160. In some instances, the CESL includes a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, and / or other suitable materials having different etch selectivities from the ILD 160.

[0176] Reference Figures 14A to 14C . A replacement gate (RPG) process scheme is adopted. The dummy gate structure 130 in the regions RA and RC is replaced with a high-k / metal gate structure 170. For example, the dummy gate structure 130 is removed (see Figure 13A and Figure 13B ) to form a plurality of gate trenches. The dummy gate structure 130 is removed by a selective etching process including selective wet etching or selective dry etching, and the substantially vertical profile of the gate spacers 140 is maintained. The gate trenches expose portions of the active region OD. Then, the high-k / metal gate structures 170 are respectively formed in the gate trenches and cover the active region OD. The high-k / metal gate structure 170 may include a gate dielectric layer 172 and a metal-containing layer 174 above the gate dielectric layer 172.

[0177] The gate dielectric layer 172 may include an interface layer and a high-k dielectric layer above the interface layer. The interface layer may include, for example, silicon oxide formed by a thermal oxidation process. As used and described herein, the high-k dielectric layer includes a dielectric material having a high dielectric constant (e.g., greater than the dielectric constant of thermally oxidized silicon (~3.9)). The high-k dielectric layer may include high-k dielectric layers such as tantalum, hafnium, titanium, lanthanum, aluminum, and their carbide, silicide, nitride, boride compositions. The high-k dielectric layer can be formed by ALD, PVD, CVD, oxidation, and / or other suitable methods.

[0178] The metal-containing layer 174 may include a metal, a metal alloy, a metal carbide, a metal silicide, a metal silicon carbide, an alloy carbonitride, and / or a metal boride. In some embodiments, the metal-containing layer 174 may include a single layer or an alternative multi-layer structure, such as various combinations of a metal layer with a work function to enhance device performance (work function metal layer), a liner layer, a wetting layer, an adhesion layer, and a conductive layer of a metal, a metal alloy, or a metal silicide. For example, the metal-containing layer 174 may be an n-type or p-type work function layer. Exemplary p-type work function metals include TiN, TaN, Ru, Mo, Al, WN, ZrSi2, MoSi2, TaSi2, NiSi2, WN, other suitable p-type work function materials, or combinations thereof. Exemplary n-type work function metals include Ti, Ag, TaAl, TaAlC, TiAlN, TaC, TaCN, TaSiN, Mn, Zr, other suitable n-type work function materials, or combinations thereof. The work function layer may include multiple layers. The (multiple) work function layers may be deposited by CVD, PVD, electroplating, and / or other suitable processes. In some embodiments, the multi-layer metal-containing layer 174 may include the same or different data.

[0179] In some embodiments, in regions RB and RD, some of the dummy gate structures 130 in the active region OD are replaced with a suitable isolation assist structure PODE to disrupt the active region OD. The isolation assist structure PODE may include a suitable dielectric material. In some other embodiments, to disrupt the active region OD, the dummy gate structures 130 in regions RB and RD may be replaced with floating high-k / metal gate structures separated from the high-k / metal gate structures 170 in regions RA and RC, thereby omitting a suitable isolation assist structure PODE. In some other embodiments, to disrupt the active region OD, the isolation structure 120 may be configured according to the assist structure PODE in the layout, thereby omitting a suitable isolation assist structure PODE.

[0180] Although the p-type strip region PStrap of bit BT1 and the p-type strip region PStrap of bit BT2 may share the same active region OD, the isolation assist structure PODE may separate the p-type strip region PStrap of bit BT1 from the p-type strip region PStrap of bit BT2. Since the isolation assist structure PODE is formed by replacing the dummy gate structure 130 with a dielectric material, the space between the p-type strip region PStrap of bit BT1 and the p-type strip region PStrap of bit BT2 sharing the same active region OD may be less than twice the unit polysilicon pitch CPP. The unit polysilicon pitch CPP is the center-to-center pitch of every two adjacent dummy gate structures 130. In context, the unit polysilicon pitch CPP may also be referred to as the gate pitch.

[0181] Reference Figure 15A and Figure 15B An ILD 180 is formed above the ILD 160 and covers the high-k / metal gate structure 170, and the contact MD is formed above the heavily doped regions P+ and N+. The ILD 180 may include silicon oxide, silicon oxynitride, or other suitable materials. The ILD 180 includes a single layer or multiple layers. The ILD 180 may be formed by suitable techniques such as CVD or ALD.

[0182] The contact MD may also be referred to as a contact socket. In some embodiments, the contact formation step includes etching contact openings through the ILD 180 and the ILD 160 to expose the surfaces of the heavily doped regions P+ and N+, and depositing one or more metal materials to fill the contact openings. A CMP process may be performed to remove the excess metal materials outside the contact openings while leaving the metal materials in the contact openings to serve as the contact MD. The one or more metal materials may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, the like, or a combination thereof. The one or more metal materials may be deposited by suitable deposition techniques (e.g., CVD, PVD, ALD, the like, or a combination thereof). In some other embodiments, a metal silicide may be formed between the contact MD and the underlying heavily doped regions P+ and N+ to reduce the contact resistance.

[0183] An ILD 190 is formed above the contact MD, and conductive structures VD and VDR are formed in the ILD 190 and above the contact MD. The ILD 190 may include silicon oxide, silicon oxynitride, or other suitable materials. The ILD 190 includes a single layer or multiple layers. The ILD 190 may be formed by suitable techniques such as CVD or ALD. In some embodiments, the formation step of the conductive structures VD and VDR includes etching openings through the ILD 190 to expose the surface of the contact MD, and depositing one or more metal materials to fill the openings. A CMP process may be performed to remove the excess metal materials outside the contact openings while leaving the metal materials in the openings to serve as the conductive structures VD and VDR. The one or more metal materials may include W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, the like, or a combination thereof. The one or more metal materials may be deposited by suitable deposition techniques (e.g., CVD, PVD, ALD, the like, or a combination thereof).

[0184] After the conductive structures VD and VDR are formed, a multilayer interconnection (MLI) structure 200 is formed over the substrate 110. The MLI structure 200 may include at least three metallization layers. The number of metallization layers may vary according to the design specifications of the integrated circuit structure. Each metallization layer includes one or more inter-metal dielectric (IMD) layers, one or more horizontal interconnections extending horizontally in the IMD layer, and one or more vertical interconnections extending vertically in the IMD layer. For example, a metallization layer includes an IMD layer 202, a horizontal interconnection (e.g., a metal wire 204), and a vertical interconnection (e.g., a metal via 206). The metallization layers may be formed using, for example, a single damascene process, a dual damascene process, the like, or a combination thereof. In some embodiments, the IMD layer 202 may include a low-k dielectric material having a k value (e.g., less than about 4.0 or even 2.0). The metal wire 204 and the via 206 may include a metal material such as W, Ru, Co, Cu, Ti, TiN, Ta, TaN, Mo, Ni, a composition, or the like.

[0185] The conductive structure VD contacts the metal wire 204 of the MLI structure 200 to achieve a signal / power electrical connection to the source / drain region SD. The metal wire 204 of the MLI structure 200 may include a high-power rail VDD and a lower-power rail VSS. The conductive structure VDR contacts the high-power rail VDD and the lower-power rail VSS to achieve a power electrical connection of the high-power rail VDD and the lower-power rail VSS to the n-type band region NStrap and the p-type band region PStrap. Accordingly, the n-type band region NStrap is connected to the high-power rail VDD, and the p-type band region PStrap is connected to the lower-power rail VSS. In some embodiments, as Figure 15A viewed from a top view of the layout shown in, the conductive structure VDR may be an elongated rectangular shape. A pad 105 may be formed over the MLI structure 200. The pad 105 may be electrically connected to the transfer circuit TX, the receiving circuit RX, and the ESD protection circuit 104a through the metal wire 204 and the via 206, the conductive structures VD and VG.

[0186] Reference Figure 16 . Figure 16FIG. 0 is a schematic diagram of an electronic design automation (EDA) system according to some embodiments of the present disclosure. According to one or more embodiments, the method of generating a design layout (e.g., the layout as described above) described herein is implementable, for example, using the EDA system 1600 according to some embodiments. At least the I / O circuits 101a, 101b, 101c, and / or 101d are fabricated from a layout design corresponding to an integrated circuit. In some embodiments, the EDA system 1600 is a computing device capable of performing one or more automatic placement & routing (APR) operations. The EDA system 1600 includes a hardware processor 1602 and a non-transitory computer-readable storage medium 1604. The computer-readable storage medium 1604 is encoded with (i.e., stores) a set of executable instructions 1606, a design layout 1607, a design rule check (DRC) group 1609, or any intermediate data for executing the instruction set. Each design layout 1607 may include a graphical representation of an integrated die, such as, for example, a GSII file. Each DRC group 1609 may include a list of design rules specific to a semiconductor process selected for fabricating the design layout 1607. The execution of the instructions 1606, the design layout 1607, and the DRC group 1609 by the hardware processor 1602 (at least in part) represents the EDA tool implementing, according to one or more embodiments, some or all of the processes and / or methods described herein (hereinafter referred to as the recited processes and / or methods).

[0187] The processor 1602 is electrically coupled to the computer-readable storage medium 1604 via a bus 1608. The processor 1602 is also electrically coupled to an I / O interface 1610 via the bus 1608. A network interface 1612 is also electrically connected to the processor 1602 via the bus 1608. The network interface 1612 is connected to a network 1614 such that the processor 1602 and the computer-readable storage medium 1604 can be connected to external components via the network 1614. The processor 1602 is configured to execute the instructions 1606 encoded in the computer-readable storage medium 1604 so that the EDA system 1600 can be used to perform some or all of the recited processes and / or methods. In one or more embodiments, the processor 1602 is a central processing unit (CPU), a multi-processor, a distributed processing system, an application specific integrated circuit (ASIC), and / or a suitable processing unit.

[0188] In one or more embodiments, the computer-readable storage medium 1604 is an electronic, magnetic, optical, electromagnetic, infrared, and / or semiconductor system (or device or apparatus). For example, the computer-readable storage medium 1604 includes semiconductor or solid state memory, magnetic tape, removable computer disks, random access memory (RAM), read-only memory (ROM), rigid disks, and / or optical disks. In one or more embodiments that use optical disks, the computer-readable storage medium 1604 includes compact disk-read only memory (CD-ROM), compact disk-read / write (CD-R / W), and / or digital video disc (DVD).

[0189] In one or more embodiments, the computer-readable storage medium 1604 stores instructions 1606, design layout 1607 (e.g., including the layout of I / O circuits 101a, 101b, 101c, and / or 101d as described previously), and DRC set 1609, to enable the EDA system 1600 (where such execution represents (at least in part) an EDA tool) to be used to perform part or all of the processes and / or methods mentioned. In one or more embodiments, the storage medium 1604 also stores information that helps to perform part or all of the processes and / or methods mentioned.

[0190] The EDA system 1600 includes an I / O interface 1610. The I / O interface 1610 is coupled to an external circuit system. In one or more embodiments, the I / O interface 1610 includes a keyboard, keypad, mouse, trackball, trackpad, touch screen, and / or cursor direction keys for communicating information and commands to the processor 1602.

[0191] The EDA system 1600 also includes a network interface 1612 coupled to the processor 1602. The network interface 1612 allows the EDA system 1600 to communicate with a network 1614 to which one or more other computer systems are connected. The network interface 1612 includes a wireless network interface, such as Bluetooth, WIFI, WiMAX, GPRS, or WCDMA; or a wired network interface, such as ETHERNET, USB, or IEEE-1388. In one or more embodiments, part or all of the processes and / or methods mentioned are implemented in two or more EDA systems 1600.

[0192] The EDA system 1600 is configured to receive information through the I / O interface 1610. The information received through the I / O interface 1610 includes one or more of the following: instructions, data, design rules, standard cell libraries, and / or other parameters for processing by the processor 1602. The information is transmitted to the processor 1602 via the bus 1608. The EDA system 1600 is configured to receive information related to the user interface (UI) 1616 through the I / O interface 1610. The information is stored in the computer-readable medium 1604 as the UI 1616.

[0193] Figure 16 Also illustrated are manufacturing tools associated with the EDA system 1600. For example, the mask room 1630 receives a design layout from the EDA system 1600 via, for example, the network 1614, and the mask room 1630 has a mask manufacturing tool 1632 (e.g., a mask writer) for manufacturing one or more masks (e.g., masks for manufacturing the I / O circuits 101a, 101b, 101c, and / or 101d as described above) based on the design layout generated by the EDA system 1600. An IC manufacturer (“Fab”) 1620 can be connected to the mask room 1630 and the EDA system 1600 via, for example, the network 1614. The Fab 1620 includes an IC manufacturing tool 1622 for manufacturing an IC wafer (e.g., including the layout of the I / O circuits 101a, 101b, 101c, and / or 101d as described above) using the masks manufactured by the mask room 1630. By way of example and not limitation, the IC manufacturing tool 1622 includes one or more cluster tools for manufacturing the IC wafer. The cluster tool can be a multi-reaction chamber type composite device including a multi-corner transfer chamber having a wafer handling robot inserted at its center, a plurality of processing chambers (e.g., CVD chambers, PVD chambers, etching chambers, annealing chambers, or the like) positioned at each wall of the multi-corner transfer chamber; and load lock chambers mounted at different walls of the transfer chamber.

[0194] Reference Figure 17 。 Figure 17 is a block diagram of an IC manufacturing system and its associated IC manufacturing process according to some embodiments of the present disclosure. In some embodiments, based on one or more design layouts, e.g., including the layout of the I / O circuits 101a, 101b, 101c, and / or 101d as described above, the manufacturing system 1700 is used to manufacture one or more masks and one or more integrated circuits.

[0195] In Figure 17In this case, the IC manufacturing system 1700 includes entities such as a design house 1720, a mask house 1730, and a foundry 1750 that interact with each other in the design, development, and manufacturing cycle, and / or services related to manufacturing the IC 1760. The entities in the IC manufacturing system 1700 are connected via a communication network. In some embodiments, the communication network is a single network. In some embodiments, the communication network is a variety of different networks, such as an Ethernet network and the Internet. The communication network includes wired and / or wireless communication channels. Each entity interacts with one or more of the other entities and provides services to one or more other entities and / or receives services from one or more other entities. In some embodiments, two or more of the design house 1720, the mask house 1730, and the foundry 1750 are owned by a single larger company. In some embodiments, two or more of the design house 1720, the mask house 1730, and the foundry 1750 coexist in a common facility and use common resources.

[0196] The design house (or design team) 1720 generates a design layout 1722 (e.g., including the layout of the I / O circuits 101a, 101b, 101c, and / or 101d as described above). The design layout 1722 includes various geometric patterns designed for the IC 1760 (e.g., the I / O circuits 101a, 101b, 101c, and / or 101d having resistor circuits as described above). The geometric patterns correspond to the patterns of metal, oxide, or semiconductor layers that make up the various components in the IC 1760 to be manufactured. The various layers are combined to form various device features. For example, a portion of the design layout 1722 includes various circuit features such as active regions, passive regions, functional gate structures, resistor structures, gate contacts, resistor contacts, source / drain contacts, and / or metal wiring to be formed in a semiconductor wafer. The design house 1720 implements appropriate design procedures to form the design layout 1722. The design procedures include one or more of logic design, physical design, or placement and routing. The design layout 1722 is presented in one or more data files that have information on the geometric patterns and a netlist of the various networks. For example, the design layout 1722 can be expressed in the GDSII file format or the DFII file format.

[0197] The mask room 1730 includes data preparation 1732 and mask manufacturing 1744. The mask room 1730 uses the design layout 1722 (e.g., a layout including the I / O circuits 101a, 101b, 101c, and / or 101d as described above) to fabricate one or more photomasks 1745, which will be used to fabricate the respective layers in the IC 1760 according to the design layout 1722. The mask room 1730 performs mask data preparation 1732, in which the design layout 1722 is translated into a representative data file ("representative data file, RDF"). The mask data preparation 1732 provides the RDF to the mask manufacturing 1744. The mask manufacturing 1744 includes a mask writer. The mask writer converts the RDF into an image on a substrate, such as a photomask (master mask) 1745. The design layout 1722 is manipulated by the mask data preparation 1732 to conform to the specific characteristics of the mask writer and / or the rules of the fab 1750. In Figure 17 FIG. 1, the mask data preparation 1732 and the mask manufacturing 1744 are illustrated as separate elements. In some embodiments, the mask data preparation 1732 and the mask manufacturing 1744 may be collectively referred to as mask data preparation.

[0198] In some embodiments, the mask data preparation 1732 includes optical proximity correction (OPC), which uses lithography enhancement techniques to compensate for image errors, such as those that may result from diffraction, interference, other process effects, or the like. The OPC adjusts the design layout 1722. In some embodiments, the mask data preparation 1732 includes other resolution enhancement techniques (RET), such as off-axis illumination, sub-resolution assist features, phase-shifting masks, other suitable techniques, the like, or combinations thereof. In some embodiments, inverse lithography technology (ILT) is also used, which treats OPC as an inverse imaging problem.

[0199] In some embodiments, the mask data preparation 1732 includes a mask rule checker (MRC) that examines the design layout 1722, which has undergone a process in the OPC that applies a set of mask generation rules that contain certain geometric and / or connectivity constraints to ensure sufficient margins, account for variability in the semiconductor manufacturing process, and the like. In some embodiments, the MRC modifies the design layout 1722 diagram to compensate for limitations during mask manufacturing 1744, which may undo some of the modifications performed by the OPC in order to satisfy the mask generation rules.

[0200] In some embodiments, mask data preparation 1732 includes lithography process checking (LPC), and the LPC simulation processes that will be implemented by the foundry 1750 to fabricate the IC 1760. The LPC simulates this process based on the design layout 1722 to generate a simulated manufactured integrated circuit, such as the IC 1760. The process parameters in the LPC simulation may include parameters associated with various processes of the IC manufacturing cycle, parameters associated with the tools used to manufacture the IC, and / or other aspects of the manufacturing process. The LPC considers various factors, such as aerial image contrast, depth of focus ("DOF"), mask error enhancement factor ("MEEF"), other suitable factors, the like, or combinations thereof. In some embodiments, after the simulated manufacturing device has been generated by the LPC, if the simulated device is not close enough to meet the design rules, OPC and / or MRC are repeated to further refine the design layout 1722.

[0201] After mask data preparation 1732 and during mask fabrication 1744, a reticle 1745 or a group of reticles 1745 is fabricated based on a design layout 1722. In some embodiments, mask fabrication 1744 includes performing one or more lithography exposures based on design layout 1722. In some embodiments, an electron-beam (e-beam) or mechanisms of multiple electron-beams are used to form a pattern on reticle 1745 based on a modified design layout 1722. The reticle 1745 can be formed using various techniques. In some embodiments, the reticle 1745 is formed using a binary technique. In some embodiments, the mask pattern includes opaque regions and transparent regions. A radiation beam such as an ultraviolet (UV) beam, which is used to expose a radiation-sensitive material layer (e.g., photoresist) coated on a wafer, is blocked by the opaque regions and transmitted through the transparent regions. In one example, the binary mask version of reticle 1745 includes a transparent substrate (e.g., fused silica) of the binary mask and opaque data (e.g., chromium) coated in the opaque regions. In another example, the reticle 1745 is formed using a phase-shift technique. In the phase-shift mask (PSM) version of reticle 1745, various features in the pattern formed on the phase-shift mask are used to have an appropriate phase difference to enhance resolution and imaging quality. In various examples, the phase-shift mask can be an attenuated PSM or an alternating PSM. The reticle(s) produced by mask fabrication 1744 are used in a variety of processes. For example, such reticle(s) are used in an ion implantation process to form various doped regions in a semiconductor wafer 1753, in an etching process to form various etched regions in a semiconductor wafer 1753, and / or in other suitable processes.

[0202] A foundry 1750 can include wafer fabrication 1752. The foundry 1750 is an IC manufacturing operation that includes one or more manufacturing facilities for manufacturing a variety of different IC products. In some embodiments, the foundry 1750 is a semiconductor foundry. For example, there can be a manufacturing facility for front-end-of-line (FEOL) manufacturing of multiple IC products, and a second manufacturing facility can provide back-end-of-line (BEOL) manufacturing for interconnecting and packaging the IC products, and a third manufacturing facility can provide other services for the foundry business.

[0203] Fab 1750 uses the (multiple) photomasks 1745 fabricated through the mask chamber 1730 to fabricate the IC 1760. Thus, Fab 1750 at least indirectly uses the design layout 1722 (e.g., including the layout of the I / O circuits 101a, 101b, 101c, and / or 101d as described above) to fabricate the IC 1760. In some embodiments, the wafer 1753 is processed by Fab 1750 using the (multiple) photomasks 1745 to form the IC 1760. In some embodiments, device fabrication includes at least indirectly performing one or more optical lithography exposures based on the design layout 1722.

[0204] Accordingly, based on the above discussion, it can be seen that the present disclosure provides advantages. However, it should be understood that other embodiments may provide additional advantages, not all advantages need to be disclosed herein, and no specific advantage is required for all embodiments. One advantage is that by sharing common portions with each other, two bits each including an I / O circuit are combined into a multi-bit cell structure, thereby significantly reducing redundant portions and improving wafer utilization. Another advantage is that the cell polysilicon pitch required for the form factor of the multi-bit cell structure is smaller, thus occupying a smaller area than that of a single bit. Still another advantage is that the multi-bit cell can meet the number of fins of the ESC protection circuit according to design rule check (DRC), while reducing the area of the I / O circuit.

[0205] In some embodiments of the present disclosure, an integrated circuit device includes a semiconductor substrate, a plurality of multi-bit cells over the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit cells includes a first bit and a second bit. The first bit includes a first electrostatic discharge (ESD) protection circuit and a first doped region in the semiconductor substrate. The second bit includes a second ESD protection circuit and a second doped region in the semiconductor substrate. In a top view, the first doped region of the first bit is symmetric with respect to the boundary between the first bit and the second bit to the second doped region of the second bit, and the first doped region of the first bit and the second doped region of the second bit have a first conductivity type. The first pad is connected to the first ESD protection circuit. The second pad is connected to the second ESD protection circuit.

[0206] According to some embodiments of the present utility model, an integrated circuit device includes a semiconductor substrate, a plurality of multi-bit units above the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit units includes a first bit and a second bit. The first bit includes a first electrostatic discharge protection circuit and a first doped band region in the semiconductor substrate. The second bit includes a second ESD protection circuit and a second doped band region in the semiconductor substrate. In a top view, the first doped band region of the first bit is symmetric with respect to the boundary between the first bit and the second bit to the second doped band region of the second bit. The first pad is connected to the first ESD protection circuit. The second pad is connected to the second ESD protection circuit.

[0207] In some embodiments, in a top view, an n-type device of the first electrostatic discharge protection circuit of the first bit is symmetric with respect to the boundary between the first bit and the second bit to an n-type device of the second electrostatic discharge protection circuit of the second bit.

[0208] In some embodiments, in a top view, a p-type device of the first electrostatic discharge protection circuit of the first bit is symmetric with respect to the boundary between the first bit and the second bit to a p-type device of the second electrostatic discharge protection circuit of the second bit.

[0209] In some embodiments, the integrated circuit device further includes a power rail connected to the first band region (or the first doped band region) and the second band region (or the second doped band region).

[0210] In some embodiments, the semiconductor substrate has at least one well region having a second conductivity type opposite to the first conductivity type, and the first band region and the second band region are spaced apart from the at least one well region.

[0211] In some embodiments, in a top view, the at least one well region does not extend across the boundary between the first bit and the second bit.

[0212] In some embodiments, the first bit further includes a third band region in a first one of the plurality of well regions, the second bit further includes a fourth band region in a second one of the plurality of well regions spaced apart from the first one of the plurality of well regions, and the third band region and the fourth band region have the second conductivity type.

[0213] In some embodiments, a space between the first band region of the first bit and the second band region of the second bit is less than twice the gate pitch of the first electrostatic discharge protection circuit.

[0214] In some embodiments, the first conductivity type corresponds to a p-type conductivity type.

[0215] In some embodiments of the present disclosure, an integrated circuit device includes a semiconductor substrate, a plurality of multi-bit cells above the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit cells includes a first bit and a second bit. The first bit includes a first ESD protection circuit. The second bit includes a second ESD protection circuit. In a top view, the first ESD protection circuit of the first bit is symmetric with respect to the second ESD protection circuit of the second bit relative to a boundary between the first bit and the second bit. The first pad is connected to the first ESD protection circuit. The second pad is connected to the second ESD protection circuit.

[0216] In some embodiments, in a top view, an n-type device of the first electrostatic discharge protection circuit is adjacent to an n-type device of the second electrostatic discharge protection circuit.

[0217] In some embodiments, a space between an n-type device of the first electrostatic discharge protection circuit and an n-type device of the second electrostatic discharge protection circuit is less than twice a gate pitch of the first electrostatic discharge protection circuit.

[0218] In some embodiments, an n-type device of the first electrostatic discharge protection circuit is spaced apart from an n-type device of the second electrostatic discharge protection circuit by a first space, and a p-type device of the first electrostatic discharge protection circuit is spaced apart from a p-type device of the second electrostatic discharge protection circuit by a second space, and the second space is greater than the first space.

[0219] In some embodiments, an n-type device of the first electrostatic discharge protection circuit is above a first active region of the semiconductor substrate, the first bit further includes an n-type strip region above a second active region of the semiconductor substrate, and the second active region is aligned with the first active region.

[0220] In some embodiments, a length of each of the plurality of multi-bit cells measured in a direction along an extension direction perpendicular to the boundary is greater than a length of each of the plurality of multi-bit cells measured in a direction along the extension direction parallel to the boundary.

[0221] In some embodiments, the first bit further includes a first transfer circuit and a first receiving circuit, the second bit further includes a second transfer circuit and a second receiving circuit, wherein in a top view, the first transfer circuit of the first bit is symmetric with respect to the second transfer circuit of the second bit relative to the boundary between the first bit and the second bit, and in a top view, the first receiving circuit of the first bit is symmetric with respect to the second receiving circuit of the second bit relative to the boundary between the first bit and the second bit.

[0222] In some embodiments of the present disclosure, a method for manufacturing an integrated circuit device is provided. The method includes forming a first n-type device and a first p-type device in a first region of a semiconductor substrate, and forming a second n-type device and a second p-type device in a second region of the semiconductor substrate, wherein in a top view, the first n-type device and the first p-type device are symmetric with respect to the second n-type device and the second p-type device relative to a boundary between the first region and the second region; forming an interconnect structure over the first n-type device, the first p-type device, the second n-type device, and the second p-type device such that the first n-type device and the first p-type device form a first ESD protection circuit and the second n-type device and the second p-type device form a second ESD protection circuit; forming a first pad over the interconnect structure, the first pad being electrically connected to the first n-type device and the first p-type device of the first ESD protection circuit; and forming a second pad over the interconnect structure, the second pad being electrically connected to the second n-type device and the second p-type device of the second ESD protection circuit.

[0223] In some embodiments, the method further includes forming a first p-type strip region in the first region of the semiconductor substrate; and forming a second p-type strip region in the second region of the semiconductor substrate, wherein in a top view, the first p-type strip region is symmetric with respect to the second p-type strip region relative to the boundary between the first region and the second region.

[0224] In some embodiments, the first p-type strip region is adjacent to the second p-type strip region.

[0225] In some embodiments, the method further includes forming a first n-type strip region in the first region of the semiconductor substrate; and forming a second n-type strip region in the second region of the semiconductor substrate, wherein in a top view, the first n-type strip region is symmetric with respect to the second n-type strip region relative to the boundary between the first region and the second region.

[0226] According to some embodiments of the present invention, an integrated circuit device includes a semiconductor substrate, a plurality of multi-bit cells over the semiconductor substrate, a first pad, and a second pad. Each of the multi-bit cells includes a first bit and a second bit. The first bit includes a first electrostatic discharge (ESD) protection circuit and a first strip region in the semiconductor substrate. The second bit includes a second ESD protection circuit and a second strip region in the semiconductor substrate. In a top view, the first strip region of the first bit is symmetric with respect to the second strip region of the second bit relative to a boundary between the first bit and the second bit. The first pad is connected to the first ESD protection circuit. The second pad is connected to the second ESD protection circuit.

[0227] In some embodiments, the integrated circuit device further includes a power rail connected to the first doped strip region and the second doped strip region.

[0228] According to some embodiments of the present invention, an integrated circuit device includes a first bit, a second bit, a first pad, and a second pad. The first bit includes a first electrostatic discharge protection circuit, wherein the first electrostatic discharge protection circuit includes a first n-type device and a first p-type device in a first region of a semiconductor substrate. The second bit includes a second electrostatic discharge protection circuit, wherein the second electrostatic discharge protection circuit includes a second n-type device and a second p-type device in a second region of the semiconductor substrate. The first n-type device and the first p-type device are symmetric with respect to the second n-type device and the second p-type device about a boundary between the first region and the second region. The first pad is located above the interconnect structure and electrically connected to the first n-type device and the first p-type device of the first electrostatic discharge protection circuit. The second pad is located above the interconnect structure and electrically connected to the second n-type device and the second p-type device of the second electrostatic discharge protection circuit.

[0229] In some embodiments, the integrated circuit device further includes a first p-type strip region and a second p-type strip region, the first p-type strip region is in the first region of the semiconductor substrate, and the second p-type strip region is in the second region of the semiconductor substrate, wherein in a top view, the first p-type strip region and the second p-type strip region are symmetric with respect to the boundary between the first region and the second region.

[0230] The foregoing outlines features of several embodiments so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for the same purposes and / or achieving the same advantages as those introduced herein. Those skilled in the art should also recognize that such equivalent constructs do not depart from the spirit and scope of the present disclosure, and that such equivalent constructs may be made herein in various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

Claims

1. An integrated circuit device, characterized in that, Comprising: A semiconductor substrate; A plurality of multi-bit cells, above the semiconductor substrate, each of the plurality of multi-bit cells comprising: A first bit, comprising a first electrostatic discharge protection circuit and a first doped band region in the semiconductor substrate; and A second bit, comprising a second electrostatic discharge protection circuit and a second doped band region in the semiconductor substrate, wherein in a top view, the first doped band region of the first bit is symmetric with respect to a boundary between the first bit and the second bit to the second doped band region of the second bit; a first pad, connected to the first electrostatic discharge protection circuit; And A second pad, connected to the second electrostatic discharge protection circuit.

2. The integrated circuit device according to claim 1, wherein Wherein in a top view, an n-type device of the first electrostatic discharge protection circuit of the first bit is symmetric with respect to the boundary between the first bit and the second bit to an n-type device of the second electrostatic discharge protection circuit of the second bit.

3. The integrated circuit device according to claim 1, wherein Wherein in a top view, a p-type device of the first electrostatic discharge protection circuit of the first bit is symmetric with respect to the boundary between the first bit and the second bit to a p-type device of the second electrostatic discharge protection circuit of the second bit.

4. The integrated circuit device according to any one of claims 1 to 3, characterized in that, Further comprising: A power rail, connected to the first doped band region and the second doped band region.

5. An integrated circuit device, characterized in that, Comprising: A semiconductor substrate; A plurality of multi-bit cells, above the semiconductor substrate, each of the plurality of multi-bit cells comprising: A first bit, comprising a first electrostatic discharge protection circuit; and A second bit, comprising a second electrostatic discharge protection circuit, wherein in a top view, the first electrostatic discharge protection circuit of the first bit is symmetric with respect to a boundary between the first bit and the second bit to the second electrostatic discharge protection circuit of the second bit; A first pad, connected to the first electrostatic discharge protection circuit; And A second pad, connected to the second electrostatic discharge protection circuit.

6. The integrated circuit device according to claim 5, wherein, Wherein in a top view, an n-type device of the first electrostatic discharge protection circuit is adjacent to an n-type device of the second electrostatic discharge protection circuit.

7. The integrated circuit device according to claim 5, characterized in that, Wherein a space between an n-type device of the first electrostatic discharge protection circuit and an n-type device of the second electrostatic discharge protection circuit is less than twice a gate pitch of the first electrostatic discharge protection circuit.

8. The integrated circuit device according to claim 5, wherein Wherein an n-type device of the first electrostatic discharge protection circuit and an n-type device of the second electrostatic discharge protection circuit are spaced apart by a first space from each other, and a p-type device of the first electrostatic discharge protection circuit and a p-type device of the second electrostatic discharge protection circuit are spaced apart by a second space from each other, and the second space is greater than the first space.

9. An integrated circuit device, characterized in that, Comprising: A first bit, comprising a first electrostatic discharge protection circuit, wherein the first electrostatic discharge protection circuit comprises a first n-type device and a first p-type device in a first region of a semiconductor substrate; A second bit element includes a second electrostatic discharge protection circuit, where the second electrostatic discharge protection circuit includes a second n-type device and a second p-type device in a second region of the semiconductor substrate, and the first n-type device and the first p-type device of the first electrostatic discharge protection circuit are symmetric to the second n-type device and the second p-type device of the second electrostatic discharge protection circuit with respect to a boundary between the first region and the second region; A first pad is electrically connected to the first n-type device and the first p-type device of the first electrostatic discharge protection circuit; and A second pad is electrically connected to the second n-type device and the second p-type device of the second electrostatic discharge protection circuit.

10. The integrated circuit device according to claim 9, wherein, Further included are: A first p-type strip region in the first region of the semiconductor substrate; and A second p-type strip region in the second region of the semiconductor substrate, where in a top view, the first p-type strip region and the second p-type strip region are symmetric with respect to the boundary between the first region and the second region.

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