Display panel and electronic device

Abstract

The utility model relates to a display panel and an electronic device. The display panel includes an element layer. The element layer includes: a plurality of light emitting elements connected to the pixel circuit; a pixel defining layer having a plurality of openings respectively overlapping the plurality of light emitting elements; and a spacer disposed on the pixel defining layer. The plurality of openings includes a first opening, a second opening, and a third opening adjacent to the spacer. The spacer includes: a central portion disposed between the first opening, the second opening, and the third opening; and a first extension portion, a second extension portion, and a third extension portion protruding from the central portion in three directions, respectively. An end portion of the first extension portion, an end portion of the second extension portion, and an end portion of the third extension portion are disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0117444, filed on September 5, 2023, with the Korean Intellectual Property Office, the entire content of which is incorporated herein by reference. Technical Field

[0003] The embodiments described herein relate to a display panel having improved manufacturing yield and reliability, and an electronic device including the display panel. Background Art

[0004] A display panel may include pixels. Each of the pixels may include an emission layer disposed between electrodes facing each other. The emission layer may be formed by various methods, and one of the methods may be a deposition method using a mask. The display panel may include spacers for supporting the mask. Summary of the Invention

[0005] Embodiments provide a display panel capable of improving manufacturing yield and reliability, and an electronic device including the display panel.

[0006] However, the embodiments are not limited to the embodiments set forth herein. The above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the following detailed description of the present disclosure.

[0007] According to an embodiment, a display panel may include an element layer. The element layer includes: a plurality of light-emitting elements connected to a pixel circuit; a pixel defining layer having a plurality of openings respectively overlapping the plurality of light-emitting elements; and spacers disposed on the pixel defining layer. The plurality of openings may include a first opening, a second opening, and a third opening, and each of the first opening, the second opening, and the third opening may be adjacent to a spacer. The spacer may include: a central portion disposed between the first opening, the second opening, and the third opening; a first extension portion extending from the central portion to be disposed between the first opening and the second opening; a second extension portion extending from the central portion to be disposed between the second opening and the third opening; and a third extension portion extending from the central portion to be disposed between the third opening and the first opening. Ends of the first extension portion, ends of the second extension portion, and ends of the third extension portion may be disposed within a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

[0008] The spacer may include a plurality of layers, and at least one of the plurality of layers may be a conductive material layer.

[0009] The spacer may include: a first layer having a first width; and a second layer disposed on the first layer and having a second width smaller than the first width.

[0010] The spacer may include a plurality of spacers, and the plurality of spacers may include a first spacer and a second spacer closest to the first spacer. At least two of the plurality of light-emitting elements may be disposed between the first spacer and the second spacer.

[0011] Each of the first opening, the second opening, and the third opening may have a polygonal shape.

[0012] The first opening may include a first side facing the first extension, the second opening may include a second side facing the first extension, and an end of the first extension may be aligned with or spaced apart from a virtual line connecting the center of the first side and the center of the second side.

[0013] The ends of the first extension, the second extension, and the third extension may have a circular shape, an angular shape, or a pointed shape.

[0014] A first angle of a side surface of the pixel defining layer that defines the first opening with respect to a bottom surface of the pixel defining layer may be about 40 degrees or less.

[0015] A second angle of a side surface of the spacer with respect to a bottom surface of the spacer may be greater than or equal to the first angle.

[0016] The spacer may be thicker than the pixel defining layer.

[0017] A plurality of valleys recessed from an upper surface of the pixel defining layer may be defined in the pixel defining layer, and the plurality of valleys may respectively surround at least a part of the first opening, the second opening, and the third opening.

[0018] The spacer may be disposed between the plurality of valleys.

[0019] The display panel may further include a plurality of protruding patterns disposed on the pixel defining layer and respectively surrounding at least a part of the first opening, the second opening, and the third opening.

[0020] The spacer may have a thickness greater than a thickness of the plurality of protruding patterns.

[0021] According to an embodiment, a display panel may include an element layer. The element layer includes: a light-emitting element including a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a part of the first electrode; and a spacer disposed on the pixel defining layer. The spacer may include a central portion and a first extension portion, a second extension portion, and a third extension portion respectively protruding from the central portion in three directions.

[0022] A first angle of a side surface of the pixel defining layer that defines the opening with respect to a bottom surface of the pixel defining layer may be less than or equal to a second angle of a side surface of the spacer with respect to a bottom surface of the spacer.

[0023] The first angle of the side surface of the pixel defining layer that defines the opening with respect to the bottom surface of the pixel defining layer may be about 40 degrees or less.

[0024] The spacer may be thicker than the pixel defining layer.

[0025] The spacer may include a plurality of layers, and at least one of the plurality of layers may be a conductive material layer.

[0026] The spacer may include: a first layer having a first width; and a second layer disposed on the first layer and having a second width smaller than the first width.

[0027] The opening may have a polygonal shape and may include a first side facing the first extension portion, and an end portion of the first extension portion may be aligned with or spaced apart from a normal line extending from the center of the first side.

[0028] The spacer may include a plurality of spacers, and the plurality of spacers may include a first spacer and a second spacer closest to the first spacer. The light-emitting element may include a plurality of light-emitting elements. At least two of the plurality of light-emitting elements may be disposed between the first spacer and the second spacer.

[0029] According to an embodiment, a display panel may include an element layer. The element layer includes: a light-emitting element connected to a pixel circuit and including a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a part of the first electrode; and a spacer disposed on the pixel defining layer. The spacer may include a central portion and a first extension portion, a second extension portion, and a third extension portion respectively protruding from the central portion in three directions. The first angle of the side surface of the pixel defining layer that defines the opening with respect to the bottom surface of the pixel defining layer is about 40 degrees or less.

[0030] The second angle of the side surface of the spacer relative to the bottom surface of the spacer may be greater than or equal to the first angle.

[0031] The spacer may include a plurality of layers, and at least one of the plurality of layers may be a conductive material layer.

[0032] The spacer may include a first layer having a first width and a second layer disposed on the first layer and having a second width smaller than the first width.

[0033] According to an embodiment, an electronic device may include: a display panel that displays an image; and a housing that houses the display panel. The display panel may include an element layer. The element layer includes: a plurality of light-emitting elements connected to a pixel circuit; a pixel defining layer having a plurality of openings respectively overlapping the plurality of light-emitting elements; and a spacer disposed on the pixel defining layer. The plurality of openings may include a first opening, a second opening, and a third opening, and each of the first opening, the second opening, and the third opening is adjacent to the spacer. The spacer may include: a central portion disposed between the first opening, the second opening, and the third opening; a first extension extending from the central portion to be disposed between the first opening and the second opening; a second extension extending from the central portion to be disposed between the second opening and the third opening; and a third extension extending from the central portion to be disposed between the third opening and the first opening. Ends of the first extension, ends of the second extension, and ends of the third extension may be disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects and features of the present disclosure will become apparent and understood by describing its embodiments in detail with reference to the accompanying drawings.

[0035] Figure 1 is a schematic perspective view of an electronic device according to an embodiment.

[0036] Figure 2 is a schematic diagram showing the use of an electronic device according to an embodiment.

[0037] Figure 3 is an exploded schematic perspective view showing a part of an electronic device according to an embodiment.

[0038] Figure 4It is an enlarged schematic plan view showing a partial area of a display panel according to an embodiment.

[0039] Figure 5A It is a schematic cross-sectional view of a display panel according to an embodiment.

[0040] Figure 5B It is a schematic cross-sectional view of a display panel according to an embodiment.

[0041] Figure 5C It is a schematic cross-sectional view of a display panel according to an embodiment.

[0042] Figure 6A It is a schematic cross-sectional view of a display panel according to an embodiment.

[0043] Figure 6B It is a schematic cross-sectional view of a display panel according to an embodiment.

[0044] Figure 7A It is an enlarged schematic plan view showing a partial area of a display panel according to an embodiment.

[0045] Figure 7B It is an enlarged schematic plan view showing a partial area of a display panel according to an embodiment.

[0046] Figure 7C It is an enlarged schematic plan view showing a partial area of a display panel according to an embodiment.

[0047] Figure 8A It is a schematic cross-sectional view of a partial area of a display panel according to an embodiment.

[0048] Figure 8B It is a schematic cross-sectional view of a partial area of a display panel according to an embodiment.

[0049] Figure 8C It is a schematic cross-sectional view of a partial area of a display panel according to an embodiment.

[0050] Figure 8D It is a schematic cross-sectional view of a partial area of a display panel according to an embodiment.

[0051] Figure 8E It is a schematic cross-sectional view of a partial area of a display panel according to an embodiment.

[0052] Figure 9 It is a schematic cross-sectional view of a partial area of a display panel according to an embodiment. Detailed implementation manners

[0053] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present utility model. As used herein, "embodiment" and "implementation" are interchangeable terms, which are non-limiting examples of the devices or methods disclosed herein. However, it will be understood that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. In this document, the various embodiments need not be exclusive and need not limit the disclosure. For example, the specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

[0054] Unless otherwise specified, the embodiments shown are to be understood as providing the features of the present utility model. Thus, unless otherwise specified, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually or collectively referred to as "elements") of each embodiment may be otherwise combined, separated, interchanged, and / or rearranged without departing from the scope of the present utility model.

[0055] The use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material properties, dimensions, ratios, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. In addition, in the drawings, for clarity and / or descriptive purposes, the dimensions and relative dimensions of the elements may be enlarged. When the embodiments may be implemented differently, a particular processing sequence may be performed in a different order than described. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to that described. In addition, like reference numerals denote like elements.

[0056] When an element or layer is referred to as being “on,” “connected to,” or “coupled to” another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or intervening elements or layers may be present. However, when an element or layer is referred to as being “directly on,” “directly connected to,” or “directly coupled to” another element or layer, no intervening elements or layers are present. For this reason, the term “connected” can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements. In addition, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a rectangular coordinate system such as the X, Y, and Z axes, and can be interpreted in a broader sense. For example, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of A and B” can be understood to mean only A, only B, or any combination of A and B. In addition, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0057] Although the terms “first,” “second,” etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of this disclosure.

[0058] Spatial relative terms such as “beneath,” “below,” “under,” “lower,” “above,” “upper,” “on,” “more elevated,” and “side” (e.g., as in “sidewall”) may be used herein for descriptive purposes and, thereby, to describe the relationship of one element to another element shown in the figures. In addition to the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture. For example, if the device in the figures is turned over, an element described as “beneath” or “below” other elements or features would then be oriented “above” or “on” the other elements or features. Thus, the term “beneath” can encompass both an orientation of “above” and “beneath.” In addition, the device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative descriptors used herein should be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments and is not intended to be limiting. As used herein, unless the context clearly dictates otherwise, the singular forms "a", "an" and "the" are also intended to include the plural forms. Further, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the stated feature, integer, step, operation, element, component and / or group thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and thus are used to interpret the inherent deviations of measured, calculated and / or provided values that would be recognized by a person of ordinary skill in the art.

[0060] Various embodiments have been described herein with reference to sectional and / or exploded illustrations, which are schematic illustrations of the embodiments and / or intermediate structures. Accordingly, variations in the shape of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein should not be construed as being limited to the particular shapes of the regions shown, but include shape deviations resulting from, for example, manufacturing. In this manner, the regions shown in the figures may be schematic in nature and the shapes of these regions may not reflect the actual shape of the regions of the device, and thus are not necessarily intended to be limiting.

[0061] As is customary in the art, in the accompanying drawings, some embodiments are described and illustrated in terms of functional blocks, units, and / or modules. Those of ordinary skill in the art will understand that these blocks, units, and / or modules are physically implemented by electronic (or optical) circuits formed by, for example, logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, which can use semiconductor-based manufacturing technologies or other manufacturing technologies. In cases where the blocks, units, and / or modules are implemented by a microprocessor or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein and can optionally be driven by firmware and / or software. It is also contemplated that each block, unit, and / or module can be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) for performing other functions. Moreover, without departing from the scope of the present utility model, each block, unit, and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units, and / or modules. In addition, without departing from the scope of the present utility model, the blocks, units, and / or modules of some embodiments can be physically combined into more complex blocks, units, and / or modules.

[0062] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0063] Figure 1 is a perspective schematic view of an electronic device HMD according to an embodiment. Figure 2 is a schematic view showing the use of an electronic device HMD according to an embodiment. Figure 3 is an exploded perspective schematic view showing a part of an electronic device HMD according to an embodiment.

[0064] Referring to Figure 1 、 Figure 2 and Figure 3 , the electronic device HMD can be a device activated according to an electrical signal. For example, the electronic device HMD can be a mobile phone, a foldable mobile phone, a notebook computer, a television, a tablet computer, an automotive navigation unit, a game console, or a wearable device, but the embodiments are not limited thereto. The wearable device worn on a part of the user's body can include a head-mounted display (HMD) device that implements extended reality (XR). Although Figure 1 shows an example in which the electronic device HMD is a head-mounted display device, the embodiments are not limited thereto.

[0065] The electronic device HMD can be a display device worn on the head of the user US. The electronic device HMD can provide an image and can block the user US's actual peripheral vision. The user US wearing the electronic device HMD can more easily immerse in virtual reality.

[0066] The electronic device HMD may include a body HS, a strap STR, a cushion PP, and a display panel DP. For example, the electronic device HMD may include various types of sensors, cameras, etc.

[0067] The body HS can be worn on the head of the user US. The display panel DP for displaying images and the acceleration sensor can be accommodated inside the body HS. The acceleration sensor can sense the movement of the user US and can transmit certain signals to the display panel DP. Accordingly, the display panel DP can provide images corresponding to changes in the gaze of the user US. Thus, the user US can experience virtual reality similar to actual reality.

[0068] In addition to the above components, components with various functions can also be accommodated inside the body HS. The body HS can be referred to as a housing or a case. For example, an operation unit for adjusting the volume, screen brightness, etc. can be additionally provided on the outside of the body HS. The operation unit can be provided as a physical button or can be in the form of a touch sensor. In addition, a proximity sensor for determining whether the user US has turned on the electronic device HMD can be accommodated inside the body HS. For example, an external display panel can be additionally provided on the body HS.

[0069] The body HS can be divided into a body part HS-1 and a cover part HS-2. Although Figure 3 an example in which the body part HS-1 and the cover part HS-2 are separated from each other is shown, the embodiments are not limited thereto. For example, the body part HS-1 and the cover part HS-2 can be integrated with each other and can not be separated from each other.

[0070] The display panel DP can be provided between the body part HS-1 and the cover part HS-2. The display panel DP can provide images through a display area DA, respectively. Although Figure 3 an example in which a left-eye image and a right-eye image are provided by a separately provided display panel DP is shown, the embodiments are not limited thereto. For example, the left-eye image and the right-eye image can be displayed through a single display panel. The display panel DP can be driven by a separate driver. However, the display panel DP is not limited thereto and can be driven by a single driver.

[0071] The display panel DP can generate images corresponding to input image data. The display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro light-emitting diode (LED) display panel, a nano LED display panel, or a liquid crystal display panel. In the present embodiment, the display panel DP being an organic light-emitting display panel will be described. However, the embodiments are not limited thereto.

[0072] The strap STR can be coupled with the body HS so that the body HS can be easily worn on the head of the user US. The strap STR can include a main strap STR1 and an upper strap STR2.

[0073] The main strap STR1 can be worn along the circumference of the head of the user US. The main strap STR1 can fix the body HS to the head of the user US so that the body HS is in close contact with the head of the user US. The upper strap STR2 can connect the body HS and the main strap STR1 along the upper part of the head of the user US. The upper strap STR2 can prevent the body HS from slipping. For example, the upper strap STR2 can disperse the load of the body HS to further improve the wearing comfort of the user US.

[0074] Although Figure 1 an example is shown in which the main strap STR1 and the upper strap STR2 are length adjustable, the embodiments are not limited thereto. For example, in another example, the main strap STR1 and the upper strap STR2 can be elastic, and the length adjustable part can be omitted.

[0075] As long as the strap STR can fix the body HS to the head of the user US, the strap STR can be modified into various forms other than Figure 1 and Figure 2 the forms shown. For example, in another example, the upper strap STR2 can be omitted. In addition, in the embodiments, the strap STR can be modified into various forms (such as a helmet coupled with the body HS or temple arms coupled with the body HS).

[0076] The cushion PP can be provided between the body HS and the head of the user US. The cushion PP can be formed of a material whose shape can be freely deformed. For example, the cushion PP can be formed of a polymer resin (such as polyurethane, polycarbonate, polypropylene, or polyethylene), or can be formed as a sponge made by foaming a liquid rubber, a urethane-based material, or an acrylic-based material. However, the embodiments are not limited thereto.

[0077] The cushion PP can make the body HS in close contact with the head of the user US to improve the wearing comfort of the user US. The cushion PP can be detached from the body HS. In another example, the cushion PP can be omitted.

[0078] The optical system OL can be disposed inside the body part HS-1 of the body HS. The optical system OL can magnify an image provided by the display panel DP. Each of the display panels DP can display an image in the third direction DR3 through the display area DA, and the display area DA is parallel to the first direction DR1 and the second direction DR2 intersecting the first direction DR1. The optical system OL can be spaced apart from the display panel DP in the third direction DR3. The optical system OL can be disposed between the display panel DP and the eyes of the user US. The optical system OL can include a right-eye optical system OL_R and a left-eye optical system OL_L. The left-eye optical system OL_L can magnify the image and provide the image to the left pupil of the user US, and the right-eye optical system OL_R can

[0079] magnify the image and provide the image to the right pupil of the user US.

[0080] The left-eye optical system OL_L and the right-eye optical system OL_R can be spaced apart from each other in the first direction DR1. The distance between the right-eye optical system OL_R and the left-eye optical system OL_L can be adjusted to correspond to the distance between the two eyes of the user US. For example, the distance between the optical system OL and the display panel DP can be adjusted according to the vision (or eyesight) of the user US.

[0081] The optical system OL can be a convex aspherical lens. For example, the optical system OL can be a pancake lens, but the embodiments are not limited thereto. In the embodiments, it has been described that each of the left-eye optical system OL_L and the right-eye optical system OL_R is implemented by a single lens. However, the embodiments are not limited thereto. For example, each of the left-eye optical system OL_L and the right-eye optical system OL_R can include a plurality of lenses.

[0082] In Figures 1 to 3 it has been described that the display panel DP is applied to an electronic device HMD such as a head-mounted display device. However, the embodiments are not limited thereto. For example, the display panel DP can also be applied to a bar-shaped electronic device, a foldable electronic device, a rollable electronic device, or a slidable electronic device.

[0083] Figure 4 is an enlarged schematic plan view showing a partial area DA-p of the display panel DP (refer to Figure 3 ) according to an embodiment.

[0084] Figure 4 The partial area DA-p (hereinafter referred to as the partial area) shown in Figure 3A part of it. The emission regions PXA-R, PXA-G, and PXA-B and the spacers SPC included in the partial region DA-p can be repeatedly arranged in the first direction DR1 and the second direction DR2.

[0085] The display region DA of the display panel DP can include emission regions PXA-R, PXA-G, and PXA-B and a non-emission region NPXA surrounding the emission regions PXA-R, PXA-G, and PXA-B. The emission regions PXA-R, PXA-G, and PXA-B can be regions separated from each other by a pixel defining layer PDL (reference Figure 5A ). The non-emission region NPXA can be the region between adjacent emission regions PXA-R, PXA-G, and PXA-B and can be a region corresponding to the pixel defining layer PDL. The emission regions PXA-R, PXA-G, and PXA-B can be separated from each other to correspond to the openings OP defined in the pixel defining layer PDL.

[0086] The emission regions PXA-R, PXA-G, and PXA-B can respectively correspond to light-emitting elements. For example, an emission region (e.g., a single emission region) PXA (reference Figure 5A ) can be defined in a light-emitting element (e.g., a single light-emitting element) 100ED (reference Figure 5A ).

[0087] The emission regions PXA-R, PXA-G, and PXA-B can include a first emission region PXA-R, a second emission region PXA-G, and a third emission region PXA-B. In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B can display lights having different wavelengths. The first emission region PXA-R can display a first light as a light having a red wavelength, the second emission region PXA-G can display a second light as a light having a green wavelength, and the third emission region PXA-B can display a third light as a light having a blue wavelength.

[0088] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B can include an emission layer that outputs the same source light. For example, the source light can be white light or blue light. The source light can be converted into lights having different colors by a wavelength conversion layer or a color filter layer included in the display panel DP. Therefore, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B can display lights having different wavelengths.

[0089] The first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may form a pixel (e.g., a single pixel). For example, a pixel may include sub-pixels, and the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may correspond to the sub-pixels in a one-to-one manner.

[0090] According to an embodiment, the display panel DP may be applied to an electronic device for implementing extended reality. For example, the display panel DP may be applied to an electronic device for implementing (or realizing) augmented reality or virtual reality. For example, in order to improve the display quality, it may be required that the display panel DP have a high resolution. For example, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may form a pixel (e.g., a single pixel), and the pixel density of the display panel DP may be 3000 pixels per inch (PPI) or greater.

[0091] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have substantially the same area. However, the embodiment is not limited thereto. For example, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have different areas according to the wavelength of the emitted light.

[0092] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a polygonal shape (e.g., in a plan view). For example, each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a hexagonal shape, but the embodiment is not limited thereto.

[0093] In an embodiment, a control pattern LLP surrounding the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B and overlapping with the non-emission region NPXA may be defined or provided in the display panel DP. The control pattern LLP may at least partially surround the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, respectively. For example, a control pattern (e.g., a single control pattern) LLP may surround an emission region (e.g., a single emission region) (e.g., PXA-R). Although Figure 4 an example where the control pattern LLP completely surrounds the emission region PXA-R is shown, the embodiment is not limited thereto. For example, the control pattern LLP may only surround a part of the emission region PXA-R.

[0094] The control pattern LLP can prevent the generation of lateral leakage current between adjacent emission regions PXA-R, PXA-G, and PXA-B. In this specification, "lateral leakage current" refers to the current flowing in a direction intersecting with a third direction DR3, rather than the current flowing in the third direction DR3 (e.g., in the direction of displaying an image). The third direction DR3 is the stacking direction of the light-emitting elements. The lateral leakage current can refer to the current flowing in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2 in the plane.

[0095] According to an embodiment, the spacer SPC can be disposed between the emission regions PXA-R, PXA-G, and PXA-B. The spacer SPC can include a first spacer SPC1 and a second spacer SPC2 closest to the first spacer SPC1. Among the emission regions PXA-R, PXA-G, and PXA-B, two or more emission regions can be disposed between the first spacer SPC1 and the second spacer SPC2. In addition, since the emission regions are defined to correspond to the light-emitting elements respectively, two or more light-emitting elements can be disposed between the first spacer SPC1 and the second spacer SPC2.

[0096] Different from the embodiment, in the case where the spacers SPC are disposed in respective regions adjacent to the three emission regions PXA-R, PXA-G, and PXA-B, the number of the spacers SPC may increase corresponding to an increase in the resolution of the display panel DP. For example, the amount of the organic material accumulated on the upper surface of the spacer SPC may increase, and the organic material may be transferred to the mask. In the process of aligning the mask and the display panel DP being processed, the foreign matter transferred to the mask may form a scratch on the emission region, which results in a dark spot defect.

[0097] According to an embodiment, the spacer SPC can be disposed only in some regions adjacent to the three emission regions PXA-R, PXA-G, and PXA-B. When compared with the above comparative example, since the number of the spacers SPC is reduced, the amount of the organic material accumulated on the upper surface of the spacer SPC can also be reduced. Therefore, the possibility of the dark spot defect can also be reduced. Although Figure 4 An example is shown in which 48 emission regions PXA-R, PXA-G, and PXA-B and two spacers SPC are disposed in a partial region (or a single partial region) DA-p, but the embodiment is not limited thereto.

[0098] According to an embodiment, 48 emission regions PXA-R, PXA-G, and PXA-B having the same layout relationship as that of the partial region DA-p shown in Figure 4 and two spacers SPC can be alternately and repeatedly disposed along the first direction DR1 and the second direction DR2.

[0099] In an embodiment, the arrangement density of the spacers SPC may be lower than the pixel density. For example, Figure 4 the three emission regions PXA-R, PXA-G, and PXA-B in Figure 4 may form a pixel (e.g., a single pixel). For example, it can be understood that 16 pixels are shown in

[0100] In an embodiment, Figure 4 the partial region DA-p shown in Figure 4 may have a width of about 28.8 μm in the first direction DR1 and a width of about 28.8 μm in the second direction DR2. The emission regions PXA-R, PXA-G, and PXA-B and the spacers SPC included in the partial region DA-p may be repeatedly arranged in the first direction DR1 and the second direction DR2. Accordingly, the distance between the spacers SPC closest to each other in the first direction DR1 may be about 28.8 μm or less, and the distance between the spacers SPC closest to each other in the second direction DR2 may be about 28.8 μm or less.

[0101] Figure 5A is a schematic cross-sectional view of a display panel DP according to an embodiment. Figure 5A is a schematic cross-sectional view of the display panel DP taken along line I-I’ of Figure 4

[0102] Referring to Figure 4 and Figure 5A the display panel DP may include a circuit board 100, an element layer 200, a packaging layer 300, and an optical layer 400.

[0103] The circuit board 100 may include a substrate base 110 and a pixel circuit 100PC on the substrate base 110. The substrate base 110 may be a silicon substrate, a germanium substrate, or a silicon-on-insulator (SOI) substrate. For example, the substrate base 110 may be a single-crystalline silicon substrate, but the embodiment is not limited thereto.

[0104] ​The pixel circuit 100PC may include transistors. The transistors may be metal-oxide-semiconductor field-effect transistors (MOSFETs). The pixel circuit 100PC may include a gate electrode E1 above the substrate base 110, a gate dielectric pattern GI between the gate electrode E1 and the substrate base 110, and source / drain regions E2 and E3 on opposite sides of the gate electrode E1. The source / drain regions E2 and E3 may be impurity implantation regions formed in the substrate base 110 on opposite sides of the gate electrode E1.

[0105] The gate electrode E1 may include at least one of a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride or tantalum nitride, etc.), and a metal (e.g., aluminum or tungsten, etc.). The gate dielectric pattern GI may include silicon oxide. The source / drain regions E2 and E3 may have a different conductivity type from the substrate base 110. The source / drain regions E2 and E3 may include an N-type impurity (e.g., phosphorus (P) or arsenic (As)) or a P-type impurity (e.g., boron (B)).

[0106] The circuit board 100 may further include an interlayer insulating layer 120. The interlayer insulating layer 120 may be formed on the substrate base 110 and may cover the pixel circuit 100PC. The interlayer insulating layer 120 may include an oxide layer, a nitride layer, or an oxynitride layer. Lower conductive contacts 130 may be formed in the interlayer insulating layer 120 and may be respectively connected to the source / drain regions E2 and E3. The lower conductive contacts 130 may include a conductive material.

[0107] The circuit board 100 may further include a wiring pattern layer 140. The wiring pattern layer 140 may be formed on the interlayer insulating layer 120. Each of the lower conductive contacts 130 may be connected to a corresponding one in the wiring pattern layer 140. The wiring pattern layer 140 may include, for example, metal. For example, an additional wiring pattern layer may be formed between the interlayer insulating layer 120 and the wiring pattern layer 140. For example, each of the lower conductive contacts 130 may be electrically connected to the corresponding wiring pattern layer 140 through a corresponding one in the additional wiring pattern layer. The additional wiring pattern layer may include, for example, metal.

[0108] The circuit board 100 may further include an upper interlayer insulating layer 150. The upper interlayer insulating layer 150 may be formed on the interlayer insulating layer 120 and may cover the wiring pattern layer 140. The upper interlayer insulating layer 150 may include an oxide layer, a nitride layer, or an oxynitride layer.

[0109] The component layer 200 may be disposed on the circuit board 100. The component layer 200 may include a light-emitting element 100ED. In Figure 5AAmong them, the light-emitting element 100ED is representatively shown. The emission region PXA may be defined to correspond to the light-emitting element 100ED. The emission region PXA may be defined by an opening OP defined in the pixel defining layer PDL. For example, the pixel circuit 100PC and the light-emitting element 100ED may be connected to each other (e.g., electrically connected) and may form a pixel PX.

[0110] The light-emitting element 100ED may include a first electrode AE, an intermediate layer CEL, and a second electrode CE. The first electrode AE may be referred to as a pixel electrode or an anode, and the second electrode CE may be referred to as a common electrode or a cathode. The intermediate layer CEL may include a functional layer commonly provided in the emission regions PXA-R, PXA-G, and PXA-B and an emission layer that is patterned to correspond to each of the emission regions PXA-R, PXA-G, and PXA-B.

[0111] The first electrode AE may be disposed on the circuit board 100. The first electrode AE may be connected to a corresponding one in the wiring pattern layer 140 through an upper conductive contact 160 that penetrates the upper interlayer insulating layer 150. The first electrode AE may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In an embodiment, the first electrode AE may include a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, titanium, titanium nitride, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, and aluminum-doped zinc oxide. For example, the first electrode AE may include a multilayer structure in which indium tin oxide, silver, and indium tin oxide are sequentially stacked on top of one another.

[0112] The pixel defining layer PDL may be disposed on the circuit board 100. An opening OP for exposing a part of the first electrode AE may be defined in the pixel defining layer PDL. For example, the pixel defining layer PDL may cover the periphery of the first electrode AE. The emission region PXA may be defined by the pixel defining layer PDL. The pixel defining layer PDL may have a single-layer structure or a multilayer structure. The pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0113] In an embodiment, a control pattern LLP overlapping with a non-emitting region NPXA may be defined in a pixel definition layer PDL. The control pattern LLP may have a shape recessed from an upper surface of the pixel definition layer PDL in a third direction DR3 that is a thickness direction. Accordingly, the control pattern LLP may be referred to as a valley, valley pattern, groove, or groove pattern. A depth of the control pattern LLP may be less than a thickness of the pixel definition layer PDL. Accordingly, side surfaces and a bottom surface of the control pattern LLP may be defined by the pixel definition layer PDL.

[0114] An intermediate layer CEL may be disposed on the first electrode AE and the pixel definition layer PDL. A second electrode CE may be disposed on the intermediate layer CEL. In an embodiment, a thickness of the intermediate layer CEL may be reduced by the control pattern LLP. For example, some layers included in the intermediate layer CEL may be interrupted. For example, current leakage to a portion where the control pattern LLP is formed may be prevented.

[0115] The element layer 200 may further include a capping layer CPL disposed on the second electrode CE. The capping layer CPL may serve to improve light emission efficiency by the principle of constructive interference. The capping layer CPL may include, for example, a material having a refractive index of about 1.6 or more for light having a wavelength of about 589 nm. The capping layer CPL may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. For example, the capping layer CPL may include a carbocyclic compound, a heterocyclic compound, an amine group-containing compound, a porphyrin derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or a combination thereof. The carbocyclic compound, the heterocyclic compound, and the amine group-containing compound may be selectively substituted with substituents including oxygen (O), nitrogen (N), sulfur (S), selenium (Se), silicon (Si), fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or a combination thereof.

[0116] A packaging layer 300 may be disposed on the element layer 200. The packaging layer 300 may include a first inorganic packaging layer 310, an organic packaging layer 320, and a second inorganic packaging layer 330 that are sequentially stacked one above the other. The first inorganic packaging layer 310 and the second inorganic packaging layer 330 may protect the element layer 200 from moisture and oxygen, and the organic packaging layer 320 may protect the element layer 200 from foreign substances such as dust particles. In an embodiment, the packaging layer 300 may be formed as a single layer. For example, the packaging layer 300 may include only an inorganic packaging layer.

[0117] An optical layer 400 may be disposed on the packaging layer 300. The optical layer 400 may include a separation layer 410, a color filter 420, a cover layer 430, and a lens pattern layer 440.

[0118] The material of the separation layer 410 is not limited as long as it is a light-absorbing material. The separation layer 410 can be a black layer. In an embodiment, the separation layer 410 can include a black colorant. The black colorant can include a black dye or a black pigment. The black colorant can include carbon black, a metal such as chromium, or an oxide thereof.

[0119] The color filter 420 can be disposed to correspond to the opening defined in the separation layer 410. The color filter 420 can transmit light provided from the intermediate layer CEL that overlaps with the color filter 420. The color filter 420 can improve the color reproduction of the light provided from the intermediate layer CEL.

[0120] The cover layer 430 can cover the color filter 420. The cover layer 430 can include an organic material, but the embodiment is not limited thereto. The lens pattern layer 440 can be disposed in a region overlapping with the opening OP of the pixel defining layer PDL and can have a convexly protruding shape. However, the shape of the lens pattern layer 440 is not limited thereto. The cover layer 430 and the lens pattern layer 440 can include the same material and can have an integrated shape.

[0121] Figure 5B is a schematic cross-sectional view of a display panel DP-1 according to an embodiment. In the description Figure 5B when Figure 5A describing, components identical to those described with reference to

[0122] will be given the same reference numerals, and descriptions thereof will be omitted for convenience of description. Figure 4 and Figure 5B , the display panel DP-1 can further include a control pattern LLPa. The control pattern LLPa of the display panel DP-1 is different from Figure 5A the control pattern LLP.

[0123] The control pattern LLPa can be disposed on the pixel defining layer PDL. The control pattern LLPa can have a shape protruding from the upper surface of the pixel defining layer PDL. Therefore, the control pattern LLPa can be referred to as a protruding pattern LLPa.

[0124] The control pattern LLPa can include a lower portion and an upper portion having a greater width than the lower portion. The upper portion of the control pattern LLPa can be spaced apart from the pixel defining layer PDL and the lower portion is between the upper portion of the control pattern LLPa and the pixel defining layer PDL. For example, an end portion can be defined in the control pattern LLPa by the upper portion and the lower portion having different widths.

[0125] The intermediate layer CEL can be disposed on the first electrode AE, the pixel defining layer PDL, and the control pattern LLPa. In an embodiment, the thickness of the intermediate layer CEL can be reduced by the control pattern LLPa. For example, some of the layers included in the intermediate layer CEL can be interrupted. For example, current leakage to the portion where the control pattern LLPa is formed can be prevented.

[0126] Figure 5C is a schematic cross-sectional view of a display panel DP-2 according to an embodiment. In the description Figure 5C when, components that are the same as the components described with reference to Figure 5A will be given the same reference numerals, and descriptions thereof will be omitted for ease of description.

[0127] Reference Figure 4 and Figure 5C , the display panel DP-2 can include a circuit board 100, an element layer 200, a packaging layer 300, and an optical layer 400a. The optical layer 400a is different from the Figure 5A optical layer 400.

[0128] The optical layer 400a can include a substrate layer MLP-BS and a lens pattern layer MLP. The substrate layer MLP-BS and the lens pattern layer MLP can include the same material and can have an integral shape. The substrate layer MLP-BS and the lens pattern layer MLP can include an organic material, but the embodiment is not limited thereto. In another example, the substrate layer MLP-BS can be omitted. For example, the lens pattern layer MLP can be directly disposed on the packaging layer 300.

[0129] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B can emit light having different wavelengths. Therefore, the Figure 5A color filter 420 shown in

[0130] Figure 6A can be omitted. For example, the light efficiency of the display panel DP-2 can be further improved, and the display panel DP-2 can display an image with higher brightness. Figure 5A ) is a schematic cross-sectional view.

[0131] Reference Figure 5A and Figure 6A , the first light-emitting element 100ED-R having a first emission region PXA-R defined therein, the second light-emitting element 100ED-G having a second emission region PXA-G defined therein, and the third light-emitting element 100ED-B having a third emission region PXA-B defined therein are shown as examples.

[0132] The first electrodes AE-R of the first light-emitting element 100ED-R, the first electrodes AE-G of the second light-emitting element 100ED-G, and the first electrodes AE-B of the third light-emitting element 100ED-B may be disposed on the circuit board 100. An intermediate layer CEL covering the first electrodes AE-R, AE-G, and AE-B may be disposed on the circuit board 100.

[0133] The intermediate layer CEL may include a first functional layer HFL, first auxiliary layers RIL and R’, second auxiliary layers GIL and G’, third auxiliary layer BIL, a first emission layer REML, a second emission layer GEML, a third emission layer BEML, a buffer layer BFL, and a second functional layer EFL. However, this is illustrative, and some components included in the intermediate layer CEL may be omitted. The intermediate layer CEL may further include other components.

[0134] The first functional layer HFL may include a hole transport layer (HTL), may include a hole injection layer (HIL), or may include a hole transport layer and a hole injection layer. The first functional layer HFL may be disposed over the entire display area DA (refer to Figure 3 ). Accordingly, the first functional layer HFL may overlap with the opening OP of the pixel defining layer PDL and the control pattern LLP of the pixel defining layer PDL (refer to Figure 4 ).

[0135] The first auxiliary layers RIL and R’, the second auxiliary layers GIL and G’, and the third auxiliary layer BIL may be disposed on the first functional layer HFL. The first auxiliary layers RIL and R’, the second auxiliary layers GIL and G’, and the third auxiliary layer BIL may be layers for increasing the light-emitting efficiency of the dopant and the host, but the embodiments are not limited thereto. In the embodiments, some of the first auxiliary layers RIL and R’, the second auxiliary layers GIL and G’, and the third auxiliary layer BIL may be omitted, and other auxiliary layers may be additionally provided.

[0136] The first emission layer REML, the second emission layer GEML, and the third emission layer BEML may be respectively disposed on the first auxiliary layers RIL and R’, the second auxiliary layers GIL and G’, and the third auxiliary layer BIL. The first emission layer REML, the second emission layer GEML, and the third emission layer BEML may include an organic material, an inorganic material, or an organic-inorganic material that emits light of a certain color. The first auxiliary layers RIL and R’, the second auxiliary layers GIL and G’, and the third auxiliary layer BIL may be respectively disposed in the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B. The first emission layer REML, the second emission layer GEML, and the third emission layer BEML may be respectively disposed in the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B.

[0137] In an embodiment, the first auxiliary layers RIL and R', and the first emission layer REML may be formed using a first mask (e.g., a fine metal mask). For example, the first mask may include mask openings, and deposition materials may pass through the openings and may be deposited on a target substrate to form the first auxiliary layers RIL and R', and the first emission layer REML. The second auxiliary layers GIL and G', and the second emission layer GEML may be formed using a second mask, and the third auxiliary layer BIL and the third emission layer BEML may be formed using a third mask. The second mask and the third mask may also be fine metal masks.

[0138] In the case of forming the first emission layer REML, the second emission layer GEML, the third emission layer BEML, the first auxiliary layers RIL and R', the second auxiliary layers GIL and G', and the third auxiliary layer BIL using masks, the spacers SPC (refer to Figure 4 ) may serve to support the masks.

[0139] The buffer layer BFL may be provided throughout the first emission layer REML, the second emission layer GEML, and the third emission layer BEML. For example, the buffer layer BFL may be provided throughout the first functional layer HFL and may cover the first emission layer REML, the second emission layer GEML, the third emission layer BEML, the first auxiliary layers RIL and R', the second auxiliary layers GIL and G', and the third auxiliary layer BIL. In another example, the buffer layer BFL may be omitted.

[0140] The second functional layer EFL may be provided on the buffer layer BFL. The second functional layer EFL may include an electron transport layer (ETL), may include an electron injection layer (EIL), or may include an electron transport layer and an electron injection layer. The second functional layer EFL may be provided in the entire display area DA (refer to Figure 3 ). Thus, the second functional layer EFL may overlap with the opening OP of the pixel defining layer PDL and the control pattern LLP of the pixel defining layer PDL (refer to Figure 4 ).

[0141] The second electrode CE may be provided on the second functional layer EFL, and the capping layer CPL may be provided on the second electrode CE. The microlens arrays MLP-R, MLP-G, and MLP-B may be provided on the capping layer CPL. Refer to Figure 5A and Figure 5B The components described may be provided between the microlens arrays MLP-R, MLP-G, and MLP-B and the capping layer CPL.

[0142] Figure 6B is a schematic cross-sectional view of a display panel DP (refer to Figure 5A ) according to an embodiment. In the description Figure 6BWhen, with reference to Figure 6A Components identical to those described will be given the same reference numerals, and descriptions thereof will be omitted for ease of description.

[0143] Reference Figure 5A and Figure 6B , the intermediate layer CEL may include first functional layers HFL-R, HFL-G, and HFL-B, first auxiliary layers RIL and R', second auxiliary layers GIL and G', third auxiliary layer BIL, first emission layer REML, second emission layer GEML, third emission layer BEML, buffer layer BFL, and second functional layer EFL.

[0144] Each of the first functional layers HFL-R, HFL-G, and HFL-B may include a hole transport layer (HTL), may include a hole injection layer (HIL), or may include a hole transport layer and a hole injection layer.

[0145] In an embodiment, the first functional layers HFL-R, HFL-G, and HFL-B may be respectively disposed in a first emission region PXA-R, a second emission region PXA-G, and a third emission region PXA-B. For example, the above control pattern LLP (reference Figure 4 ) may be omitted. However, the embodiment is not limited thereto.

[0146] In an embodiment, a first mask may be used to form the first functional layer HFL-R, the first auxiliary layer RIL and R', and the first emission layer REML. A second mask may be used to form the first functional layer HFL-G, the second auxiliary layer GIL and G', and the second emission layer GEML, and a third mask may be used to form the first functional layer HFL-B, the third auxiliary layer BIL, and the third emission layer BEML.

[0147] Unlike Figure 6A and Figure 6B shown, the intermediate layer CEL may include a common emission layer that generates the same source light. The source light may be white light or blue light. For example, the common emission layer may be provided to replace Figure 6A and Figure 6B shown in the first auxiliary layers RIL and R', the second auxiliary layers GIL and G', the third auxiliary layer BIL, the first emission layer REML, the second emission layer GEML, and the third emission layer BEML. The common emission layer may be connected to the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, and may be integrally provided. However, the embodiment is not limited thereto, and the common emission layer may be patterned and formed in each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B.

[0148] In an embodiment, the common emission layer may include a first sub-emission layer, a charge generation layer, and a second sub-emission layer that are sequentially stacked one above the other. The first sub-emission layer and the second sub-emission layer may emit lights of different colors. For example, the first sub-emission layer and the second sub-emission layer may emit lights of complementary colors respectively. For example, the first sub-emission layer may emit blue light, and the second sub-emission layer may emit yellow light. Therefore, the emission layer may provide white source light, which is a combination of the light provided by the first sub-emission layer and the light provided by the second sub-emission layer. The charge generation layer may supply electrons or holes to the first sub-emission layer and the second sub-emission layer to improve the light emission efficiency.

[0149] In an embodiment, the common emission layer may include a first sub-emission layer, a first charge generation layer, a second sub-emission layer, a second charge generation layer, and a third sub-emission layer that are sequentially stacked one above the other. At least one of the first sub-emission layer, the second sub-emission layer, and the third sub-emission layer may emit light having a color different from that of the light emitted by at least another one of the first sub-emission layer, the second sub-emission layer, and the third sub-emission layer. For example, the first sub-emission layer and the third sub-emission layer may emit a first light having the same color, and the second sub-emission layer may emit a second light having a color different from that of the first light. For example, the first light and the second light may have a complementary color relationship. For example, the first sub-emission layer and the third sub-emission layer may emit blue light, and the second sub-emission layer may emit yellow light. Therefore, the common emission layer may provide white source light, which is a combination of the lights provided by the first sub-emission layer, the second sub-emission layer, and the third sub-emission layer. The first charge generation layer may supply electrons or holes to the first sub-emission layer and the second sub-emission layer to improve the light emission efficiency. For example, the second charge generation layer may supply electrons or holes to the second sub-emission layer and the third sub-emission layer to improve the light emission efficiency.

[0150] Figure 7A is an enlarged schematic plan view showing a partial region of a display panel according to an embodiment.

[0151] Reference Figure 7A , openings OP-R, OP-G, and OP-B defined in the pixel defining layer PDL are shown. The openings OP-R, OP-G, and OP-B may include a first opening OP-R, a second opening OP-G, and a third opening OP-B. The first opening OP-R, the second opening OP-G, and the third opening OP-B may be adjacent to a spacer (e.g., a single spacer) SPC.

[0152] In an embodiment, each of the first opening OP-R, the second opening OP-G, and the third opening OP-B may have a polygonal shape. For example, when viewed from above the plane (e.g., in the third direction DR3), each of the first opening OP-R, the second opening OP-G, and the third opening OP-B may have a hexagonal shape. However, this is illustrative, and the embodiment is not limited thereto.

[0153] In an embodiment, the spacer SPC may include a central portion CP, a first extension P1, a second extension P2, and a third extension P3. The central portion CP may correspond to a triangular shape (e.g., in a plan view). The first extension P1 may extend from the central portion CP to be disposed between the first opening OP-R and the second opening OP-G (e.g., in a plan view). The second extension P2 may extend from the central portion CP to be disposed between the second opening OP-G and the third opening OP-B (e.g., in a plan view). The third extension P3 may extend from the central portion CP to be disposed between the first opening OP-R and the third opening OP-B (e.g., in a plan view). Thus, when viewed from above the plane (or in a plan view), the spacer SPC may have a tripod shape.

[0154] In an embodiment, the first extension P1, the second extension P2, and the third extension P3 may extend from the central portion CP in three different directions, respectively. For example, the first extension P1 may extend in the first crossing direction CDR1, the third extension P3 may extend in the second crossing direction CDR2, and the second extension P2 may extend in a direction opposite to the second direction DR2. The first crossing direction CDR1 may be a direction between the first direction DR1 and the second direction DR2, and the second crossing direction CDR2 may be a direction between the second direction DR2 and the direction opposite to the first direction DR1.

[0155] According to an embodiment, the area of the region where the spacer SPC is disposed may be reduced in accordance with an increase in the resolution of the display panel DP (refer to Figure 5A ). In a case where the spacer SPC has a shape extending in at least three directions with a limited area, the rigidity of the spacer SPC may be improved. During deposition using a mask, the possibility of damaging the spacer SPC due to insufficient rigidity of the spacer SPC may be eliminated or reduced. Thus, the manufacturing yield and reliability of the display panel DP may be improved.

[0156] In an embodiment, the ends of the first extension part P1, the second extension part P2, and the third extension part P3 may have an arc shape. The ends of the first extension part P1, the second extension part P2, and the third extension part P3 may be disposed within a region AR defined by a virtual line connecting a first center CP-R of a first opening OP-R, a second center CP-G of a second opening OP-G, and a third center CP-B of a third opening OP-B. For example, the lengths of the first extension part P1, the second extension part P2, and the third extension part P3 may be shorter than the length LT of a side SS of each of the first opening OP-R, the second opening OP-G, and the third opening OP-B.

[0157] The first opening OP-R may include a first side SS1 facing the first extension part P1, and the second opening OP-G may include a second side SS2 facing the first extension part P1. A virtual line connecting the center of the first side SS1 and the center of the second side SS2 may be the same as a normal line extending from the center of the first side SS1. For example, the line and the normal line may be a part of the line defining the region AR. For example, the end of the first extension part P1 may be spaced apart from (or may not overlap with) the line and the normal line, or may be aligned with the line and the normal line.

[0158] According to an embodiment, the display panel DP may be implemented to have a high resolution. For example, as the resolution increases, the maximum width at which the first extension part P1, the second extension part P2, and the third extension part P3 can be disposed may decrease, and the widths of the first extension part P1, the second extension part P2, and the third extension part P3 (e.g., the widths in a direction intersecting the extension direction) may decrease. Accordingly, even when the widths of the first extension part P1, the second extension part P2, and the third extension part P3 decrease, the rigidity of the spacer SPC may be improved by restricting the extension lengths of the first extension part P2, the second extension part P2, and the third extension part P3.

[0159] Figure 7B is an enlarged schematic plan view showing a partial region of a display panel according to an embodiment. In the description Figure 7B when Figure 7A describing, components identical to those described with reference

[0160] reference Figure 7B, the spacer SPCa may include a central portion CPa, a first extension P1a, a second extension P2a, and a third extension P3a. The first extension P1a may extend (e.g., in a plan view) from the central portion CPa to be disposed between the first opening OP-R and the second opening OP-G. The second extension P2a may extend (e.g., in a plan view) from the central portion CPa to be disposed between the second opening OP-G and the third opening OP-B. The third extension P3a may extend (e.g., in a plan view) from the central portion CPa to be disposed between the first opening OP-R and the third opening OP-B.

[0161] In an embodiment, the ends of the first extension P1a, the second extension P2a, and the third extension P3a may have an angled shape. For example, the first extension P1a, the second extension P2a, and the third extension P3a may have a quadrilateral shape. The ends of the first extension P1a, the second extension P2a, and the third extension P3a may be disposed within a region AR defined by a virtual line connecting a first center CP-R of the first opening OP-R, a second center CP-G of the second opening OP-G, and a third center CP-B of the third opening OP-B. Thus, even if the first extension P1a, the second extension P2a, and the third extension P3a become narrower due to an increase in the resolution of the display panel DP (refer to Figure 5A ), the rigidity of the spacer SPCa can be improved by restricting the extension lengths of the first extension P1a, the second extension P2a, and the third extension P3a.

[0162] Figure 7C is an enlarged schematic plan view showing a partial region of a display panel according to an embodiment. In the description Figure 7C when, components identical to those described with reference to Figure 7A will be given the same reference numerals, and descriptions thereof will be omitted for convenience of description.

[0163] Reference Figure 7C , the spacer SPCb may include a central portion CPb, a first extension P1b, a second extension P2b, and a third extension P3b. The first extension P1b may extend (e.g., in a plan view) from the central portion CPb to be disposed between the first opening OP-R and the second opening OP-G. The second extension P2b may extend (e.g., in a plan view) from the central portion CPb to be disposed between the second opening OP-G and the third opening OP-B. The third extension P3b may extend (e.g., in a plan view) from the central portion CPb to be disposed between the first opening OP-R and the third opening OP-B.

[0164] In an embodiment, the ends of the first extension part P1b, the second extension part P2b, and the third extension part P3b may have a pointed shape. For example, the central part CPb and the first extension part P1b, the second extension part P2b, and the third extension part P3b may have a triangular shape. The ends of the first extension part P1b, the second extension part P2b, and the third extension part P3b may be disposed within a region AR defined by a virtual line connecting a first center CP-R of the first opening OP-R, a second center CP-G of the second opening OP-G, and a third center CP-B of the third opening OP-B. Thus, even if the first extension part P1b, the second extension part P2b, and the third extension part P3b become narrower due to an increase in the resolution of the display panel DP (refer to Figure 5A ), the rigidity of the spacer SPCb can be improved by restricting the extension lengths of the first extension part P1b, the second extension part P2b, and the third extension part P3b.

[0165] Figure 8A is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Figure 8A is a schematic cross-sectional view of the display panel taken along the line II-II’ of Figure 7A . In Figure 8A , only the circuit board 100 and the element layer 200 described with reference to Figures 5A to 5C are shown, and the encapsulation layer 300 and the optical layer 400 or 400a are omitted.

[0166] Referring to Figure 4 , Figure 7A and Figure 8A , a pixel defining layer PDL may be disposed on the circuit board 100. An opening OP for exposing a portion of the first electrode AE may be defined in the pixel defining layer PDL. The opening OP may include a first opening OP-R, a second opening OP-G, and a third opening OP-B. The region between the second opening OP-G and the third opening OP-B is shown in Figure 8A .

[0167] A control pattern LLP recessed from the upper surface of the pixel defining layer PDL may be defined in the pixel defining layer PDL. The control pattern LLP may be referred to as a valley. The control pattern LLP may surround at least a portion of the first opening OP-R, the second opening OP-G, and the third opening OP-B, respectively. Spacers SPC may be disposed between the control patterns LLP.

[0168] Spacers SPC may be disposed on the pixel defining layer PDL. In an embodiment, the spacers SPC and the pixel defining layer PDL may include an inorganic material. For example, the spacers SPC and the pixel defining layer PDL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0169] In an embodiment, a first angle AG1 of a side surface of a pixel defining layer PDL with respect to a bottom surface of the pixel defining layer PDL may be about 40 degrees or less. For example, an intermediate layer CEL provided on the pixel defining layer PDL may be stably formed. However, the first angle AG1 is merely an example and is not limited thereto. In an embodiment, a second angle AG2 of a side surface of a spacer SPC with respect to a bottom surface of the spacer SPC may be greater than or equal to the first angle AG1 of the side surface of the pixel defining layer PDL with respect to the bottom surface of the pixel defining layer PDL. Even if a part of the intermediate layer CEL or the second electrode CE is disconnected by the spacer SPC, the influence on the driving of the display panel DP (refer to Figure 5A ) may be limited because the arrangement density of the spacer SPC may be less than or equal to half of the pixel density (e.g., about 1 / 8 of the pixel density). Therefore, the second angle AG2 of the spacer SPC may be designed in various ways and is not limited to a specific angle or less.

[0170] In an embodiment, the spacer SPC may include multiple layers. For example, the spacer SPC may include a first layer SPL1, a second layer SPL2 provided on the first layer SPL1, and a third layer SPL3 provided on the second layer SPL2. A first width SWT1 of the first layer SPL1 may be greater than a second width SWT2 of the second layer SPL2. In the case where the spacer SPC has a stepped structure, monomers may flow smoothly when forming an organic encapsulation layer 320 (refer to Figure 5A ). Accordingly, the organic encapsulation layer 320 may be more easily planarized. However, the shape of the spacer SPC is not limited thereto. For example, the first width SWT1 and the second width SWT2 may be substantially the same as each other. The third layer SPL3 may be thinner than the first layer SPL1 and the second layer SPL2.

[0171] In an embodiment, each of the first layer SPL1 and the second layer SPL2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. When the first layer SPL1 and the second layer SPL2 are patterned, the third layer SPL3 may be used as a mask (e.g., a hard mask). For example, the third layer SPL3 may include a metal, a metal alloy, a metal oxide, a metal nitride, or a transparent conductive oxide. For example, the third layer SPL3 may include titanium (Ti), titanium nitride (TiN x ), nickel (Ni), gold (Au), molybdenum (Mo), indium tin oxide (ITO), or indium zinc oxide (IZO).

[0172] The intermediate layer CEL, the second electrode CE, and the capping layer CPL may be sequentially disposed on the first electrode AE, the pixel defining layer PDL, and the spacer SPC. The intermediate layer CEL may be disposed in the control pattern LLP defined in the upper surface of the pixel defining layer PDL. In an embodiment, the resistance of the intermediate layer CEL (e.g., the first functional layer HFL) may be increased by the control pattern LLP. For example, the first functional layer HFL may be disconnected (or separated) by the control pattern LLP. Accordingly, the occurrence of lateral leakage current, color mixing between adjacent pixel regions, and luminance degradation can be prevented.

[0173] The first dummy layer DMP1 may be disposed on the first layer SPL1, and the second dummy layer DMP2 may be disposed on the third layer SPL3. Each of the first dummy layer DMP1 and the second dummy layer DMP2 may include the same layers as the first functional layer HFL and the second functional layer EFL. In an embodiment, each of the first dummy layer DMP1 and the second dummy layer DMP2 may further include a layer containing the same material as the emission layer EML. In another example, a process of removing the first dummy layer DMP1 and the second dummy layer DMP2 may be added, and the first dummy layer DMP1 and the second dummy layer DMP2 may be omitted.

[0174] In an embodiment, at least one of the first layer SPL1, the second layer SPL2, and the third layer SPL3 may include a conductive material. For example, the second electrode CE may be brought into contact with at least one layer of the spacer SPC including the conductive material. Accordingly, even if the second electrode CE is disconnected by the spacer SPC, the disconnected portion may be connected through the spacer SPC. In another example, even if the resistance of the second electrode CE increases due to the spacer SPC, the increased resistance may be reduced as the spacer SPC and the second electrode CE come into contact with each other.

[0175] In an embodiment, the first thickness TK1 of the pixel defining layer PDL may be in the range of about to about , but the embodiment is not limited thereto. The second thickness TK2 of the spacer SPC may be greater than or equal to the first thickness TK1 of the pixel defining layer PDL, but the embodiment is not limited thereto.

[0176] In an embodiment, the second thickness TK2 of the spacer SPC may be greater than or equal to the maximum organic material deposition thickness that may occur during deposition using a mask. For example, referring to Figure 6A , the first thickness TK-R of the first auxiliary layer RIL and R', and the first emission layer REML, the second thickness TK-G of the second auxiliary layer GIL and G', and the second emission layer GEML, and the third thickness TK-B of the third auxiliary layer BIL and the third emission layer BEML are shown. For example, referring to Figure 6B, showing the first thickness TK-Ra of the first functional layer HFL-R, the first auxiliary layers RIL and R', and the first emission layer REML, the second thickness TK-Ga of the first functional layer HFL-G, the second auxiliary layers GIL and G', and the second emission layer GEML, and the third thickness TK-Ba of the first functional layer HFL-B, the third auxiliary layer BIL, and the third emission layer BEML.

[0177] In an embodiment, the second thickness TK2 of the spacer SPC may be defined as greater than or equal to the sum of the two largest thicknesses among the first thickness TK-R, the second thickness TK-G, and the third thickness TK-B. In another example, the second thickness TK2 of the spacer SPC may be defined as greater than or equal to the sum of the two largest thicknesses among the first thickness TK-Ra, the second thickness TK-Ga, and the third thickness TK-Ba. For example, the first thickness TK-R, the second thickness TK-G, and the third thickness TK-B may be about 0.25 μm, about 0.2 μm, and about 0.15 μm, respectively. For example, the second thickness TK2 of the spacer SPC may be about 0.45 μm or greater. However, these are merely thicknesses determined in consideration of the alignment error of the mask, and the embodiments are not limited thereto.

[0178] In an embodiment, the second thickness TK2 of the spacer SPC may be defined as greater than or equal to the largest thickness among the first thickness TK-R, the second thickness TK-G, and the third thickness TK-B. In another example, the second thickness TK2 of the spacer SPC may be defined as greater than or equal to the largest thickness among the first thickness TK-Ra, the second thickness TK-Ga, and the third thickness TK-Ba. For example, the second thickness TK2 of the spacer SPC may be about 0.25 μm or greater or about 0.3 μm or greater.

[0179] In an embodiment, the pixel defining layer PDL may have a first width WT1. The first width WT1 may correspond to the distance between the adjacent openings OP-G and OP-B among the openings OP-R, OP-G, and OP-B. As the resolution of the display panel DP increases, the first width WT1 may decrease. For example, the first width WT1 may be several μm. For example, the first width WT1 may range from about 2 μm to dozens of μm. For example, the first width WT1 may be about 2 μm.

[0180] The width WT2 of the region where the spacer SPC is formed may correspond to a value obtained by subtracting the widths WTa1 and WTa2 of the tapered regions, the widths WTb1 and WTb2 of the regions where the control pattern LLP is formed, and the width of the process margin from the first width WT1 of the pixel defining layer PDL. The width WT2 may be defined as the second width WT2 of the spacer SPC. For example, when the first width WT1 of the pixel defining layer PDL is about 2 μm or more, the second width WT2 of the spacer SPC may be about 0.6 μm or more. However, the values are illustrative, and the embodiments are not limited thereto. For example, the process margin may vary according to the exposure equipment, and the widths WTa1 and WTa2 of the tapered regions may change according to the material of the pixel defining layer PDL. Therefore, the second width WT2 of the spacer SPC is not limited to a specific value.

[0181] Figure 8B is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. In the description Figure 8B when, components identical to those described with reference to Figure 8A will be given the same reference numerals, and descriptions thereof will be omitted for convenience of description.

[0182] Referring to Figure 7A and Figure 8B , the spacer SPC-1 may be disposed on the pixel defining layer PDL.

[0183] In an embodiment, the spacer SPC-1 may include multiple layers. For example, the spacer SPC-1 may include a first layer SPL1a and a second layer SPL2a disposed on the first layer SPL1a. The second layer SPL2a may be thinner than the first layer SPL1a. When the first layer SPL1a is patterned, the second layer SPL2a may be used as a mask (e.g., a hard mask).

[0184] Figure 8C is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. In the description Figure 8C when, components identical to those described with reference to Figure 8A will be given the same reference numerals, and descriptions thereof will be omitted for convenience of description.

[0185] Referring to Figure 7A and Figure 8C , the spacer SPC-2 may be disposed on the pixel defining layer PDL. The spacer SPC-2 may have a single-layer structure or a multi-layer structure. The spacer SPC-2 may include an inorganic material.

[0186] In an embodiment, a second angle AG2a of a side surface of the spacer SPC-2 with respect to a bottom surface of the spacer SPC-2 may be greater than or equal to a first angle AG1 of a side surface of the pixel defining layer PDL with respect to a bottom surface of the pixel defining layer PDL. The first angle AG1 may be about 40 degrees or less, and the second angle AG2a may be about 90 degrees. However, the numerical values of the first angle AG1 and the second angle AG2a are illustrative, and the embodiment is not limited thereto.

[0187] Figure 8D is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. In the description Figure 8D when, components identical to those described with reference to Figure 8A will be given the same reference numerals, and descriptions thereof will be omitted for convenience of description.

[0188] Reference Figure 7A and Figure 8D , the spacer SPC-3 may be disposed on the pixel defining layer PDL. The spacer SPC-3 may include a first layer SPL1b and a second layer SPL2b. Each of the first layer SPL1b and the second layer SPL2b may have a single-layer structure or a multi-layer structure. Each of the first layer SPL1b and the second layer SPL2b may include an inorganic material.

[0189] Figure 8E is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. In the description Figure 8E when, components identical to those described with reference to Figure 8A will be given the same reference numerals, and descriptions thereof will be omitted for convenience of description.

[0190] Reference Figure 7A and Figure 8E , the spacer SPC-4 may be disposed on the pixel defining layer PDL. The spacer SPC-4 may include a first layer SPL1c, a second layer SPL2c, and a third layer SPL3c. Each of the first layer SPL1c, the second layer SPL2c, and the third layer SPL3c may have a single-layer structure or a multi-layer structure. Each of the first layer SPL1c, the second layer SPL2c, and the third layer SPL3c may include an inorganic material.

[0191] A first width of the first layer SPL1c may be greater than a second width of the second layer SPL2c, and the second width of the second layer SPL2c may be greater than a third width of the third layer SPL3c. However, the embodiment is not limited thereto.

[0192] Reference Figures 8A to 8E The cross-sectional structures of the spacers SPC and SPC-1 to SPC-4 described may be applied to reference Figures 7A to 7CPlanar structures of the described spacers SPC, SPCa, and SPCb.

[0193] Figure 9 is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. In the description Figure 9 when, components identical to those described in the reference Figure 8A description will be given the same reference numerals, and descriptions thereof will be omitted for ease of description.

[0194] Reference Figure 4 、 Figure 7A and Figure 9 , the control pattern LLPa can be provided on the pixel defining layer PDL. The control pattern LLPa can be referred to as a protruding pattern. The second thickness TK2 of the spacer SPC can be greater than or equal to the third thickness TK3 of each of the control patterns LLPa. The spacer SPC can be provided between the control patterns LLPa.

[0195] The intermediate layer CEL can be provided on the first electrode AE, the pixel defining layer PDL, and the control pattern LLPa. In an embodiment, the thickness of the intermediate layer CEL (e.g., the first functional layer HFL) can be reduced by the control pattern LLPa. In another example, the first functional layer HFL can be disconnected by the control pattern LLPa. For example, current leakage to the portion where the control pattern LLPa is formed can be prevented.

[0196] According to the above description, the area of the region where the spacer is to be provided can decrease as the resolution of the display panel increases. The spacer can have a shape extending in at least three directions. Thus, the rigidity of the spacer can be improved. In addition, even if the width of the extension portion of the spacer decreases due to the limited area, the rigidity of the spacer can be improved by restricting the extension length of the extension portion. Therefore, during deposition using a mask, the possibility of damaging the spacer due to insufficient rigidity can be eliminated or reduced. Consequently, the manufacturing yield and reliability of the display panel can be improved.

[0197] In summarizing the detailed description, those skilled in the art will understand that many variations and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of the present disclosure. Therefore, the disclosed embodiments are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display panel, characterized in that, The display panel includes: An element layer, the element layer including: A plurality of light-emitting elements connected to a pixel circuit; A pixel defining layer having a plurality of openings respectively overlapping the plurality of light-emitting elements; and Spacers disposed on the pixel defining layer, wherein, The plurality of openings include a first opening, a second opening, and a third opening, and each of the first opening, the second opening, and the third opening is adjacent to the spacer, The spacer includes: A central portion disposed between the first opening, the second opening, and the third opening; A first extension extending from the central portion to be disposed between the first opening and the second opening; A second extension extending from the central portion to be disposed between the second opening and the third opening; and A third extension extending from the central portion to be disposed between the third opening and the first opening, and Ends of the first extension, ends of the second extension, and ends of the third extension are disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

2. The display panel according to claim 1, wherein The spacer includes a plurality of layers, and At least one of the plurality of layers is a conductive material layer.

3. The display panel according to claim 1, wherein The spacer includes: A first layer having a first width; and A second layer disposed on the first layer and having a second width smaller than the first width of the first layer.

4. The display panel according to claim 1, wherein The spacer includes a plurality of spacers, The plurality of spacers include a first spacer and a second spacer closest to the first spacer, and At least two of the plurality of light-emitting elements are disposed between the first spacer and the second spacer.

5. The display panel according to claim 1, wherein Each of the first opening, the second opening, and the third opening has a polygonal shape.

6. The display panel according to claim 5, wherein The first opening includes a first side facing the first extension, The second opening includes a second side facing the first extension, and The end of the first extension is aligned with or spaced apart from a virtual line connecting the center of the first side and the center of the second side.

7. The display panel according to claim 1, characterized in that, The ends of the first extension, the ends of the second extension, and the ends of the third extension have a circular shape, an angular shape, or a pointed shape.

8. The display panel according to claim 1, wherein A first angle of a side surface of the pixel defining layer defining the first opening with respect to a bottom surface of the pixel defining layer is about 40 degrees or less.

9. The display panel according to claim 8, wherein, A second angle of a side surface of the spacer with respect to a bottom surface of the spacer is greater than or equal to the first angle.

10. The display panel according to claim 1, wherein The spacer is thicker than the pixel defining layer.

11. The display panel according to claim 1, wherein A plurality of valleys recessed from the upper surface of the pixel defining layer are provided in the pixel defining layer, and the plurality of valleys respectively surround at least a part of the first opening, the second opening, and the third opening.

12. The display panel according to claim 11, wherein The spacers are provided between the plurality of valleys.

13. The display panel according to claim 1, wherein, The display panel further includes: a plurality of protruding patterns provided on the pixel defining layer, wherein the plurality of protruding patterns respectively surround at least a part of the first opening, the second opening, and the third opening.

14. The display panel according to claim 13, wherein The spacers have a thickness greater than the thickness of the plurality of protruding patterns.

15. A display panel, characterized in that, The display panel includes: an element layer, the element layer including: a light-emitting element connected to a pixel circuit and including a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a part of the first electrode; and spacers provided on the pixel defining layer, wherein the spacers include a central portion and a first extension portion, a second extension portion, and a third extension portion respectively protruding from the central portion in three directions.

16. The display panel according to claim 15, wherein, A first angle of a side surface of the pixel defining layer defining the opening with respect to a bottom surface of the pixel defining layer is less than or equal to a second angle of a side surface of the spacer with respect to a bottom surface of the spacer.

17. The display panel according to claim 15, characterized in that, The first angle of the side surface of the pixel defining layer defining the opening with respect to the bottom surface of the pixel defining layer is about 40 degrees or less.

18. The display panel according to claim 15, characterized in that, The spacers are thicker than the pixel defining layer.

19. The display panel according to claim 15, wherein the spacers include a plurality of layers, and at least one of the plurality of layers is a conductive material layer.

20. The display panel according to claim 15, wherein The spacers include: a first layer having a first width; and a second layer provided on the first layer and having a second width smaller than the first width.

21. The display panel according to claim 15, wherein the opening has a polygonal shape and includes a first side facing the first extension portion, and an end of the first extension portion is aligned with or spaced from a normal line extending from the center of the first side.

22. The display panel according to claim 15, wherein the spacers include a plurality of spacers, the plurality of spacers include a first spacer and a second spacer closest to the first spacer, the light-emitting element includes a plurality of light-emitting elements, and at least two of the plurality of light-emitting elements are provided between the first spacer and the second spacer.

23. A display panel, characterized in that, The display panel includes: an element layer, the element layer including: a light-emitting element connected to a pixel circuit and including a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a part of the first electrode; and spacers provided on the pixel defining layer, wherein the spacers include a central portion and a first extension portion, a second extension portion, and a third extension portion respectively protruding from the central portion in three directions, and A first angle of a side surface of the pixel defining layer that defines the opening with respect to a bottom surface of the pixel defining layer is about 40 degrees or less.

24. The display panel according to claim 23, wherein A second angle of a side surface of the spacer with respect to a bottom surface of the spacer is greater than or equal to the first angle.

25. The display panel according to claim 23, wherein the spacer includes a plurality of layers, and at least one of the plurality of layers is a conductive material layer.

26. The display panel according to claim 23, wherein The spacer includes: a first layer having a first width; and a second layer disposed on the first layer and having a second width smaller than the first width.

27. An electronic device, characterized in that, The electronic device includes: a display panel that displays an image; and a housing that houses the display panel, wherein the display panel includes: an element layer including: a plurality of light-emitting elements connected to a pixel circuit; a pixel defining layer having a plurality of openings respectively overlapping the plurality of light-emitting elements; and a spacer disposed on the pixel defining layer, the plurality of openings include a first opening, a second opening, and a third opening, each of the first opening, the second opening, and the third opening being adjacent to the spacer, and the spacer includes: a central portion disposed between the first opening, the second opening, and the third opening; a first extension portion extending from the central portion to be disposed between the first opening and the second opening; a second extension portion extending from the central portion to be disposed between the second opening and the third opening; and a third extension portion extending from the central portion to be disposed between the third opening and the first opening, and ends of the first extension portion, ends of the second extension portion, and ends of the third extension portion are disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

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