Detection device
Through the combination of signal receiver, downfrequency processor and phase locker, the detection sensitivity problem of the analog phase lock amplification structure in high-frequency excitation occasions is solved, and low-cost high-frequency detection is achieved.
Patent Information
- Application Number
- CN202422131007.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-30
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-08-30
AI Technical Summary
The existing analog phase-locked amplification structure is limited by the bandwidth of the analog device and cannot be applied to high-frequency excitation occasions, resulting in limited detection sensitivity.
The combination of signal receiver, downfrequency processor, phase locker and signal converter is adopted to sample and maintain the high-frequency eddy current signal through the downfrequency processor to generate low-frequency signals, and bypass the performance bottleneck of analog phase locker at high frequencies.
The frequency range of detection or measurement is broadened, the cost is reduced, and the application of analog phase-locked amplification structure in high-frequency excitation occasions is realized.
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Figure CN223091899U_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electromagnetic non-destructive testing technology, and particularly to a detection device. Background Art
[0002] In existing eddy current detection devices, phase-locked amplification technology is commonly used for extracting small signals. Phase-locked amplification is divided into two categories: analog phase-locked amplification and digital phase-locked amplification. Analog phase-locked amplification has a relatively simple structure, low cost, high frequency stability, good phase consistency, strong noise suppression ability, and relatively simple post-processing of signals. However, limited by the bandwidth of analog devices, it cannot be applied to occasions with high-frequency excitation, resulting in limited detection sensitivity and being unsuitable for occasions requiring high detection sensitivity. Digital phase-locked amplification has high precision and can achieve very accurate small-phase detection; it has high stability and is not affected by factors such as temperature and device drift, being suitable for long-term stable operation; it has a high bandwidth and is suitable for high-frequency excitation, being able to meet the requirements of high-sensitivity detection. But it has high cost and a complex system.
[0003] How to broaden the detection frequency range of the analog phase-locked amplification structure and realize the application of the low-cost analog phase-locked amplification structure to occasions with high-frequency excitation is an urgent problem to be solved. Summary of the Utility Model
[0004] In view of the above problems, this application provides a detection device to solve the technical problem that the analog phase-locked amplification structure in the prior art is limited by the bandwidth of analog devices and cannot be applied to occasions with high-frequency excitation.
[0005] A detection device, the detection device includes a signal receiver, a frequency-down converter, a phase-locker, and a signal converter. The signal receiver is used to receive an eddy current signal of a first frequency; the frequency-down converter is coupled to the signal receiver and is configured to obtain the instantaneous voltage of the eddy current signal according to a second frequency to obtain a low-frequency signal; wherein, the second frequency is set to be lower than the first frequency; the phase-locker is coupled to the frequency-down converter and is configured to generate a phase-locked signal according to the phase and frequency of the low-frequency signal; the signal converter is coupled to the phase-locker and is used to perform level sampling on the phase-locked signal to generate a level signal.
[0006] Further, the frequency-down converter includes a sample-and-hold module, and the sample-and-hold module is coupled to the output end of the signal receiver and is used to collect the instantaneous voltage of the eddy current signal and hold it for a preset time.
[0007] Further, the frequency-down converter further includes a filtering module, and the filtering module is coupled to the output end of the sample-and-hold module and is used to filter out high-frequency signals.
[0008] Further, the frequency-down converter further includes a sampling switching module coupled to the sample-and-hold module. The sampling switching module includes a first switch and a second switch, and the sample-and-hold module includes an amplifier. A first input terminal of the amplifier is coupled to the signal receiver through the first switch and is coupled to an output terminal of the amplifier through a first capacitor. A second input terminal of the amplifier is grounded. The second switch is coupled to the output terminal of the amplifier and is coupled to the signal receiver. The first switch and the second switch are configured such that the on and off states of the first switch and the second switch are not synchronized.
[0009] Further, when the first switch is on and the second switch is off, the sample-and-hold module samples the instantaneous voltage.
[0010] Further, when the first switch is off and the second switch is on, the sample-and-hold module holds the instantaneous voltage.
[0011] Further, the filtering module is an LC three-stage filtering circuit.
[0012] Further, the second switch is coupled to the output terminal of the amplifier through a third resistor.
[0013] Further, the phase-locked loop includes a phase-sensitive detector. The phase-sensitive detector has a first input terminal, a second input terminal, and an output terminal. Its first input terminal is coupled to the output terminal of the frequency-down converter for receiving the low-frequency signal, and its second input terminal receives a reference signal. The phase-sensitive detector is configured to multiply the low-frequency signal by the reference signal to obtain a phase-locked signal characterizing the phase difference information between the low-frequency signal and the reference signal.
[0014] Further, the filtering module is coupled to the second input terminal of the phase-sensitive detector through a phase adjustment module and a square-wave conversion module in sequence to provide the reference signal.
[0015] This application relates to a detection device. By adding a frequency-down converter, the acquired high-frequency eddy current signal is sampled and held to obtain a low-frequency signal. The high-frequency signal is frequency-down converted by the frequency-down converter, bypassing the performance bottleneck of the analog phase-locked loop at high frequencies, broadening the frequency range of detection or measurement. Compared with directly using a digital lock-in amplifier, the cost of using an analog lock-in amplifier plus the pre-processing of sample-and-hold is usually lower. BRIEF DESCRIPTION OF THE DRAWINGS
[0016] Figure 1 It is a schematic diagram of the detection device of this application;
[0017] Figure 2 It is a schematic diagram of the frequency-down converter in the detection device of this application;
[0018] Figure 3 Schematic diagram of the circuit of the frequency - down processor of the detection device of the present application;
[0019] Figure 4 Schematic diagram of the circuit connection of the first switch and the second switch in the frequency - down processor of the present application;
[0020] Figure 5 Schematic diagram of the phase - locked loop in the detection device of the present application.
[0021] Explanation of reference numerals
[0022] 1. Signal receiver; 2. Frequency - down processor; 21. Sample - and - hold module; 22. Filter module; 23. Sampling switching module; 3. Phase - locked loop; 31. Phase - sensitive detector; 32. Phase adjustment module; 33. Square - wave conversion module; 34. Low - pass filter; 4. Signal converter. Detailed implementation manners
[0023] In order to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference only and are not intended to limit the embodiments of the present disclosure. In the following technical description, for the sake of explanation, a sufficient understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, well - known structures and devices can be shown in a simplified manner.
[0024] The terms "first", "second", etc. in the specification and claims of the embodiments of the present disclosure and the above - mentioned accompanying drawings are used to distinguish similar objects and do not necessarily describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so as to implement the embodiments of the present disclosure described here. In addition, the terms "include" and "have" and any variations thereof are intended to cover non - exclusive inclusion.
[0025] In addition, the terms "set", "connect", "fix" should be understood in a broad sense. For example, "connect" can be a fixed connection, a detachable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be directly connected, or indirectly connected through an intermediate medium, or there is internal communication between two devices, elements or components. For those of ordinary skill in the art, the specific meanings of the above - mentioned terms in the embodiments of the present disclosure can be understood according to specific circumstances.
[0026] The term "and / or" describes the associated relationship of objects and indicates that three relationships can exist. For example, A and / or B means: A or B, or, A and B these three relationships.
[0027] It should be noted that, without conflict, the embodiments in the present disclosure and the features in the embodiments may be combined with each other.
[0028] For a further understanding of the purpose, structure, features, and functions of the present application, the following is a detailed description in conjunction with the attached Figures 1-4 and embodiments.
[0029] During the eddy current detection process, a high-frequency excitation circuit generates a high-frequency voltage signal. After the voltage-to-current conversion, it acts on the detection coil. When current flows through the detection coil, a magnetic field is generated. This magnetic field induces eddy currents in the object to be measured. The magnitude and distribution of the eddy currents are related to factors such as the material, shape, and defects of the object to be measured. Finally, the signal obtained from the detection coil is a high-frequency voltage signal. Although the analog lock-in amplifier structure has low cost and strong noise suppression ability, it is limited by the bandwidth of analog devices and cannot be applied to high-frequency excitation occasions. To solve this problem, the present application provides a detection device to broaden the frequency range detected by the analog lock-in amplifier structure and realize the application of the low-cost analog lock-in amplifier structure in high-frequency excitation occasions.
[0030] Specifically, refer to Figure 1 , Figure 2 , Figure 3 , Figure 4 and Figure 5 , the present application provides a detection device. The detection device includes a signal receiver 1, a frequency-down converter 2, a phase-locked loop 3, and a signal converter 4. The signal receiver 1 is used to receive the eddy current signal of the first frequency; the frequency-down converter 2 is coupled to the signal receiver 1 and is configured to obtain the instantaneous voltage modulation of the eddy current signal according to the second frequency to obtain a low-frequency signal. Specifically, after the frequency-down converter 2 obtains the instantaneous voltage of the eddy current signal of the first frequency at the second frequency, it samples and holds it and embeds it in a low-frequency carrier to obtain a low-frequency signal; wherein, the second frequency is set to be lower than the first frequency; the phase-locked loop 3 is coupled to the frequency-down converter 2 and is configured to generate a phase-locked signal according to the phase and frequency of the low-frequency signal.
[0031] The phase-locked signal is a signal obtained by locking the phase and frequency of the low-frequency signal and then amplifying the signal component with a specific phase difference.
[0032] The specific phase difference is the signal component in phase with the reference signal input to the phase-locked loop 3.
[0033] The signal converter 4 is coupled to the phase-locked loop 3 and is used to perform level sampling on the phase-locked signal to generate a level signal for subsequent processing. Specifically, the phase-locked signal output by the phase-locked loop 3 is a low-frequency analog signal. The signal converter 4 performs level sampling on the low-frequency analog signal at a certain frequency and converts the low-frequency analog signal into a digital level signal for subsequent processing.
[0034] Among them, the eddy current signal of the first frequency received by the signal receiver 1 is the high-frequency voltage signal obtained from the detection coil.
[0035] For example, for the setting of the first frequency and the second frequency, the first frequency is 5M, and the second frequency is set to 4.5M. The specific setting of the second frequency is determined according to the actual situation, and this application does not make any restrictions.
[0036] In an embodiment of the present application, the frequency-down converter 2 includes a sample-and-hold module 21. The sample-and-hold module 21 is coupled to the output end of the signal receiver 1 and is used to collect the instantaneous voltage of the eddy current signal at a specific sampling time point and hold it for a preset time. The sampling frequency of the sample-and-hold module 21 is the second frequency, which is preset according to the actual situation. The second frequency is lower than the first frequency. The sample-and-hold module 21 realizes the frequency-down processing of the signal by setting the second frequency of sampling, so that the high-frequency eddy current signal can be converted into a low-frequency signal that is easier to process and analyze.
[0037] In an embodiment of the present application, the frequency-down converter 2 further includes a filtering module 22. The filtering module 22 is coupled to the output end of the sample-and-hold module 21 and is used to filter out unnecessary high-frequency signals that still exist after passing through the sample-and-hold module 21 and retain the useful low-frequency signals for the phase-locked loop 3 to process.
[0038] The frequency-down converter 2 further includes a sampling switching module 23 coupled to the sample-and-hold module 21. The sampling switching module includes a first switch S1 and a second switch S2. The sample-and-hold module 21 includes an amplifier U1.
[0039] The first input terminal of the amplifier U1 is coupled to the signal receiver 1 through the first switch S1 to obtain the eddy current signal of the first frequency; the first input terminal of the amplifier U1 is also coupled to the output end of the amplifier U1 through a first capacitor C1. The second input terminal of the amplifier U1 is grounded; the second switch S2 is coupled to the output end of the amplifier U1 and is coupled to the signal receiver 1. Specifically, the first end of the second switch S2 is grounded, the second end of the second switch S2 is coupled to the output end of the amplifier U1 through a third resistor R3, and the second end of the second switch S2 is simultaneously coupled to the signal receiver 1.
[0040] When the first switch S1 is turned on and the second switch S2 is turned off, the amplifier U1 of the sample and hold module 21 samples the instantaneous voltage of the eddy current signal at the first frequency. When the sample and hold module 21 samples, the first capacitor C1 is charged according to this high-frequency voltage signal, and the sample and hold module 21 is in the sampling stage; when the first switch S1 is turned off and the second switch S2 is turned on, at this time, the sample and hold module 21 conducts the obtained eddy current signal at the first frequency to the ground through the second switch S2, and the charge at both ends of the first capacitor C1 remains unchanged, and the sample and hold module 21 is in the hold stage.
[0041] In an embodiment of the present application, the model of the amplifier U1 is LT1399. The amplifier U1 is powered by the fourth voltage V4 and the fifth voltage V5. The first input terminal of the amplifier U1 is the inverting input terminal, and the second input terminal of the amplifier U1 is the non-inverting input terminal.
[0042] The first switch S1 and the second switch S2 are configured such that the on and off states of the first switch S1 and the second switch S2 are not synchronized to achieve the separation of the sampling and holding states.
[0043] In an embodiment of the present application, the model of the switch is HI9P0201HS-9Z. HI9P0201HS-9Z is a 4-channel switch with 16 pins. The electrical connection of HI9P0201HS-9Z in the present application can be seen Figure 4 , specifically: select the third channel A3 as the second switch S2, the fourth channel A4 as the first switch S1. The positive control terminal of HI9P0201HS-9Z is connected to the second voltage signal V2, and the negative control terminal of HI9P0201HS-9Z is grounded; the 9th pin of the third channel A3 is connected to the first voltage signal V1, the input terminal IN3 of the third channel A3 is grounded, and the output terminal OUT3 of the third channel A3 is connected to the inverting input terminal of the amplifier U1; the 8th pin of the fourth channel A4 is connected to the first voltage signal V1 through an inverter, the input terminal IN4 of the fourth channel A4 is connected to the signal receiver 1 through the first resistor R1 for obtaining the eddy current signal at the first frequency, and the output terminal OUT4 of the fourth channel A4 is connected to the output terminal of the amplifier U1 through the resistor R3.
[0044] When the first voltage signal V1 is at a high level, the first switch S1 is turned off and the second switch S2 is turned on at the same time. Specifically: when the first voltage signal V1 is at a high level, the third channel A3 receives a high-level signal, enabling the third channel A3 to conduct, that is, the second switch S2 is turned on, and the fourth channel A4 receives a low-level signal, enabling the fourth channel A4 to be turned off, that is, the first switch S1 is turned off.
[0045] When the first voltage signal V1 is at a low level, the first switch S1 is turned on and the second switch S2 is turned off. Specifically: when the first voltage signal V1 is at a low level, the third channel A3 receives a low-level signal, causing the third channel A3 to be turned off, that is, the second switch S2 is turned off, and the fourth channel A4 receives a high-level signal, causing the fourth channel A4 to be turned on, that is, the first switch S1 is turned on.
[0046] The first switch S1 and the second switch S2 are configured such that: according to the first control signal, the on and off states of the first switch S1 and the second switch S2 are not synchronized.
[0047] When the sample and hold module 21 needs to sample, the first voltage signal V1 is set to a high level, the first switch S1 is turned on and the second switch S2 is turned off. When the sample and hold module 21 needs to hold the signal, the first voltage signal V1 is set to a low level, the first switch S1 is turned off and the second switch S2 is turned on.
[0048] In this way, the on and off states of the first switch S1 and the second switch S2 are controlled by the first control signal and are not synchronized.
[0049] When the first switch S1 is turned on and the second switch S2 is turned off, the amplifier U1 of the sample and hold module 21 samples the instantaneous voltage value of the eddy current signal of the first frequency. When the first switch S1 is turned on, the eddy current signal of the first frequency is transmitted from the signal receiver 1 to the first input terminal of the amplifier U1, charging the first capacitor C1. At the same time, the amplifier U1 amplifies the sampled instantaneous voltage value and outputs it from its output terminal.
[0050] When the first switch S1 is turned off and the second switch S2 is turned on, the sample and hold module 21 holds the instantaneous voltage value. When the first switch S1 is turned off, at the same time, the second switch S2 is turned on, and the eddy current signal of the first frequency is transmitted to the ground through the second switch S2. During this process, the signal at the output terminal of the amplifier U1 is held for a period of time. Even if the voltage of the eddy current signal of the first frequency changes, the output voltage at the output terminal of the amplifier U1 remains unchanged.
[0051] Preferably, the filtering module 22 is coupled to the output end of the sampling and holding module 21 via a fourth resistor R4. The filtering module 22 is an LC three-stage filtering circuit. Specifically, the filtering module 22 includes a second capacitor C2, a third capacitor C3, a fourth capacitor C4, a fifth capacitor C5, a first inductor L1, a second inductor L2, a third inductor L3, and a second resistor R2. The first end of the second capacitor C2 is coupled to the output end of the amplifier U1 via the fourth resistor R4, and the second end of the second capacitor C2 is coupled to the ground. The first end of the first inductor L1 is coupled to the first end of the second capacitor C2, and the second end of the first inductor L1 is grounded through the third capacitor C3. The first inductor L1 and the third capacitor C3 form a first filtering circuit. The first end of the second inductor L2 is coupled to the second end of the first inductor L1, and the second end of the second inductor L2 is grounded through the fourth capacitor C4. The second inductor L2 and the fourth capacitor C4 form a second filtering circuit. The first end of the third inductor L3 is coupled to the second end of the second inductor L2, and the second end of the third inductor L3 is grounded through the second resistor R2. The fifth capacitor C5 is connected in parallel with the second resistor R2 and then in series with the third inductor L3. The third inductor L3, the fifth capacitor C5, and the second resistor R2 form a third filtering circuit.
[0052] The first filtering circuit, the second filtering circuit, and the third filtering circuit perform filtering for different frequency ranges to achieve a filtering effect in a wider frequency band, effectively reducing noise and interference.
[0053] In an embodiment, the second switch S2 is coupled to the output end of the amplifier U1 via a third resistor R3. Specifically, the second end of the second switch S2 is coupled to the output end of the amplifier U1 via the third resistor R3, and the first end of the second switch S2 is grounded.
[0054] The resistance value of the third resistor R3 affects the time constant of the sampling and holding module 21 during the holding stage, that is, the attenuation speed of the signal during the holding stage.
[0055] In an embodiment of the present application, the resistance value of the third resistor R3 is set to 1000 ohms. By adjusting the resistance value of the third resistor R3, the holding time of the sampling and holding module 21 for holding the signal can be adjusted.
[0056] Preferably, the phase-locked loop 3 includes a phase-sensitive detector 31. The phase-sensitive detector 31 has a first input end, a second input end, and an output end. Its first input end is coupled to the output end of the down-conversion processor 2. Specifically, the first input terminal of the phase-sensitive detector 31 is coupled to the output end of the filtering module 22 of the down-conversion processor 2 for receiving the low-frequency signal output by the filtering module 22, and its second input end receives a reference signal.
[0057] The phase-sensitive detector 31 is configured to multiply the low-frequency signal by the reference signal to obtain a phase-locked signal characterizing the phase difference information between the low-frequency signal and the reference signal. The phase-locked signal is a signal obtained by amplifying the component with the same phase as the reference signal after locking the phase and frequency of the low-frequency signal.
[0058] In one embodiment, the filtering module 22 is sequentially coupled to the second input terminal of the phase-sensitive detector 31 via a phase adjustment module 32 and a square-wave conversion module 33 to provide the reference signal. That is, the reference signal of the phase-sensitive detector 31 can be obtained by sequentially performing phase adjustment and square-wave conversion on the low-frequency signal output by the filtering module 22 in the down-conversion processor 2.
[0059] In another embodiment, the reference signal can also be an externally connected reference signal according to actual requirements, and the present application does not make specific limitations.
[0060] The present application relates to a detection device. The detection device includes a signal receiver 1, a down-conversion processor 2, a phase-locked loop 3, and a signal converter 4. The signal receiver 1 is used to receive an eddy current signal of a first frequency. The down-conversion processor 2 is coupled to the signal receiver 1 and is configured to obtain the instantaneous voltage of the eddy current signal according to a second frequency to obtain a low-frequency signal. Wherein, the second frequency is set to be lower than the first frequency. The phase-locked loop 3 is coupled to the down-conversion processor 2 and is configured to generate a phase-locked signal according to the phase and frequency of the low-frequency signal. The signal converter 4 is coupled to the phase-locked loop 3 and is used to perform level sampling on the phase-locked signal to generate a level signal. By down-converting the high-frequency signal through the down-conversion processor 2, the performance bottleneck of the analog phase-locked loop at high frequencies is bypassed, and the frequency range of detection or measurement is broadened. Compared with directly using a digital lock-in amplifier, the cost of using an analog lock-in amplifier plus a sampling and holding front-end process is usually lower.
[0061] In the description of this specification, the description of reference terms such as "one embodiment", "some embodiments", "example", "specific example", or "some examples" means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. Moreover, the specific features, structures, materials, or characteristics described can be combined in a suitable manner in any one or more embodiments or examples. In addition, without conflict, those skilled in the art can combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.
[0062] The present application has been described by the above relevant embodiments. However, the above embodiments are only examples for implementing the present application. It is necessary to point out that the disclosed embodiments do not limit the scope of the present application. On the contrary, modifications and refinements made without departing from the spirit and scope of the present application fall within the scope of patent protection of the present application.
Claims
1. A detection device, characterized in that, The detection device includes: A signal receiver for receiving eddy current signals of a first frequency; A frequency-down converter coupled to the signal receiver and configured to obtain an instantaneous voltage of the eddy current signal according to a second frequency to obtain a low-frequency signal; wherein the second frequency is set to be lower than the first frequency; A phase-locked loop coupled to the frequency-down converter and configured to generate a phase-locked signal according to the phase and frequency of the low-frequency signal; A signal converter coupled to the phase-locked loop for performing level sampling on the phase-locked signal to generate a level signal.
2. The detection device according to claim 1, characterized in that, The frequency-down converter includes a sample-and-hold module, and the sample-and-hold module is coupled to the output end of the signal receiver for collecting the instantaneous voltage of the eddy current signal and holding it for a preset time.
3. The detection device according to claim 2, wherein, The frequency-down converter further includes a filtering module, and the filtering module is coupled to the output end of the sample-and-hold module for filtering out high-frequency signals.
4. The detection device according to claim 2, characterized in that, The frequency-down converter further includes a sampling switching module coupled to the sample-and-hold module. The sampling switching module includes a first switch and a second switch. The sample-and-hold module includes an amplifier. A first input end of the amplifier is coupled to the signal receiver through the first switch and is coupled to the output end of the amplifier through a first capacitor. A second input end of the amplifier is grounded; The second switch is coupled to the output end of the amplifier and is coupled to the signal receiver; The first switch and the second switch are configured such that the on and off states of the first switch and the second switch are not synchronized.
5. The detection device according to claim 4, wherein When the first switch is on and the second switch is off, the sample-and-hold module collects the instantaneous voltage.
6. The detection device according to claim 4, wherein, When the first switch is off and the second switch is on, the sample-and-hold module holds the instantaneous voltage.
7. The detection device according to claim 3, wherein, The filtering module is an LC three-stage filtering circuit.
8. The detection device according to claim 4, wherein The second switch is coupled to the output end of the amplifier through a third resistor.
9. The detection device according to claim 3, characterized in that The phase-locked loop includes a phase-sensitive detector. The phase-sensitive detector has a first input end, a second input end, and an output end. Its first input end is coupled to the output end of the frequency-down converter for receiving the low-frequency signal. Its second input end receives a reference signal. The phase-sensitive detector is configured to multiply the low-frequency signal by the reference signal to obtain a phase-locked signal characterizing the phase difference information between the low-frequency signal and the reference signal.
10. The detection device according to claim 9, characterized in that, The filtering module is sequentially coupled to the second input end of the phase-sensitive detector through a phase adjustment module and a square wave conversion module to provide the reference signal.