Signal time parameter measuring device

Abstract

The utility model provides a signal time parameter measuring device which comprises at least one measuring link, and each measuring link comprises a channel fan-out unit, a signal preprocessing unit, a signal conversion unit, a control unit and a time digital conversion unit which are connected in sequence. The channel fan-out unit is used for fan-out of at least one sampling channel, each sampling channel is connected with one PIN of a tested device, and a tested signal is sampled by switching the sampling channels; the signal preprocessing unit is used for carrying out attenuation, gain and filtering processing on a measured signal; the signal conversion unit is used for carrying out hysteresis processing on the measured signal and converting the measured signal into a differential square wave signal; the control unit is used for calculating to obtain a low-precision measurement result of the time parameter; and the time-to-digital conversion unit is used for calculating to obtain a high-precision measurement result of the time parameter. According to the method and the device, the resolution and the precision of time parameter measurement are improved, and the problem that the design complexity of the DUT is increased due to measurement link switching at the DUT end in a high-integration-level test is solved.

Description

Technical Field

[0001] This application relates to the field of integrated circuit testing technology, and particularly relates to a signal time parameter measurement device. Background Art

[0002] In the field of Automatic Test Equipment (ATE) testing technology, testing the time parameters of the output signal of a Device Under Test (DUT) is an essential part. This part of the test often involves digital signals, analog signals, and mixed-signal signals.

[0003] As Figure 1 shown, currently, signal time parameter measurement usually uses a signal measurement device composed of multiple 1M ohm attenuation networks, 50 ohm attenuation networks, and high-input swing comparators (such as 16V high-speed PE comparators). When measuring the time parameters of the signal output by the DUT, the corresponding attenuation network is selected according to the signal characteristics and output to the high-speed PE comparator. The high-speed PE comparator outputs a square wave signal to the FPGA (Field Programmable Gate Array), and the FPGA realizes data encoding and time parameter calculation, and transmits the obtained measurement results to the host computer.

[0004] However, the above signal measurement device often has the following problems in actual testing:

[0005] The signal output by the DUT is transmitted to the time parameter test module through different modules. During the transmission process, affected by hardware traces and other interference sources, the signal is prone to signal hookback or glitches;

[0006] With the improvement of IC integration, more measurement modules are required to complete time parameter testing. The increase in modules requires more link switches, which places higher requirements on the DUT;

[0007] The measurement resolution of this signal measurement device depends on the highest rate of the FPGA, resulting in a loss of measurement accuracy. In addition, the signal swing input to the high-speed PE comparator depends on the pre-stage attenuation network, without considering the optimal input range of the high-speed PE comparator, resulting in certain errors in the test. Utility Model Content

[0008] In view of this, the main purpose of this application is to provide a signal time parameter measurement device, which improves the resolution and accuracy of time parameter measurement, and solves the problem of increasing the design complexity of the DUT caused by the measurement link switching at the DUT end in high-integration testing.

[0009] To achieve the above object, the present application provides a signal time parameter measurement device, including at least one measurement link, and the measurement link includes a channel fan-out unit, a signal preprocessing unit, a signal conversion unit, a control unit, and a time-to-digital conversion unit that are connected in sequence;

[0010] The channel fan-out unit fans out at least one sampling channel, and each sampling channel is connected to a PIN foot of the device under test, and the measured signals output by different PIN feet of the device under test are sampled by switching the sampling channels respectively;

[0011] The signal preprocessing unit is used to perform attenuation, gain, and filtering processing on the measured signal according to the preprocessing instruction;

[0012] The signal conversion unit is used to perform hysteresis processing on the measured signal and convert it into a differential square wave signal according to the comparison threshold;

[0013] In the low-precision mode, the control unit is used to sample the differential square wave signal and calculate the time parameter according to the configured trigger signal, so as to obtain a low-precision measurement result of the time parameter;

[0014] In the high-precision mode, the time-to-digital conversion unit is used to sample the differential square wave signal and calculate the time parameter according to the trigger signal configured by the control unit, so as to obtain a high-precision measurement result of the time parameter.

[0015] As described above, in the signal time parameter measurement device provided by the present application, at least one measurement link is included. The measurement link is provided with a channel fan-out unit including multiple sampling channels to be respectively connected to different PIN feet of the device under test, and according to the test requirements, the corresponding sampling channel is selected to sample the measured signal of the PIN foot it is connected to. After sampling, the measured signal can be attenuated, amplified, and filtered according to the amplitude requirements of the backend signal conversion unit, and the measured signal that meets the amplitude requirements is input into the signal conversion unit and converted into a differential square wave signal by means of hysteresis processing. For low-precision measurement requirements, the control unit can sample the differential square wave signal and calculate the time parameter to obtain a low-precision measurement result of the time parameter. For high-precision measurement requirements, the time-to-digital conversion unit can sample the differential square wave signal and calculate the time parameter to obtain a high-precision measurement result of the time parameter. Through the signal time parameter measurement device provided by the present application, the resolution and accuracy of time parameter measurement are improved, and at the same time, the problem of increasing the design complexity of the DUT caused by the measurement link switching at the DUT end in high-integration testing is solved.

[0016] Optionally, the channel fan-out unit includes at least one path of switch circuit connected in parallel. One end of the switch circuit is connected to a PIN pin of the device under test, and the other end is connected to the input end of the signal preprocessing unit.

[0017] As described above, by providing one or more paths of switch circuits in the channel fan-out unit, each path of switch circuit is respectively connected to a PIN pin of the device under test. When it is necessary to measure the signal time parameter of a certain PIN pin of the device under test, the switch circuit connected to the PIN pin can be controlled to be gated, so as to sample the measured signal output by the PIN pin and transmit it to the signal preprocessing unit.

[0018] Optionally, the signal preprocessing unit includes one path of preprocessing circuit, and the preprocessing circuit includes a capacitive-resistive attenuation circuit, a controllable gain circuit and a filter circuit connected in sequence.

[0019] As described above, by providing a preprocessing circuit composed of a capacitive-resistive attenuation circuit, a controllable gain circuit and a filter circuit, the input measured signal can be attenuated, amplified and filtered, so that the amplitude of the preprocessed measured signal meets the amplitude requirements of the backend signal conversion unit.

[0020] Optionally, the capacitive-resistive attenuation circuit includes at least one group of RC parallel circuits;

[0021] The DC measured signal is attenuated by a fixed ratio through the resistor of the RC parallel circuit, or the AC measured signal is attenuated by a fixed ratio through the resistor and capacitor of the RC parallel circuit.

[0022] As described above, by providing one or more groups of RC parallel circuits connected in series in sequence to perform fixed-ratio attenuation processing on the measured signal. Among them, when the measured signal is DC, it can be directly attenuated by a fixed ratio through the impedance of the resistor in the RC parallel circuit. When the measured signal is AC, it can be attenuated by a fixed ratio through the capacitor and resistor in the RC parallel circuit.

[0023] Optionally, the controllable gain circuit includes a voltage follower and a programmable amplifier connected in sequence. After being isolated and buffered by the voltage follower, the attenuated measured signal is amplified by the programmable amplifier according to the gain value;

[0024] The programmable amplifier is also connected to a gain voltage output circuit for providing the gain value for the programmable amplifier.

[0025] As described above, the measured signal after attenuation processing increases the driving ability through the voltage follower, and is transmitted to the programmable amplifier after front and rear stage isolation. The programmable amplifier amplifies the measured signal by a certain ratio according to the configured gain value.

[0026] Optionally, the filter circuit includes a low-pass filter of at least one frequency, and filters the measured signal after gain processing by adjusting the inductance value and capacitance value.

[0027] As described above, the filter circuit can be composed of low-pass filters of one or more frequencies. By adjusting the inductance value and capacitance value of the low-pass filter, it can filter noise signals of different frequencies to output a pure measured signal.

[0028] Optionally, the signal preprocessing unit further includes a switch circuit connected in parallel with the preprocessing circuit, which is used to select and connect the channel fan-out unit and the signal conversion unit.

[0029] As described above, the signal preprocessing unit is also provided with a switch circuit connected in parallel with the preprocessing circuit. When the amplitude of the measured signal meets the amplitude requirement of the backend signal conversion unit, there is no need to attenuate, gain, and filter the measured signal. The switch circuit can be directly selected and connected to directly transmit the measured signal sampled by the channel fan-out unit to the signal conversion unit.

[0030] Optionally, the signal conversion unit includes a hysteresis comparator. The hysteresis comparator configures a hysteresis value for the comparison threshold, and after performing hysteresis processing on the measured signal, converts it into a differential square wave signal.

[0031] As described above, due to the back-hook or low slew rate of the measured signal, it is easy to cause mis-sampling of the comparator. Therefore, by using a hysteresis comparator and setting a suitable hysteresis value for the comparison threshold, hysteresis processing is performed on the measured signal to avoid mis-sampling caused by the back-hook or low slew rate of the measured signal itself, and it is converted into a differential square wave signal for output.

[0032] Optionally, the control unit includes an FPGA controller. The FPGA controller configures trigger signals for the start and end of sampling, and samples the differential square wave signal and calculates time parameters according to the trigger signals to obtain a low-precision measurement result of the time parameters;

[0033] The FPGA controller is also used to control the selection of the sampling channels of the channel fan-out unit and configure the comparison threshold for the signal conversion unit.

[0034] As described above, the FPGA controller can control the channel fan-out unit and configure the comparison threshold for the signal conversion unit. It can also convert the differential square wave signal into a single-ended signal through internal conversion, and respectively set the start time and end time of sampling at a specific frequency clock. According to the clock count and clock frequency between the start time and end time, the time parameters of the measured signal are calculated to obtain a low-precision measurement result of the time parameters.

[0035] Optionally, it further includes a communication unit connected to the control unit for implementing communication between the host computer and the control unit.

[0036] As described above, by providing a communication unit between the host computer and the control unit, communication between the host computer and the control unit can be achieved.

[0037] These and other aspects of the present application will become more readily apparent in the following description of the (multiple) embodiments. Description of the Drawings

[0038] Figure 1 It is a module diagram of a signal measurement device provided by the prior art;

[0039] Figure 2 It is a module diagram of a signal time parameter measurement device provided by an embodiment of the present application;

[0040] Figure 3 It is a circuit diagram of a measurement link provided by an embodiment of the present application;

[0041] Figure 4 It is a circuit diagram of a resistor-capacitor attenuation circuit provided by an embodiment of the present application;

[0042] Figure 5 It is a circuit diagram of a filter circuit provided by an embodiment of the present application;

[0043] Figure 6 It is a schematic diagram of a differential square wave signal generated by false sampling caused by the back-hooking of the measured signal provided by an embodiment of the present application;

[0044] Figure 7 It is a schematic diagram of a differential square wave signal generated after hysteresis processing provided by an embodiment of the present application. Detailed Embodiments

[0045] In order to make the objectives, technical solutions, and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings.

[0046] An embodiment of the present application provides a signal time parameter measurement device, which avoids false sampling caused by the back-hooking and glitches of the measured signal, ensures that the signal amplitude meets the processing amplitude of the high-speed hysteresis comparator, removes signal interference, improves the resolution and accuracy of time parameter measurement, and solves the problem of increased DUT design complexity caused by the switching of the measurement link at the DUT end in high-integration testing.

[0047] Such as Figure 2As shown in the figure, an embodiment of the present application provides a signal time parameter measurement device, which may include multiple measurement links, such as 16 measurement links. Each measurement link includes a channel fan-out unit 101, a signal preprocessing unit 201, a signal conversion unit 301, a control unit 401, and a time-to-digital conversion unit 501 connected in sequence.

[0048] Among them, the channel fan-out unit 101 can fan out multiple sampling channels, and each sampling channel is connected to a PIN foot of the device under test. By switching the sampling channels, the measured signals output from different PIN feet of the device under test are sampled respectively. In this embodiment, the sampling channels can be implemented in the form of a switching circuit or in the form of chip selection, without specific limitation; when the amplitude of the measured signal sampled by the channel fan-out unit 101 meets the amplitude requirement of the signal conversion unit 301 at the back end, the signal preprocessing unit 201 can directly transmit the measured signal to the signal conversion unit 301, or according to the preprocessing instruction, perform preprocessing such as attenuation, gain, and filtering on the measured signal that does not meet the amplitude requirement and then transmit it to the signal conversion unit 301; the signal conversion unit 301 is used to perform hysteresis processing on the measured signal according to the comparison threshold and convert it into a differential square wave signal; in the low-precision mode, the control unit 401 is used to sample the differential square wave signal and calculate the time parameter according to the configured trigger signal to obtain a low-precision measurement result of the time parameter; in the high-precision mode, the time-to-digital conversion unit 501 is used to sample the differential square wave signal and calculate the time parameter according to the trigger signal configured by the control unit 401 to obtain a high-precision measurement result of the time parameter.

[0049] In some embodiments, the above preprocessing instruction can be generated and sent by the control unit 401, and the preprocessing instruction can be implemented in the form of high and low levels. For example, when the amplitude of the measured signal sampled by the channel fan-out unit 101 meets the amplitude requirement of the signal conversion unit 301 at the back end, the control unit 401 can send a low-level preprocessing instruction, and there is no need to preprocess the measured signal and directly transmit the measured signal to the signal conversion unit 301; when the amplitude of the measured signal sampled by the channel fan-out unit 101 does not meet the amplitude requirement of the signal conversion unit 301 at the back end, the control unit 401 can send a high-level preprocessing instruction, and at this time, the preprocessing unit 201 performs preprocessing such as attenuation, gain, and filtering on the measured signal that does not meet the amplitude requirement and then transmits it to the signal conversion unit 301.

[0050] In some embodiments, it may further include a communication unit 601 connected to the control unit 401 and the host computer 701. The communication unit 601 can implement communication between the control unit 401 and the host computer 701 through a PCIE channel.

[0051] In some embodiments, the above-mentioned signal conversion unit 301 has two input ports and can convert two measured signals. Therefore, to save circuit costs, in multiple measurement links, the number of signal conversion units can be set to half of the number of measurement links, which can meet the conversion of multiple measured signals.

[0052] In some embodiments, the above-mentioned control unit has multiple input ports and can process multiple differential square-wave signals simultaneously. For example, the control unit can sample 8 differential square-wave signals according to a trigger signal and perform time parameter calculation, or send the 8 differential square-wave signals to 8 subsequent time-to-digital conversion units respectively for high-precision time parameter measurement. Therefore, when arranging the circuit, the number of control units can be set to 1 / 8 of the number of measurement links, which can meet the measurement or transmission of multiple differential square-wave signals.

[0053] The following refers to Figure 3 the circuit diagram of a measurement link shown in the figure, and details any one of the measurement links in the signal time parameter measurement device according to the embodiments of the present application. As Figure 3 shown, this measurement link includes a channel fan-out unit, a signal preprocessing unit, a signal conversion unit, a control unit, and a time-to-digital conversion unit connected in sequence.

[0054] Among them, the channel fan-out unit may include four-way switch circuits S1 - S4, which can connect different PIN feet of the device under test according to different test requirements of the device under test. For example, switch S1 can be connected to PIN1 of the device under test, and switch S2 can be connected to PIN2 of the device under test. According to the measurement requirements, switch S1 is closed to transmit the measured signal output from PIN1 of the device under test to the subsequent signal processing unit for subsequent time parameter measurement. After the time parameter measurement of the measured signal output from PIN1 is completed, the time parameter measurement of the measured signal output from PIN2 can be performed by the operation of disconnecting switch S1 and closing switch S2. Through the four-way switch circuits S1 - S4, the switching measurement of the signal time parameters of up to 4 PIN feet of the device under test can be realized.

[0055] The signal preprocessing unit includes a preprocessing circuit and a switching circuit connected in parallel. At both ends of the preprocessing circuit, switches S5 and S7 are respectively provided, and at both ends of the switching circuit, switches S6 and S8 are respectively provided. For the amplitude of the input measured signal, by switching switches S5, S7 or switches S6, S8, preprocessing or direct transmission of the measured signal can be achieved. For example, if the amplitude of the measured signal meets the amplitude requirement (VPP) of the signal conversion unit at the back end and meets factors such as signal purity, etc., then there is no need to preprocess the measured signal. By opening switches S5 and S7 and closing switch S6 and S8, the measured signal can be directly transmitted to the signal conversion unit at the back end. If the measured signal is a time parameter signal that does not meet the amplitude requirement (VPP) of the signal conversion unit and needs to be preprocessed, then by opening switches S6 and S8 and closing switches S5 and S7, the measured signal is input into the preprocessing circuit for attenuation, gain, and filtering processing. Specifically, the preprocessing circuit includes a resistor-capacitor attenuation circuit, a signal amplification circuit, a filtering circuit, and a gain voltage output circuit connected to the signal amplification circuit. The resistor-capacitor attenuation circuit includes at least one group of RC parallel circuits, which can achieve attenuation of the measured signal by a fixed ratio k. Among them, the DC measured signal can be attenuated through resistor R1, and the AC measured signal is attenuated through resistor R1 and capacitor C1. Among them, the Figure 3 resistor R1 and capacitor C1 in it are schematic diagrams of the combination of several fixed resistors and capacitors, and the structure of the resistor-capacitor attenuation circuit can also be realized by the parallel connection of multiple resistors and multiple capacitors. The signal amplification circuit includes a voltage follower Buff and a programmable gain amplifier VGA. The measured signal attenuated by the resistor-capacitor attenuation circuit increases the driving ability of the signal through the voltage follower Buff and isolates the front and back stages of the signal to ensure that the time characteristics of the measured signal do not change when transmitted to the subsequent stage. The isolated measured signal can be amplified by a certain ratio through the programmable gain amplifier VGA to meet the amplitude requirement (VPP) of the signal conversion unit at the back end. The amplification factor of the programmable gain amplifier VGA is Gain = VPP / (VPP - I / k), where the gain value Gain is determined by the gain voltage Vgain of the gain voltage output circuit. The gain voltage output circuit includes a digital-to-analog converter DAC and an operational amplifier OPA. By adjusting the output value of the digital-to-analog converter DAC and outputting a specified gain voltage Vgain through the operational amplifier OPA, the programmable gain amplifier VGA is controlled to amplify the measured signal.

[0056] The filter circuit includes a low-pass filter of at least one frequency. The low-pass filter is specifically composed of an inductor L1 connected in series and capacitors C2 and C3 connected to both ends of the inductor L1. By adjusting the inductance value and capacitance value of the low-pass filter, the interference frequency signal contained in the amplified measured signal is filtered out.

[0057] The signal conversion unit includes a high-speed hysteresis comparator. By setting appropriate hysteresis values for the comparison thresholds, the high-speed hysteresis comparator performs hysteresis processing on the signal under test to avoid false sampling caused by the signal under test itself hooking back or having a low slew rate. By configuring two different comparison thresholds for the high-speed hysteresis comparator and setting appropriate hysteresis values for the comparison thresholds, the signal under test input to the high-speed hysteresis comparator can be decomposed and converted into two pairs of differential square-wave signals for output. For example, as Figure 6 shown, let the comparison thresholds sampled by the comparator be CVH and CVL respectively. The signal under test is sampled according to the comparison thresholds CVH and CVL. When the signal under test triggers the comparison threshold CVL, differential square-wave signals QL_P and QL_N will be generated. When the signal under test triggers the comparison threshold CVH, differential square-wave signals QH_P and QH_N will be generated. According to Figure 6 shown, when the signal under test gradually increases and it is assumed that a hook-back occurs near the comparison threshold CVH, this will cause false sampling of the comparator and generate inaccurate differential square-wave signals QH_P and QH_N. Based on this, by setting appropriate hysteresis values for the comparison thresholds, hysteresis processing can be performed on the signal under test to avoid false sampling caused by the signal under test itself hooking back or having a low slew rate. For example, according to the hook-back amplitude of the signal under test, an appropriate hysteresis value Det_V is set for the comparison threshold CVH, so that the comparison threshold CVH becomes CVH + Det_V. Therefore, when the signal under test hooks back near the comparison threshold CVH, due to the set hysteresis value Det_V, false sampling of the comparator will not occur, and accurate differential square-wave signals QH_P and QH_N can be generated.

[0058] The control unit includes an FPGA controller. The FPGA controller can achieve the control of the channel fan-out unit and configure the comparison thresholds for the signal conversion unit. It can also, in the low-precision mode, convert the differential square-wave signals into single-ended signals through internal conversion, and at a clock of a specific frequency, respectively configure the start time and end time of sampling. According to the clock count and clock frequency between the start time and the end time, the time parameters of the signal under test are calculated to obtain the low-precision measurement result of the time parameters of the signal under test. For example, at a clock of a specific frequency, the rising edge / falling edge of QH is sampled as the start time of timing, and the falling / rising time of QL is sampled as the end time. The reciprocal of the product of the clock count between the two times and the clock frequency is the measurement time.

[0059] The time digital conversion unit includes a Time-to-Digital Converter (TDC). Through this TDC chip, a continuous time signal can be converted into a digital signal, thereby realizing the digitization of time measurement. In the high-precision mode, this TDC chip can sample and calculate and analyze the time parameters of the differential square wave signal according to the starting and ending moments of sampling configured by the FPGA controller, so as to obtain a high-precision measurement result of the time parameters of the measured signal. Among them, the measurement resolution of the time parameters can reach the ps level, featuring high precision and high resolution.

[0060] In some embodiments, as Figure 4 shown, the resistor-capacitor attenuation circuit may include multiple groups of RC parallel circuits connected in series to the ground in sequence. Specifically, this resistor-capacitor attenuation circuit includes resistors R1 - R8 and capacitors C1 - C7, where resistors R1 - R7 are connected in series and grounded in sequence, resistors R2 - R7 are respectively connected in parallel with capacitors C1 - C6, one end of resistor R1 serves as the input end of the measured signal, the series connection point of resistors R6 and R7 serves as the output end of the attenuated measured signal, the other end of resistor R7 is grounded, and resistor R8 and capacitor C7 are connected in series to form a resonant circuit, which is connected between the output end of the measured signal and the ground to cooperate with the resonant output of the AC signal. When the measured signal is DC, a fixed ratio of attenuation of this DC measured signal can be achieved through the impedance of resistors R1 - R7. When the measured signal is AC, capacitors C1 - C6 cooperate with resistors R1 - R7 to achieve a fixed ratio of attenuation of this AC measured signal.

[0061] In some embodiments, as Figure 5 shown, the filter circuit may include low-pass filters with three frequencies, whose cut-off frequencies are f1, f2, and f3 respectively. Exemplarily, these three-frequency low-pass filters can be implemented by three-frequency π-type low-pass filters. These three-frequency π-type low-pass filters can be respectively controlled for gating through switches S1, S2, switches S3, S4, and switches S5, S6. For example, when the two frequencies contained in the measured signal are fa, fb (fa > f1 > fb), and the signal with frequency fb is the signal that actually needs to be measured. To ensure that the signal is correctly sampled, switches S1 and S2 can be closed, and the π-type low-pass filter link with a cut-off frequency of f1 can be opened to filter out the signal with frequency fa in the measured signal. At this time, the signal output at the Vout terminal only has the signal with frequency fb. The application principles of the other two-frequency π-type low-pass filters are similar and will not be elaborated here.

[0062] In summary, a signal time parameter measurement device provided by an embodiment of the present application can support multiple measurement links, and each measurement link can fan out multiple sampling channels, changing the signal link switching from the DUT end to this measurement device, greatly releasing the space of the DUT board to achieve the layout of more functional tests. The controllability of the signal attenuation ratio can be supported through the resistor-capacitor attenuation circuit and the controllable gain circuit, ensuring that the signal amplitude input to the subsequent stage is completely within the best linearity required by the comparator, reducing signal sampling errors. Different frequency filters can also be selected through the controllable filter circuit to filter out abnormal glitches and pulses, ensuring the normal sampling of the desired signal. In addition, the hysteresis function of the high-speed hysteresis comparator circuit can effectively avoid mis-sampling of the comparator caused by back-hooking introduced under low slew rate or PCB traces. The control unit samples the differential square wave signal and calculates the time parameters to obtain a low-precision measurement result of the time parameters, and the time-to-digital conversion unit samples the differential square wave signal and calculates the time parameters to obtain a high-precision measurement result of the time parameters. Based on this, the signal time parameter measurement device provided by the embodiment of the present application improves the resolution and accuracy of time parameter measurement, and solves the problem of increased DUT design complexity caused by measurement link switching at the DUT end in high-integration tests.

[0063] It should be noted that the embodiments described in the present application are only a part of the embodiments of the present application, rather than all embodiments. The components of the embodiments of the present application described and illustrated in the drawings can be arranged and designed in various different configurations. Therefore, the detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the present application to be protected, but only represents the selected embodiments of the present application. All other embodiments obtained by those skilled in the art based on the embodiments of the present application without creative efforts belong to the scope of protection of the present application.

[0064] Terms such as "first", "second", "third", etc. in the description and claims are only used to distinguish similar objects and do not represent a specific order for the objects. It can be understood that, where permitted, the specific order or sequence can be interchanged so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0065] In the above description, the reference numerals representing steps do not necessarily mean that the steps will be executed in this order. It may also include intermediate steps or be replaced by other steps. Where permitted, the order of the front and rear steps can be interchanged, or they can be executed simultaneously.

[0066] The term "comprising" as used in the description and claims should not be construed as limited to the content listed thereafter; it does not exclude other elements or steps. Thus, it should be interpreted as specifying the presence of the recited features, integers, steps or components, but not excluding the presence or addition of one or more other features, integers, steps or components and groups thereof. Accordingly, the expression "a device comprising devices A and B" should not be limited to a device consisting only of components A and B.

[0067] As used herein, the term "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present application. Thus, the phrases "in one embodiment" or "in an embodiment" that appear throughout this specification do not necessarily all refer to the same embodiment, but may. Furthermore, in the various embodiments of the present application, if there is no special indication and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be cross-referenced to each other, and the technical features in different embodiments can be combined to form new embodiments according to their inherent logical relationships.

[0068] Note that the above are only the preferred embodiments of the present application and the technical principles applied. Those skilled in the art will understand that the present application is not limited to the specific embodiments described herein, and various obvious changes, re-adjustments and substitutions can be made by those skilled in the art without departing from the protection scope of the present application. Therefore, although the present application has been described in detail through the above embodiments, the present application is not limited to the above embodiments, and without departing from the concept of the present application, more other equivalent embodiments can be included, all of which fall within the protection scope of the present application.

Claims

1. A signal time parameter measuring device, characterized in that, Comprising at least one measurement link, the measurement link including a channel fan-out unit, a signal preprocessing unit, a signal conversion unit, a control unit, and a time-to-digital conversion unit connected in sequence; The channel fan-out unit fans out at least one sampling channel, and each sampling channel is connected to a PIN foot of the device under test, for sampling the measured signals output from different PIN feet of the device under test by switching the sampling channels; The signal preprocessing unit includes a preprocessing circuit, the preprocessing circuit is connected to the channel fan-out unit, and the preprocessing circuit includes a resistor-capacitor attenuation circuit, a controllable gain circuit, and a filter circuit connected in sequence, for attenuating, amplifying, and filtering the measured signal according to the preprocessing instruction; The signal conversion unit includes a hysteresis comparator, the hysteresis comparator is connected to the filter circuit, and the hysteresis comparator is used for performing hysteresis processing on the measured signal by configuring a hysteresis value for the comparison threshold, and then converting it into a differential square wave signal; The control unit includes an FPGA controller, the FPGA controller is connected to the hysteresis comparator, and the FPGA controller is used for converting the differential square wave signal into a single-ended signal through internal conversion, and configuring the start time and end time of sampling respectively under a clock of a specific frequency, and calculating the time parameter of the measured signal according to the clock count and clock frequency between the start time and the end time, to obtain a low-precision measurement result of the time parameter of the measured signal; The time-to-digital conversion unit includes a TDC chip, the TDC chip is connected to the FPGA controller, and the TDC chip is used for sampling and calculating the time parameter of the differential square wave signal according to the start time and end time of sampling configured by the FPGA controller, so as to obtain a high-precision measurement result of the time parameter of the measured signal.

2. The device according to claim 1, characterized in that The channel fan-out unit includes at least one switch circuit connected in parallel, one end of the switch circuit is connected to a PIN foot of the device under test, and the other end is connected to the input end of the signal preprocessing unit.

3. The device according to claim 1, characterized in that, The resistor-capacitor attenuation circuit includes at least one group of RC parallel circuits; The DC measured signal is attenuated in a fixed ratio through the resistor of the RC parallel circuit, or the AC measured signal is attenuated in a fixed ratio through the resistor and capacitor of the RC parallel circuit.

4. The device according to claim 1, characterized in that The controllable gain circuit includes a voltage follower and a programmable amplifier connected in sequence. After the attenuated measured signal is isolated and buffered by the voltage follower, it is amplified by the programmable amplifier according to the gain value; The programmable amplifier is also connected to a gain voltage output circuit for providing the gain value for the programmable amplifier.

5. The device according to claim 1, characterized in that, The filter circuit includes a low-pass filter of at least one frequency, and filters the measured signal after gain processing by adjusting the inductance value and capacitance value.

6. The device according to claim 1, wherein The signal preprocessing unit further includes a switch circuit connected in parallel with the preprocessing circuit, for selecting and connecting the channel fan-out unit and the signal conversion unit.

7. The device according to claim 1, wherein, It further includes a communication unit connected to the control unit, for realizing communication between the host computer and the control unit.

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