Semiconductor device

Abstract

A semiconductor device having a dummy region is provided herein, and the dummy region has dummy fill structures of different lateral dimensions. A semiconductor device may include a through silicon via extending through a substrate of the semiconductor device; the active device is positioned in or on the substrate; and a dummy region of the substrate separating the through silicon via and the active region, the dummy region including a plurality of dummy filling structures, the dummy filling structures having lateral dimensions in a first direction from the through silicon via to the active region, and the lateral dimensions of the dummy filling structures in the first direction being different.

Description

Technical Field

[0001] Embodiments of the present utility model relate to dummy regions near through-silicon via regions, and more particularly to the configuration of dummy fill structures in the dummy regions. Background Art

[0002] The semiconductor integrated circuit industry has continued to grow rapidly in recent years. Technological advancements in integrated circuit materials and design have enabled continuous improvement of each generation of integrated circuits. Each generation of integrated circuits has smaller and more complex circuits than the previous generation, resulting in higher functional density (i.e., the number of interconnect devices per unit chip area) and smaller geometric dimensions (i.e., the smallest components or lines that can be produced using the manufacturing process). The shrinking process is also beneficial for increasing production capacity and reducing related costs. However, as the structure size continues to shrink, the manufacturing process becomes increasingly challenging, and it is increasingly difficult to ensure the reliability of semiconductor devices. As a result, the industry faces challenges in process development when producing smaller and more reliable integrated circuits. Summary of the Invention

[0003] In one embodiment, a semiconductor device is provided, which includes a through-silicon via extending through a substrate of the semiconductor device; active devices located within or on the substrate; and a dummy region of the substrate separating the through-silicon via from the active devices, the dummy region including a plurality of dummy fill structures, wherein the dummy fill structures have a lateral dimension in a first direction from the through-silicon via to the active devices, and wherein the lateral dimension of a first dummy fill structure in the dummy region is different from the lateral dimension of a second dummy fill structure.

[0004] In one embodiment, the lateral dimensions of the dummy fill structures define a gradient lateral dimension between the through-silicon via and the active devices, which decreases from a maximum lateral dimension to a minimum lateral dimension in the first direction, wherein the maximum lateral dimension is 50 nm to 200 nm, and the minimum lateral dimension is less than or equal to 50 nm.

[0005] In one embodiment, the gradient lateral dimension is in a stepped form.

[0006] In one embodiment, the maximum lateral dimension is 100 nm to 150 nm, and the minimum lateral dimension is 6 nm to 75 nm.

[0007] In one embodiment, the gradient lateral dimension is defined by at least two consecutive portions of the dummy region, a first one of the consecutive portions including a first group of dummy fill structures having a maximum lateral dimension, and a second one of the consecutive portions including a second group of dummy fill structures having a minimum lateral dimension.

[0008] In one embodiment, the maximum lateral dimension is 100 nm to 150 nm, and the minimum lateral dimension is 6 nm to 75 nm.

[0009] In one embodiment, a stress relief structure is further included in the substrate to surround the through-silicon via.

[0010] In one embodiment, the stress relief structure has a second lateral dimension in the first direction, and the second lateral dimension is greater than the lateral dimension of the dummy fill structures.

[0011] In one embodiment, the lateral dimension of the dummy region in the first direction is less than or equal to 100 micrometers.

[0012] In one embodiment, the lateral dimension of the dummy region in the first direction is less than or equal to 50 micrometers. Description of the Drawings

[0013] Figure 1 is a cross-sectional view of a part of a semiconductor device in a stage of an integrated circuit manufacturing process in some embodiments.

[0014] Figure 2 is a top view of a part of a semiconductor device in some embodiments, which includes a through-silicon via region, an active device region, and a dummy region between the two.

[0015] Figure 3 is a cross-sectional view of a part of a semiconductor device in some embodiments, which includes a through-silicon via region, an active device region, and a dummy region between the two.

[0016] Figure 4 is in some embodiments Figure 3 of a cross-sectional view of a part of a semiconductor device, which shows a chemical mechanical polishing step of the semiconductor device.

[0017] Figure 5 is a flowchart of an exemplary method for forming a semiconductor device in some embodiments.

[0018] Figure 6 is a table of atomic force measurement data obtained from multiple sample semiconductor devices during experimental research in one embodiment.

[0019] Description of the Reference Numerals:

[0020] 100: Semiconductor device

[0021] 101, 201: Through-silicon via region

[0022] 102: First external device

[0023] 103, 203: Dummy region

[0024] 103A: First part

[0025] 103B: Second part

[0026] 104: Second external device

[0027] 105, 205: Functional region

[0028] 107: Direction

[0029] 110, 210: Substrate

[0030] 112: Metallization layer

[0031] 114: First passivation layer

[0032] 116: Through-silicon via

[0033] 118, 218: Active device

[0034] 120: Contact pad

[0035] 122: Redistribution layer

[0036] 124: Second passivation layer

[0037] 126: Conductive bump

[0038] 130, 230: Non-structured region

[0039] 132, 232: Stress relief structure

[0040] 136, 138, 236, 238, 240: Void fill structure

[0041] 200: Portion

[0042] 201A: Non-structured portion

[0043] 201B: Stress relief region

[0044] 234: Structure

[0045] 242: Outermost layer

[0046] 250: Oval

[0047] 300: Method

[0048] 310, 312, 314, 316, 318, 320: Steps Detailed description

[0049] The following detailed description may be accompanied by the accompanying drawings to facilitate understanding of various aspects of the present utility model. It should be noted that the various structures are only for illustrative purposes and are not drawn to scale, as is normal in the industry. In fact, for clarity of illustration, the sizes of various structures can be increased or decreased arbitrarily.

[0050] The different embodiments or examples provided below can implement different structures of the present utility model. The embodiments of the specific components and arrangements below are used to simplify the content of the present utility model rather than limit the present utility model. For example, the description of forming the first component on the second component includes embodiments where the two are in direct contact, or embodiments where there are other additional components between the two and they are not in direct contact. In addition, multiple examples of the present utility model may reuse the same reference numerals for simplicity, but the elements with the same reference numerals in multiple embodiments and / or arrangements do not necessarily have the same corresponding relationships.

[0051] Terms such as "first", "second", and "third" used herein describe various units, components, regions, layers, and / or parts, but these units, components, regions, layers, and / or parts are not limited by these terms. These terms are only used to distinguish one unit, component, region, layer, or part from another unit, component, region, layer, or part. The "first", "second", and "third" used herein do not imply an order, unless clearly stated in the content.

[0052] For the sake of simplicity, the related prior art of manufacturing existing semiconductor devices is not described in detail herein. In addition, the various operations and processes described herein can be incorporated into a more comprehensive process or process with additional functions not described herein in detail. Specifically, various processes for fabricating semiconductor devices are common. Therefore, for the sake of simplicity, many existing processes are only briefly mentioned or completely omitted herein, without providing common process details. Those skilled in the art in this technical field should understand, after reading this disclosure in its entirety, that the structures disclosed herein can be used with various technologies and can be incorporated into various semiconductor devices and products. In addition, it should be noted that the semiconductor device structure may include a varying number of components, and a single component shown in the drawings may represent multiple components.

[0053] In addition, spatial relative terms such as "below", "beneath", "lower", "above", "upper", or similar terms can be used to simplify the relative relationship between one element and another element in the drawings. The spatial relative terms can extend to elements used in other directions and are not limited to the directions shown in the drawings. The elements can also be rotated 90 degrees or other angles, so the directional terms are only used to illustrate the directions in the drawings. When the above spatial relative terms are used to describe the first unit relative to the second unit, the first unit can be directly located on top of the other unit, or there can be intermediate units or layers. When a unit or layer is considered to be on top of another unit or layer, it can be directly located on top of the other unit or layer and in contact with the other unit or layer.

[0054] It should be noted that the embodiments described by terms such as "an embodiment", "an exemplary embodiment", "exemplary", or similar terms of the following content may include specific features, structures, or characteristics, but each embodiment does not necessarily include the specific features, structures, or characteristics. In addition, these terms do not necessarily refer to the same embodiment. In addition, when describing specific features, structures, or characteristics in combination with an embodiment, those skilled in the art can implement these features, structures, or characteristics in combination with other embodiments whether explicitly stated or not.

[0055] Some embodiments of the present invention will be described with reference to the accompanying drawings, where the same reference numerals are generally used to denote the same units. In the following content, many specific details are described to facilitate the understanding of the subject matter protected by the claims. However, the subject matter of the claims can be clearly implemented without these specific details. In other examples, the structures and devices are shown in block diagrams to facilitate the description of the subject matter of the claims.

[0056] Additional steps may be provided before, during, and / or after the stage described in the embodiment. Different embodiments may replace or omit some of the described stages. Additional structures may be added to the semiconductor device structure. Different embodiments may replace or omit some of the following structures. Although the steps described in a specific order illustrate some embodiments, these steps may be performed in another logical order.

[0057] As used herein, a "layer" is a region, such as a region including any boundary, and does not necessarily include a uniform thickness. For example, a layer may include at least some regions with thickness variations.

[0058] Generally, through-silicon vias can be formed in a semiconductor substrate to provide electrical connection to the back side of the semiconductor substrate. By providing this electrical connection, the possibility of connecting the semiconductor substrate can be extended beyond the electrical connections that were only located on one side of the semiconductor substrate in previous generations of semiconductor processes. This extension can be used for three-dimensional stacking of semiconductor dies and provide power lines, ground lines, and signal lines in the entire three-dimensional stack through the connection of through-silicon vias.

[0059] To form a through-silicon via, an opening can be formed on the active side of the semiconductor substrate, where the opening extends deeper into the semiconductor substrate than the active devices located within or on the semiconductor substrate. Then, a conductive material can be filled into the opening. After filling the opening, the back side of the semiconductor substrate can be thinned via a chemical mechanical polishing or etching process to expose the conductive material, thereby leaving a flat surface between the conductive material and the surrounding materials. Then, a conductive adhesive layer can be formed on the flat surface to provide an interface between the through-silicon via and the subsequently formed contact.

[0060] Larger unstructured regions (such as polysilicon blank regions) typically surround the through-silicon vias, and the unstructured regions are composed of non-conductive materials. During the chemical mechanical polishing step related to forming the through-silicon vias, over-thinning (i.e., dishing) may occur. Therefore, sufficient distance must usually be provided between the through-silicon vias and any adjacent active devices to reduce negative impacts such as dishing on the active region, such as a reduction in gate height.

[0061] The embodiments described herein are semiconductor structures and methods of forming the same having dummy regions such as non-functional regions located between the through-silicon vias and adjacent active devices. The dummy regions include dummy fill structures (such as non-functional structures) that are arranged to reduce dishing during planarization, shrinking the dummy regions and improving topography control. For ease of explanation, the semiconductor structures and methods described herein are illustrated with the planarization step of forming the through-silicon vias. However, the semiconductor structures and methods are not limited to this aspect and / or stage of the integrated circuit manufacturing process.

[0062] The dummy regions provide isolation and reduce electrical interference or crosstalk between the through-silicon vias and adjacent circuits or active regions. The dummy regions may include non-conductive materials such as silicon oxide, which can act as an insulating layer. The dummy regions may also include additional layers or structures that can enhance electrical isolation, reduce noise, or provide mechanical stability. In addition, the dummy regions can be arranged to provide sufficient space between the through-silicon vias and nearby active devices such that the step of planarizing the through-silicon via region does not substantially impact the active devices (such as significantly reducing the gate height).

[0063] In various embodiments, the material of the dummy fill structure of the dummy region thins only slightly or not at all relative to the surrounding insulating material (such as non-conductive material, such as silicon oxide) during the planarization step. For example, the etchant used to planarize the through-silicon via region does not etch the material of the dummy fill structure (such as a metal material). The dummy fill structures can include the same or different materials. In the examples described herein, the dummy regions include patterns of dummy fill structures that are configured such that the lateral dimensions of the dummy fill structures in the dummy regions between the through-silicon via region and the active devices vary or are different. In some embodiments, the lateral dimensions of the dummy fill structures define a gradient lateral dimension that decreases from a maximum lateral dimension to a minimum lateral dimension in the direction from the through-silicon via towards the active device.

[0064] Figure 1In one embodiment, it is a cross-sectional view of a part of a semiconductor device 100 at a stage in an integrated circuit manufacturing process. The drawing is only a part of the semiconductor device 100, which has electrical circuits formed in and / or on a substrate 110. The substrate 110 can be one of various semiconductor substrates commonly used in semiconductor integrated circuit fabrication, and the integrated circuit can be formed in and / or on the semiconductor substrate. The substrate 110 can be or include a semiconductor material, such as but not limited to bulk silicon, a semiconductor wafer, a silicon-on-insulator substrate, or a silicon-germanium substrate. Other semiconductor materials such as Group III, Group IV, and / or Group V semiconductor materials can also be used.

[0065] The semiconductor device 100 includes one or more metallization layers 112 on a first side of the substrate 110, one or more first passivation layers 114 on a second side of the substrate 110, through-silicon vias 116 formed in the substrate 110 and extending through the substrate 110, at least one active device 118 formed in or on the substrate 110, contact pads 120 and a redistribution layer 122 formed on the passivation layer 114 and electrically contacting the through-silicon vias 116, and one or more second passivation layers 124 formed on the contact pads 120 and the redistribution layer 122. Conductive bumps 126 connect the semiconductor device 100 to a first external device 102 on its first side and connect the semiconductor device 100 to a second external device 104 on its second side. An inactive region 103 is located between a first one of the through-silicon vias 116 and the active device 118.

[0066] In some embodiments, the substrate 110 can include multiple functional regions. Isolation structures such as shallow trench isolation structures or local oxidation of silicon structures can define the multiple functional regions and electrically isolate the functional regions from each other, but the present invention is not limited thereto. Various electronic components can be formed on the substrate 110 in the functional regions. Examples of electrical components include active regions (such as the active device 118, such as a transistor or a diode), and passive devices (such as a capacitor, an inductor, or a resistor). As Figure 1In some of the illustrated embodiments, active devices (i.e., transistors) may be formed on substrate 110. Functional regions separated by isolation structures may include electronic units formed in and / or on substrate 110. The types of microelectronic units that may be formed in substrate 110 may include, but are not limited to, metal oxide semiconductor field effect transistors, complementary metal oxide semiconductor transistors, bipolar junction transistors, high voltage transistors, high frequency transistors, p-type and / or n-type channel field effect transistors, resistors, diodes, capacitors, inductors, fuses, and / or other suitable units. A variety of processes may be performed to form the various microelectronic units, including but not limited to one or more depositions, etches, implants, lithographies, anneals, and other suitable processes. The microelectronic units are interconnected to form an integrated circuit device, which may include one or more logic devices such as memory devices (e.g., static random access memory), radio frequency devices, input / output devices, system-on-chip devices, or other suitable types of devices.

[0067] Figure 2 is a top view of a portion of the first side of semiconductor device 100 in some embodiments, which includes through-silicon via region 101, functional region 105, and dummy region 103 between through-silicon via region 101 and functional region 105. In this example, through-silicon via region 101 includes through-silicon via 116 surrounded by unstructured region 130 (such as a polysilicon blank area), and a barrier (such as a through-silicon via growth layer) further surrounds unstructured region 130, and the barrier includes stress relief structure 132 to release the stress caused by the formation and presence of through-silicon via 116. In some embodiments, stress relief structure 132 may include a metallic material, such as but not limited to copper or its alloys. Functional region 105 includes active device 118.

[0068] Dummy region 103 includes dummy fill (i.e., non-functional) structures 136 and 138, the constituent materials of which may resist the removal process during planarization of through-silicon via region 101, and thus react little or not at all with the etchant used during planarization. The above-mentioned etchant is configured to etch polysilicon or other surrounding materials (such as non-conductive materials, such as silicon oxide). In some embodiments, the constituents of dummy fill structures 136 and 138 may be metallic materials, such as but not limited to copper or its alloys. The dummy fill structures 136 and 138 in dummy region 103 may define a pattern, wherein the lateral dimensions of dummy fill structures 136 and 138 vary (e.g., are different from each other) between through-silicon via region 101 and functional region 105. In some examples, the lateral dimensions of dummy fill structures 136 and 138 may be less than or equal to about 200 nm. In some embodiments, the lateral dimensions of dummy fill structures 136 and 138 are in the direction from through-silicon via region 101 towards functional region 105 (such as Figure 2In the direction 107), it can be reduced from the maximum lateral dimension to the minimum lateral dimension. For example, the lateral dimensions of the dummy fill structures 136 and 138 can be reduced from about 200 nm to 6 nm, such as from about 135 nm to about 6 nm, such as from about 54 nm to about 6 nm. In some embodiments, the lateral dimensions of the dummy fill structures 136 and 138 can be reduced in a stepped manner, such as from 200 nm to 135 nm and then to 54 nm, such as from 135 nm to 54 nm and then to 6 nm, or a similar manner. For example, Figure 2 the dummy region 103 in is divided into a first part 103A and a second part 103B. In this example, the dummy fill structure 136 of the first part 103A can have a first lateral dimension (such as 135 nm) or a first lateral dimension range (such as 100 nm to 150 nm), and the dummy fill structure 138 of the second part 103B can have a second lateral dimension (such as 54 nm) or a second lateral dimension range (such as 6 nm to 75 nm), and the second lateral dimension and / or the second lateral dimension range is less than the first lateral dimension and / or the first lateral dimension range. Although Figure 2 the part of the semiconductor device 100 shown only includes two dummy fill structures 136 and two dummy fill structures 138, it should be understood that the dummy region can contain fewer or more dummy fill structures 136 and dummy fill structures 138, and / or include any number of additional dummy fill structures (with other lateral dimensions).

[0069] such as Figure 3 A cross-sectional view of a part 200 of a substrate 210 of another exemplary semiconductor device as shown, which has one or more outermost layers 242 (such as a dielectric layer, such as polysilicon). In some embodiments, the part 200 includes a through-silicon via region 201, a functional region 205, and a dummy region 203 between the through-silicon via region 201 and the functional region 205. The through-silicon via region 201 is divided into an unstructured part 201A containing through-silicon vias (not shown or not yet formed), and a stress release region 201B. The unstructured part 201A includes an unstructured region 230 (such as a polysilicon blank region), and the stress release region 201B includes a stress release structure 232. The functional region 205 includes active devices 218. In this example, the dummy region 203 includes dummy fill structures 236, 238, and 240, each having different lateral dimensions that decrease in the direction from the through-silicon via region 201 to the functional region 205. In this way, the dummy fill structure 236 can have a first lateral dimension, the dummy fill structure 238 can have a second lateral dimension (which is less than the first lateral dimension), and the dummy fill structure 240 can have a third lateral dimension (which is less than the second lateral dimension). In addition, in an example where the structure 234 included in the stress release structure 232 has a fourth lateral dimension, the fourth lateral dimension is greater than the first lateral dimension of the dummy fill structure 236.

[0070] As Figure 4 shown, a chemical mechanical polishing process is performed on a semiconductor structure of Figure 3 which shows the advantages of including dummy fill structures 236, 238, and 240. The region thinned (e.g., reduced in thickness) by the chemical mechanical polishing process is represented by an oval 250. As shown, the chemical mechanical polishing process does not thin the active device 218. Specifically, the dummy fill structures 236, 238, and 240 are used to reduce dishing caused by the chemical mechanical polishing process, thereby protecting the active device 218.

[0071] As Figure 5 shown, an exemplary method 300 can be used to form a semiconductor structure. In some embodiments, method 300 can be used to form Figure 2 a part of the semiconductor device 100 as described and / or Figure 3 a part of the semiconductor device 200 as described. Method 300 can start with step 310. Step 312 of method 300 can specify a dummy region of the substrate of the semiconductor device, which is located between the through-silicon via region and the functional region.

[0072] Step 314 of method 300 can form one or more active devices in and / or on the substrate in the functional region. A variety of processes can be performed to form the active devices, including but not limited to one or more depositions, etchings, implantations, lithographies, annealings, and other suitable processes. In other embodiments, a substrate with active devices can be provided.

[0073] Step 316 of method 300 can form one or more stress relief structures in the substrate in the through-silicon via region. A variety of processes can be performed to form the stress relief structures, including but not limited to one or more depositions, etchings, implantations, lithographies, annealings, and other suitable processes. In other embodiments, a substrate with stress relief structures can be provided.

[0074] Step 318 of method 300 can form dummy fill structures in the substrate in the dummy region between the stress relief structures and the active devices. The dummy fill structures can have varying or different lateral dimensions in a first direction from the through-silicon via region to the functional region. In some embodiments, the dummy fill structures can be formed to define a gradient lateral dimension that decreases from a maximum lateral dimension to a minimum lateral dimension in the first direction.

[0075] In some embodiments, the method of forming the dummy fill structure may be to first form openings in the surface of a substrate or a layer thereon in a dummy region. In some embodiments, the lateral dimension of each opening in a first direction may correspond to the maximum lateral dimension of the dummy fill structure, the minimum lateral dimension of the dummy fill structure, or another lateral dimension between the maximum and minimum lateral dimensions. In some embodiments, a gradient lateral dimension may be defined by at least two consecutive portions of the dummy region, with the first of the consecutive portions including a first group of dummy fill structures having a maximum lateral dimension and the second of the consecutive portions including a second group of dummy fill structures having a minimum lateral dimension. The openings may be filled with one or more fill materials to form one or more fill layers in the openings to define the dummy fill structures. The one or more fill materials may include materials that react little or not at all with the etchant used in subsequent planarization of the through-silicon via regions. In some embodiments, the fill material may include a metallic material, such as but not limited to copper or its alloys.

[0076] In some embodiments, method 300 may include forming through-silicon vias in a through-silicon via region after forming the dummy fill structures in the dummy region. A variety of processes may be performed to form the through-silicon vias, including but not limited to one or more of deposition, etching, implantation, lithography, annealing, and other suitable processes. The step of forming the through-silicon vias may include performing one or more chemical mechanical polishing processes on the through-silicon via region. The one or more chemical mechanical polishing processes may include placing the semiconductor device in a carrier that presses the polishing surface (i.e., the through-silicon via region) against a polishing pad that is adhered to a roller. When a chemical mechanical polishing slurry containing polishing particles and a reactive chemical agent (such as an etchant) is applied to the polishing pad, the roller and the carrier may be rotated in opposite directions. By rotating the polishing pad, the chemical mechanical polishing slurry may be transferred to the surface of the semiconductor device. The combination of the relative movement of the polishing pad and the surface and the reactive chemical agent in the chemical mechanical polishing slurry may cause the chemical mechanical polishing to planarize the through-silicon via region by physical and chemical actions that may remove materials (such as polysilicon) that react with the reactive chemical agent.

[0077] Method 300 may end at step 320.

[0078] As described above, dishing may occur during the chemical mechanical polishing process. According to method 300, the dummy region includes dummy fill structures that react little or not at all with the reactive chemical agent (such as an etchant) during the chemical mechanical polishing process, and thus may be significantly resistant to thinning during the chemical mechanical polishing process. The inclusion of the dummy fill structures may limit overall dishing, thereby reducing or eliminating the negative impact of the chemical mechanical polishing process on the active devices in the functional regions. In summary, the total lateral dimension of the dummy region may be reduced, making the surface design of the semiconductor device more compact.

[0079] In the experimental studies of some embodiments described herein, a sample device having a through-silicon via region, a functional region, and a dummy region therebetween is fabricated, and the dummy fill structures contained in the dummy region have various lateral dimension patterns. A chemical mechanical polishing process is performed on the sample device to determine the effect of the various patterns on reducing dishing in the dummy region, and thereby reducing the impact of the chemical mechanical polishing process on the functional region (such as reducing the gate height). For example, Figure 6 The surface shows the patterns and test results of five sample devices. The lateral dimensions of the dummy fill structures of the polysilicon are measured in a first direction from the through-silicon via region to the functional region.

[0080] The first sample device (sample number 1) includes two sets of dummy fill structures having lateral dimensions of 54 nm and 6 nm in the first direction. The second sample device (sample number 2) includes three sets of dummy fill structures having lateral dimensions of 84 nm, 135 nm, and 6 nm in the first direction. The third sample device (sample number 3) includes three sets of dummy fill structures having lateral dimensions of 135 nm, 54 nm, and 6 nm in the first direction. The fourth sample device (sample number 4) includes five sets of dummy fill structures having lateral dimensions of 200 nm, 36 nm, 135 nm, 54 nm, and 6 nm in the first direction. The fifth sample device (sample number 5) includes five sets of dummy fill structures having lateral dimensions of 200 nm, 36 nm, 84 nm, 135 nm, and 6 nm in the first direction.

[0081] Figure 6 The table shows the topographical gap (such as the height change in the first direction, nm) in the dummy region after the chemical mechanical polishing process, and the impact distance (such as significant dishing, microns) of the through-silicon via region after the chemical mechanical polishing process. As shown. The first sample device has the smallest topographical gap (i.e., 0.26 nm), while the third sample device has the smallest impact distance (i.e., 28.2 microns). These results indicate that reducing the gradient lateral distance (such as the first sample and the third sample) can produce better results compared to different lateral dimensions (such as the second, fourth, and fifth samples).

[0082] Embodiments of the present invention thus provide a semiconductor device having a dummy region and a method of forming the same, and the dummy fill structures of the dummy region have varying lateral dimensions.

[0083] In one embodiment, a semiconductor device is provided that includes a through-silicon via extending through a substrate of the semiconductor device; active devices located within or on the substrate; and a dummy region of the substrate separating the through-silicon via from the active devices, the dummy region including a plurality of dummy fill structures, wherein the dummy fill structures have a lateral dimension in a first direction from the through-silicon via to the active devices, and wherein the lateral dimension of a first dummy fill structure in the dummy region is different from the lateral dimension of a second dummy fill structure.

[0084] In some embodiments, the lateral dimension of the dummy fill structures defines a gradient lateral dimension between the through-silicon via and the active devices that decreases from a maximum lateral dimension to a minimum lateral dimension in the first direction, wherein the maximum lateral dimension is from 50 nm to 200 nm and the minimum lateral dimension is less than or equal to 50 nm.

[0085] In some embodiments, the gradient lateral dimension is in a stepped form.

[0086] In some embodiments, the maximum lateral dimension is from 100 nm to 150 nm and the minimum lateral dimension is from 6 nm to 75 nm.

[0087] In some embodiments, the gradient lateral dimension is defined by at least two consecutive portions of the dummy region, a first one of the consecutive portions including a first group of dummy fill structures having the maximum lateral dimension and a second one of the consecutive portions including a second group of dummy fill structures having the minimum lateral dimension.

[0088] In some embodiments, the maximum lateral dimension is from 100 nm to 150 nm and the minimum lateral dimension is from 6 nm to 75 nm.

[0089] In some embodiments, at least some of the dummy fill structures include a metallic material.

[0090] In some embodiments, the semiconductor device further includes a stress relief structure in the substrate to surround the through-silicon via, wherein the stress relief structure has a second lateral dimension in the first direction and the second lateral dimension is greater than the lateral dimension of the dummy fill structures.

[0091] In some embodiments, the lateral dimension of the dummy region in the first direction is less than or equal to 100 microns.

[0092] In some embodiments, the lateral dimension of the dummy region in the first direction is less than or equal to 50 microns.

[0093] In another embodiment, a method of forming a semiconductor device is provided, which includes designating a dummy region of a substrate between a through-silicon via region of the substrate and a functional region of the substrate, the through-silicon via region being configured to include through-silicon vias extending through the substrate, and the functional region being configured to include active devices in or on the substrate; and forming a dummy fill structure in the dummy region, which has a lateral dimension in a first direction from the through-silicon via region to the functional region, wherein the lateral dimension of the dummy fill structure defines a gradient lateral dimension between the through-silicon via region and the functional region, which decreases from a maximum lateral dimension to a minimum lateral dimension in the first direction.

[0094] In some embodiments, the maximum lateral dimension is 50 nm to 200 nm, and the minimum lateral dimension is less than or equal to 50 nm.

[0095] In some embodiments, the gradient lateral dimension is defined by at least two consecutive portions of the dummy region, the first of the consecutive portions including a first set of dummy fill structures having the maximum lateral dimension, and the second of the consecutive portions including a second set of dummy fill structures having the minimum lateral dimension.

[0096] In some embodiments, the step of forming the dummy fill structure includes forming a plurality of openings in a surface of the substrate in the dummy region, wherein each opening has a third lateral dimension in the first direction that is the maximum lateral dimension, the minimum lateral dimension, or another lateral dimension between the maximum lateral dimension and the minimum lateral dimension; and filling the one or more openings with one or more fill materials to form one or more fill layers in the openings to define the dummy fill structure, wherein the hardness of the fill material is greater than the hardness of the material surrounding the dummy fill structure in the dummy region.

[0097] In some embodiments, the lateral dimension of the dummy region in the first direction is less than or equal to 100 microns.

[0098] In some embodiments, the lateral dimension of the dummy region in the first direction is less than or equal to 50 microns.

[0099] In some embodiments, the through-silicon via region includes a plurality of stress relief structures configured to surround the through-silicon vias, wherein the stress relief structures have a second lateral dimension in the first direction, and the second lateral dimension is greater than the lateral dimension of the dummy fill structure.

[0100] In yet another embodiment, a method of forming a semiconductor device is provided, which includes forming active devices in or on a substrate of the semiconductor device; forming a plurality of stress relief structures in the substrate, which are arranged to surround through-silicon vias; and forming a plurality of dummy fill structures between the stress relief structures and the active devices, wherein the stress relief structures have a first lateral dimension in a first direction from the stress relief structures to the active devices, the dummy fill structures have a second lateral dimension in the first direction, and the first lateral dimension of the stress relief structures is greater than the second lateral dimension of the dummy fill structures, wherein the second lateral dimension of the dummy fill structures defines a gradient lateral dimension between the stress relief structures and the active devices, which decreases from a maximum lateral dimension to a minimum lateral dimension in the first direction.

[0101] In some embodiments, the maximum lateral dimension is from 50 nm to 200 nm, and the minimum lateral dimension is less than or equal to 50 nm.

[0102] In some embodiments, the maximum lateral dimension is from 100 nm to 150 nm, and the minimum lateral dimension is from 6 nm to 75 nm.

[0103] In some embodiments, the gradient lateral dimension is defined by at least two consecutive portions of the substrate, the first of the consecutive portions including a first set of dummy fill structures having the maximum lateral dimension, and the second of the consecutive portions including a second set of dummy fill structures having the minimum lateral dimension.

[0104] In some embodiments, the stress relief structures and the active devices are separated by a third lateral dimension in the first direction, which is less than or equal to 100 microns.

[0105] In some embodiments, at least some of the dummy fill structures include a metallic material.

[0106] The features of the above embodiments are beneficial for those skilled in the art of the present technology to understand the present invention. Those skilled in the art of the present technology should understand that the present invention can be used as a basis to design and vary other processes and structures to achieve the same purpose and / or the same advantages of the above embodiments. Those skilled in the art of the present technology should also understand that these equivalent replacements do not depart from the concept and scope of the present invention, and can be changed, replaced, or varied without departing from the concept and scope of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A through-silicon via extending through a substrate of the semiconductor device; An active device located within or on the substrate; And A dummy region of the substrate separating the through-silicon via from the active device, the dummy region including a plurality of dummy fill structures, wherein the dummy fill structures have a lateral dimension in a first direction from the through-silicon via to the active device, and wherein a lateral dimension of a first dummy fill structure in the dummy region is different from a lateral dimension of a second dummy fill structure.

2. The semiconductor device according to claim 1, wherein, The lateral dimensions of the dummy fill structures define a gradient lateral dimension between the through-silicon via and the active device, which decreases from a maximum lateral dimension to a minimum lateral dimension in the first direction, wherein the maximum lateral dimension is 50 nm to 200 nm and the minimum lateral dimension is less than or equal to 50 nm.

3. The semiconductor device according to claim 2, wherein, The gradient lateral dimension is in a stepped form.

4. The semiconductor device according to claim 2, wherein The maximum lateral dimension is 100 nm to 150 nm and the minimum lateral dimension is 6 nm to 75 nm.

5. The semiconductor device according to claim 2, characterized in that, The gradient lateral dimension is defined by at least two consecutive portions of the dummy region, a first of the consecutive portions including a first group of dummy fill structures having the maximum lateral dimension and a second of the consecutive portions including a second group of dummy fill structures having the minimum lateral dimension.

6. The semiconductor device according to claim 5, wherein, The maximum lateral dimension is 100 nm to 150 nm and the minimum lateral dimension is 6 nm to 75 nm.

7. The semiconductor device according to claim 1, wherein Further comprising a stress relief structure in the substrate to surround the through-silicon via.

8. The semiconductor device according to claim 7, wherein, The stress relief structure has a second lateral dimension in the first direction and the second lateral dimension is greater than the lateral dimensions of the dummy fill structures.

9. The semiconductor device according to claim 1, wherein, The lateral dimension of the dummy region in the first direction is less than or equal to 100 microns.

10. The semiconductor device according to claim 1, wherein, The lateral dimension of the dummy region in the first direction is less than or equal to 50 microns.

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