Operational amplifier circuit, chip and electronic equipment

Abstract

The utility model provides an operational amplifier circuit, a chip and electronic equipment, and belongs to the technical field of electronics. The operational amplifier circuit comprises at least one high-voltage unit and at least one transistor unit; any high-voltage unit serves as a first target high-voltage unit, any transistor unit connected with the first target high-voltage unit serves as a first target transistor unit, the first end of the first target high-voltage unit is connected with the second end of the first target transistor unit, the first end refers to an output end, and the second end refers to an output end. The first end is an input end, the second end is an input end, or the first end is the input end, and the second end is an output end. According to the invention, the operational amplifier circuit can work in a high-voltage power supply domain.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to an operational amplifier circuit, a chip, and an electronic device. Background Art

[0002] An operational amplifier (abbreviated as "op-amp") is a circuit unit with a very high amplification factor. In an actual circuit, it is usually combined with a feedback network to form a certain functional module. It is an amplifier with a special coupling circuit and feedback. Its output signal can be the result of mathematical operations such as addition, subtraction, differentiation, or integration of the input signal. Since it was early applied in analog computers to perform mathematical operations, it was named "operational amplifier".

[0003] In some application scenarios, an op-amp circuit needs to work in a high-voltage power supply domain. However, the high-voltage power supply domain may cause a relatively high voltage drop of the devices in the existing op-amp circuit, exceeding the tolerable range and causing damage to the device, thereby affecting the normal operation of the system.

[0004] Therefore, there is an urgent need for an op-amp circuit that can be applied in a high-voltage power supply domain. Summary of the Utility Model

[0005] To solve the problems of the prior art, embodiments of this application provide an op-amp circuit, a chip, and an electronic device, and the op-amp circuit can work in a high-voltage power supply domain. The technical solutions are as follows:

[0006] According to one aspect of this application, an op-amp circuit is provided, and the op-amp circuit includes at least one high-voltage unit and at least one transistor unit;

[0007] Taking any high-voltage unit as a first target high-voltage unit, and taking any transistor unit connected to the first target high-voltage unit as a first target transistor unit, a first end of the first target high-voltage unit is connected to a second end of the first target transistor unit, where the first end refers to the output end and the second end refers to the input end, or the first end refers to the input end and the second end refers to the output end.

[0008] According to another aspect of this application, a chip is provided, including the above-mentioned op-amp circuit.

[0009] According to another aspect of this application, an electronic device is provided, including the above-mentioned op-amp circuit.

[0010] In this application, a high-voltage unit can be arranged in the op-amp circuit, and by means of the high-voltage unit, the input-output voltage, input-control voltage, or output-control voltage of the transistor unit is ensured to be within the withstand voltage range, so as to reduce the damage probability of the transistor unit. Thus, the op-amp module can also work normally in a high-voltage power supply domain and has the ability of a wide power supply domain. Description of the Drawings

[0011] In the following description of exemplary embodiments with reference to the drawings, more details, features, and advantages of the present application are disclosed. In the drawings:

[0012] Figure 1 A schematic diagram of the connection between a high-voltage unit and a transistor unit provided according to an exemplary embodiment of the present application is shown;

[0013] Figure 2 A schematic diagram of the connection between another high-voltage unit and a transistor unit provided according to an exemplary embodiment of the present application is shown;

[0014] Figure 3 A schematic diagram of an operational amplifier circuit provided according to an exemplary embodiment of the present application is shown;

[0015] Figure 4 A schematic diagram of a bias sub-circuit provided according to an exemplary embodiment of the present application is shown;

[0016] Figure 5 A schematic diagram of a first bias voltage branch provided according to an exemplary embodiment of the present application is shown;

[0017] Figure 6 A schematic diagram of a second bias voltage branch provided according to an exemplary embodiment of the present application is shown;

[0018] Figure 7 A schematic diagram of an operational amplifier circuit including a Zener diode provided according to an exemplary embodiment of the present application is shown.

[0019] In the figures,

[0020] 1. First target high-voltage unit; 2. First target transistor unit; 3. Second target transistor unit; 4. Second target high-voltage unit; 5. First input module; 6. Second input module; 7. Bias sub-circuit; 71. First bias current branch; 72. Second bias current branch; 73. First bias voltage branch; 731. First voltage division module; 74. Second bias voltage branch; 741. Second voltage division module. Detailed Embodiments

[0021] Embodiments of the present application will be described in more detail below with reference to the drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Instead, these embodiments are provided to more thoroughly and completely understand the present application. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes and are not used to limit the protection scope of the present application.

[0022] As used herein, the term "comprising" and its variations are open-ended, i.e., "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". The relevant definitions of other terms will be given in the following description. It should be noted that the concepts such as "first", "second", etc. mentioned in this application are only used to distinguish different devices, modules or units, and are not used to limit the order or interdependence of the functions performed by these devices, modules or units.

[0023] In addition, "a plurality of" in the embodiments of this application means two or more. In view of this, "a plurality of" in the embodiments of this application can also be understood as "at least two". "At least one" can be understood as one or more, for example, understood as one, two or more. For example, including at least one means including one, two or more, and does not limit which ones are included. For example, including at least one of A, B, and C, then what is included can be A, B, C, A and B, A and C, B and C, or A and B and C.

[0024] It should be pointed out that "connection" in the embodiments of this application can be understood as electrical connection, and the connection of two electrical components can be a direct or indirect connection between the two electrical components. For example, when A is connected to B, it can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0025] The names of the messages or information exchanged between multiple devices in the embodiments of this application are only for illustrative purposes and are not used to limit the scope of these messages or information.

[0026] The embodiments of this application provide an operational amplifier circuit, which can be integrated in a chip or disposed in an electronic device.

[0027] Referring to Figure 1 the schematic diagram of the connection between the high-voltage unit and the transistor unit shown, the operational amplifier circuit may include at least one high-voltage unit and at least one transistor unit.

[0028] Taking any high-voltage unit as the first target high-voltage unit 1 and taking any transistor unit connected to the first target high-voltage unit 1 as the first target transistor unit 2, the first end of the first target high-voltage unit 1 is connected to the second end of the first target transistor unit 2, where the first end refers to the output end and the second end refers to the input end, or the first end refers to the input end and the second end refers to the output end.

[0029] The implementation principle is as follows:

[0030] In this embodiment, the basic circuit of the operational amplifier circuit can adopt an existing structure, and the structure of this basic circuit is not limited herein. The operational amplifier circuit may include at least one transistor unit and other related devices to implement the operational amplifier function. Among them, there is a withstand voltage range for the voltages between the respective ports (i.e., the input terminal, the output terminal, and the control terminal) of the transistor unit. Within this withstand voltage range, the transistor unit can operate normally. If it exceeds this withstand voltage range, the transistor unit may be damaged. In the high-voltage power supply domain, the power supply voltage is relatively high, which may cause the voltage at the input terminal or the output terminal of the transistor unit to be correspondingly high. Therefore, a high-voltage unit can be used to ensure that the input-output voltage, the input-control voltage, or the output-control voltage of the transistor unit is within the withstand voltage range, so as to reduce the damage probability of the transistor unit.

[0031] Specifically, as Figure 1 shown in the schematic diagram of the connection between the high-voltage unit and the transistor unit, the output terminal of the first target high-voltage unit 1 can be connected to the input terminal of the first target transistor unit 2, or the output terminal of the first target transistor unit 2 can be connected to the input terminal of the first target high-voltage unit 1, that is, the first target high-voltage unit 1 and the first target transistor unit 2 are stacked longitudinally. That is, the input terminal of the P-type first target high-voltage unit 1 can be connected to the output terminal of the P-type first target transistor unit 2, and the input terminal of the N-type first target transistor unit 2 is connected to the output terminal of the N-type first target high-voltage unit 1.

[0032] Optionally, referring to Figure 2 another schematic diagram of the connection between the high-voltage unit and the transistor unit shown, when the control terminal of the second target transistor unit 3 is connected to the control terminal of the first target transistor unit 2, the second terminal of the second target transistor unit 3 is connected to the first terminal of the second target high-voltage unit 4, and the control terminal of the second target high-voltage unit 4 is connected to the control terminal of the first target high-voltage unit 1. That is to say, the connection relationship between the second target high-voltage unit 4 and the second target transistor unit 3 is the same as the connection relationship between the first target high-voltage unit 1 and the first target transistor unit 2, that is, the second target high-voltage unit 4 and the second target transistor unit 3 are stacked longitudinally.

[0033] In some possible implementation manners, the first target high-voltage unit 1 may be of the same type as the second target high-voltage unit 4. For example, both are P-type LDMOS (Laterally Diffused Metal Oxide Semiconductor) transistors; the first target transistor unit 2 may be of the same type as the second target transistor unit 3. For example, both are PMOS (Positive channel Metal Oxide Semiconductor) transistors. Taking the size ratio relationship between the first target high-voltage unit 1 and the second target high-voltage unit 4 as the first size ratio, and taking the size ratio relationship between the first target transistor unit 2 and the second target transistor unit 3 as the second size ratio, then the first size ratio may be equal to the second size ratio. Moreover, the control terminal of the first target high-voltage unit 1 is connected to the control terminal of the second target high-voltage unit 4, and the control terminal of the first target transistor unit 2 is connected to the control terminal of the second target transistor unit 3. Thus, the first target high-voltage unit 1, the first target transistor unit 2, the second target high-voltage unit 4, and the second target transistor unit 3 may form a mirror circuit, where the first target high-voltage unit 1 and the first target transistor unit 2 may serve as one mirror branch, and the second target high-voltage unit 4 and the second target transistor unit 3 may serve as another mirror branch.

[0034] Optionally, the operational amplifier circuit may include a folded cascode operational amplifier. Among them, the at least one high-voltage unit may include a first high-voltage unit LDMp1, a second high-voltage unit LDMp2, a third high-voltage unit LDMp3, a fourth high-voltage unit LDMp4, a fifth high-voltage unit LDMn1, a sixth high-voltage unit LDMn2, and a seventh high-voltage unit LDMn3, and the at least one transistor unit may include a first transistor unit Mp1, a second transistor unit Mp2, a third transistor unit Mp3, a fourth transistor unit Mp4, a fifth transistor unit Mn1, a sixth transistor unit Mn2, a seventh transistor unit Mn3, and an eighth transistor unit Mn4. The operational amplifier circuit may further include a first input module 5 and a second input module 6.

[0035] Among them, the first input module 5 and the second input module 6 may include PMOS transistors.

[0036] As Figure 3 shown in the operational amplifier circuit, the first end of the first transistor unit Mp1 is used to receive the power supply voltage, the second end is connected to the first end of the first high-voltage unit LDMp1, the control end is connected to the control end of the second transistor unit Mp2, and the control end of the first transistor unit Mp1 is further connected to the second end of the first high-voltage unit LDMp1;

[0037] The first terminal of the second transistor unit Mp2 is used to receive the power supply voltage, and the second terminal is connected to the first terminal of the second high-voltage unit LDMp2;

[0038] The first terminal of the third transistor unit Mp3 is used to receive the power supply voltage, the second terminal is connected to the first terminal of the third high-voltage unit LDMp3, and the control terminal is connected to the control terminal of the fourth transistor unit Mp4. The control terminal of the third transistor unit Mp3 is also connected to the second terminal of the third high-voltage unit LDMp3;

[0039] The first terminal of the fourth transistor unit Mp4 is used to receive the power supply voltage, and the second terminal is connected to the first terminal of the fourth high-voltage unit LDMp4;

[0040] The control terminal of the first high-voltage unit LDMp1 is connected to the control terminal of the second high-voltage unit LDMp2, and the second terminal is connected to the first terminal of the fifth high-voltage unit LDMn1;

[0041] The second terminal of the second high-voltage unit LDMp2 is connected to the first terminal of the first input module 5 and the first terminal of the second input module 6;

[0042] The control terminal of the third high-voltage unit LDMp3 is connected to the control terminal of the fourth high-voltage unit LDMp4, and the second terminal is connected to the first terminal of the sixth high-voltage unit LDMn2;

[0043] The second terminal of the fourth high-voltage unit LDMp4 is connected to the first terminal of the seventh high-voltage unit LDMn3 and is also connected to the output terminal of the operational amplifier circuit;

[0044] The second terminal of the fifth high-voltage unit LDMn1 is connected to the first terminal of the fifth transistor unit Mn1;

[0045] The control terminal of the sixth high-voltage unit LDMn2 is connected to the control terminal of the seventh high-voltage unit LDMn3, the second terminal is connected to the second terminal of the second input module 6, and the second terminal of the sixth high-voltage unit LDMn2 is also connected to the first terminal of the seventh transistor unit Mn3;

[0046] The first terminal of the seventh high-voltage unit LDMn3 is connected to the output terminal of the operational amplifier circuit, the second terminal is connected to the second terminal of the first input module 5, and the second terminal of the seventh high-voltage unit LDMn3 is also connected to the first terminal of the eighth transistor unit Mn4;

[0047] The control terminal of the fifth transistor unit Mn1 is connected to the control terminal of the sixth transistor unit Mn2, and the second terminal is grounded;

[0048] The first terminal of the sixth transistor unit Mn2 is used to receive the bias current, the control terminal is connected to the first terminal of the sixth transistor unit Mn2, and the second terminal is grounded;

[0049] The control terminal of the seventh transistor unit Mn3 is connected to any one of the control terminals of the fifth transistor unit Mn1 and the sixth transistor unit Mn2, and the second terminal is grounded;

[0050] The control terminal of the eighth transistor unit Mn4 is connected to the control terminal of the seventh transistor unit Mn3, and the second terminal is grounded;

[0051] The third terminal of the first input module 5 is used to receive the first input signal of the operational amplifier circuit, and the third terminal of the second input module 6 is used to receive the second input signal of the operational amplifier circuit.

[0052] Wherein, the first input signal of the operational amplifier circuit may refer to the non-inverting input signal, and the second input signal may refer to the inverting input signal; or, the first input signal of the operational amplifier circuit may refer to the inverting input signal, and the second input signal may refer to the non-inverting input signal.

[0053] Optionally, the first high-voltage unit, the second high-voltage unit, the third high-voltage unit, and the fourth high-voltage unit may include P-type LDMOS transistors, and the control terminal of the P-type LDMOS transistor is used to receive the first bias voltage;

[0054] The fifth high-voltage unit, the sixth high-voltage unit, and the seventh high-voltage unit may include N-type LDMOS transistors, and the control terminal of the N-type LDMOS transistor is used to receive the second bias voltage.

[0055] Wherein, the first bias voltage and the second bias voltage are different, the first bias voltage may include a low-voltage bias voltage, and the second bias voltage may include a high-voltage bias voltage.

[0056] Optionally, the operational amplifier circuit further includes a bias sub-circuit 7, the bias sub-circuit 7 includes a first bias current branch 71 and a second bias current branch 71, and the above-mentioned bias current may be generated by the first bias current branch 71 and the second bias current branch 71. The first bias current branch 71 may include a ninth transistor unit Mp5, a tenth transistor unit Mn5, an eighth high-voltage unit LDMp5, and a ninth high-voltage unit LDMn4, and the second bias current branch 72 includes an eleventh transistor unit Mp6, a twelfth transistor unit Mn6, a tenth high-voltage unit LDMp6, an eleventh high-voltage unit LDMn5, and a resistor unit R.

[0057] As Figure 4 In the shown bias sub-circuit, the first terminal of the ninth transistor unit Mp5 is used to receive the power supply voltage, the control terminal is connected to the control terminal of the eleventh transistor unit Mp6, and the second terminal is connected to the first terminal of the eighth high-voltage unit LDMp5;

[0058] The control terminal of the eighth high-voltage unit LDMp5 is connected to the control terminal of the tenth high-voltage unit LDMp6, and the second terminal is connected to the first terminal of the ninth high-voltage unit LDMn4;

[0059] The control terminal of the ninth high-voltage unit LDMn4 is connected to the control terminal of the eleventh high-voltage unit LDMn5, and the second terminal is connected to the first terminal of the tenth transistor unit Mn5;

[0060] The control terminal of the tenth transistor unit Mn5 is connected to the control terminal of the twelfth transistor unit Mn6, and the control terminal of the tenth transistor unit Mn5 is also connected to the first terminal of the ninth high-voltage unit LDMn4;

[0061] The first terminal of the eleventh transistor Mp6 is used to receive the power supply voltage, the control terminal is connected to the second terminal of the tenth high-voltage unit LDMp6, and the second terminal is connected to the first terminal of the tenth high-voltage unit LDMp6;

[0062] The second terminal of the tenth high-voltage unit LDMp6 is connected to the first terminal of the eleventh high-voltage unit LDMn5;

[0063] The second terminal of the eleventh high-voltage unit LDMn5 is connected to the first terminal of the twelfth transistor unit Mn6;

[0064] The second terminal of the twelfth transistor unit Mn6 is connected to the first terminal of the resistor unit R;

[0065] The second terminal of the resistor unit R is grounded.

[0066] The implementation principle is as follows:

[0067] Mp5 and Mp6 have the same size, LDMp5 and LDMp6 have the same size, LDMn4 and LDMn5 have the same size, and the aspect ratio of Mn5 is K times that of Mn6, where K > 0. The bias current can be generated according to Mn5, Mn6, and the resistor unit R, specifically:

[0068]

[0069] Among them, Ibias represents the bias current, μ n represents the carrier mobility, C ox represents the gate oxide capacitance per unit area, represents the aspect ratio of Mn6, R represents the resistance value of the resistor unit R, and K refers to the multiple of the aspect ratio of Mn5 to that of Mn6.

[0070] Optionally, the bias sub-circuit 7 may further include a first bias voltage branch 73 and a second bias voltage branch 74. The first bias voltage branch 73 may include a thirteenth transistor unit Mn7, a twelfth high-voltage unit LDMn6, and a first voltage division module 731, and the second bias voltage branch 74 may include a fourteenth transistor unit Mp7, a thirteenth high-voltage unit LDMp7, and a second voltage division module 741.

[0071] In Figure 5 the first bias voltage branch shown in the figure, the first end of the first voltage dividing module 731 is used to receive the power supply voltage, the second end is connected to the first end of the twelfth high-voltage unit LDMn6, the second end of the first voltage dividing module 731 is also connected to the output end of the first bias voltage branch 73, and the output end of the first bias voltage branch 73 is used to output the first bias voltage;

[0072] The control end of the twelfth high-voltage unit LDMn6 is connected to any one of the control ends of the ninth high-voltage unit LDMn4 and the eleventh high-voltage unit LDMn5, and the second end is connected to the first end of the thirteenth transistor unit Mn7;

[0073] The control end of the thirteenth transistor unit Mn7 is connected to any one of the control ends of the tenth transistor unit Mn5 and the twelfth transistor unit Mn6, and the second end is grounded.

[0074] In Figure 6 the second bias voltage branch shown in the figure, the first end of the fourteenth transistor unit Mp7 is used to receive the power supply voltage, the control end is connected to any one of the control ends of the ninth transistor unit Mp5 and the eleventh transistor unit Mp6, and the second end is connected to the first end of the thirteenth high-voltage unit LDMp7;

[0075] The control end of the thirteenth high-voltage unit LDMp7 is connected to any one of the control ends of the eighth high-voltage unit LDMp5 and the tenth high-voltage unit LDMp6, the second end is connected to the first end of the second voltage dividing module 741, the second end of the thirteenth high-voltage unit LDMp7 is also connected to the output end of the second bias voltage branch 74, and the output end of the second bias voltage branch 74 is used to output the second bias voltage;

[0076] The second end of the second voltage dividing module 741 is grounded.

[0077] The implementation principle is as follows:

[0078] In order to improve the matching of the bias voltage with the current high-voltage power supply domain, the vertically stacked twelfth high-voltage unit LDMn6 and the thirteenth transistor unit Mn7 can be used as a mirror branch of the bias current, and the vertically stacked fourteenth transistor unit Mp7 and the thirteenth high-voltage unit LDMp7 can be used as another mirror branch of the bias current to mirror the bias current in the first bias current branch 71 and the second bias current branch 72.

[0079] The first voltage dividing module 731 and the second voltage dividing module 741 may include diode-connected transistors or other impedance devices, such that when the mirrored bias current flows through the voltage dividing module, a desired bias voltage can be generated at one end of the voltage dividing module. Among them, the diode-connected transistors may be low-voltage MOS transistors, high-voltage MOS transistors, LDMOS transistors or BJTs (Bipolar Junction Transistors), etc., and this embodiment does not limit this.

[0080] Optionally, the eighth high-voltage unit LDMp5, the tenth high-voltage unit LDMp6 and the thirteenth high-voltage unit LDMp7 may include P-type LDMOS transistors, and the ninth high-voltage unit LDMn4, the eleventh high-voltage unit LDMn5 and the twelfth high-voltage unit LDMn6 may include N-type LDMOS transistors.

[0081] Optionally, the operational amplifier circuit may further include a capacitor unit C. The first end of the capacitor unit C is connected to the output end of the operational amplifier circuit, and the second end of the capacitor unit C is used to receive the power supply voltage. Since the second end of the capacitor unit C is connected to the power supply, when the power supply jitters, the capacitor unit C can filter the fluctuations of the power supply voltage, and can effectively reduce the occurrence of safety problems caused by power supply jitters.

[0082] Optionally, the operational amplifier circuit further includes at least one Zener diode unit, and the Zener diode unit is disposed across the voltage clamping target device.

[0083] Among them, the voltage clamping target device may refer to a device in the operational amplifier circuit affected by instantaneous voltage.

[0084] In a possible implementation manner, during the power-on process of the power supply, the power supply voltage may overshoot or undershoot, resulting in an excessive instantaneous voltage value, which may cause device damage. According to the voltage clamping characteristic of the Zener diode unit, the voltage across the Zener diode unit can be clamped within a set range. Therefore, according to actual needs, the two ends of the Zener diode unit can be respectively connected to the two ends of the device that may be damaged to clamp the voltage of the device within the set range, reduce the risk of device damage during the power-on process, and improve the circuit safety.

[0085] As a specific example, as Figure 7 shown in the operational amplifier circuit, which may include Zener diodes D1, D2, D3, D4, D5. It should be noted that in addition to the setting manner of the Zener diode unit shown above Figure 7 According to actual needs, there may also be other specific setting manners, and this embodiment does not limit the specific setting manner of the Zener diode unit.

[0086] The embodiments of the present application can achieve the following beneficial effects:

[0087] (1) A high-voltage unit can be set in the operational amplifier circuit. By means of the high-voltage unit, the voltage between the input terminal and the output terminal, the voltage between the input terminal and the control terminal, or the voltage between the output terminal and the control terminal of the transistor unit is ensured to be within the withstand voltage range, so as to reduce the damage probability of the transistor unit. Thereby enabling the operational amplifier module to also work properly in the high-voltage power supply domain and having the ability of a wide power supply domain.

[0088] (2) The capacitor unit in the operational amplifier module can effectively reduce the occurrence of safety problems caused by power supply jitter.

[0089] (3) By using a Zener diode, the voltage of the device is clamped within a set range, reducing the risk of damaging the device during the power-on process and improving the circuit safety.

[0090] The exemplary embodiments of the present application further provide a chip, including the operational amplifier circuit provided by the embodiments of the present application. A high-voltage unit can be set in the operational amplifier circuit. By means of the high-voltage unit, the voltage between the input terminal and the output terminal, the voltage between the input terminal and the control terminal, or the voltage between the output terminal and the control terminal of the transistor unit is ensured to be within the withstand voltage range, so as to reduce the damage probability of the transistor unit. Furthermore, the chip can work properly in the high-voltage power supply domain and has the ability of a wide power supply domain.

[0091] The exemplary embodiments of the present application further provide an electronic device, including the operational amplifier circuit provided by the embodiments of the present application. A high-voltage unit can be set in the operational amplifier circuit. By means of the high-voltage unit, the voltage between the input terminal and the output terminal, the voltage between the input terminal and the control terminal, or the voltage between the output terminal and the control terminal of the transistor unit is ensured to be within the withstand voltage range, so as to reduce the damage probability of the transistor unit. Furthermore, the electronic device can work properly in the high-voltage power supply domain and has the ability of a wide power supply domain.

[0092] The above has introduced in detail an operational amplifier circuit, a chip and an electronic device provided by the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. An operational amplifier circuit, characterized in that, The operational amplifier circuit includes at least one high-voltage unit and at least one transistor unit; Taking any one of the high-voltage units as the first target high-voltage unit, and taking any one of the transistor units connected to the first target high-voltage unit as the first target transistor unit, the first end of the first target high-voltage unit is connected to the second end of the first target transistor unit, where the first end refers to the output end and the second end refers to the input end, or the first end refers to the input end and the second end refers to the output end.

2. The operational amplifier circuit according to claim 1, wherein When the control end of the second target transistor unit is connected to the control end of the first target transistor unit, the second end of the second target transistor unit is connected to the first end of the second target high-voltage unit, and the control end of the second target high-voltage unit is connected to the control end of the first target high-voltage unit.

3. The operational amplifier circuit according to claim 2, characterized in that, The at least one high-voltage unit includes a first high-voltage unit, a second high-voltage unit, a third high-voltage unit, a fourth high-voltage unit, a fifth high-voltage unit, a sixth high-voltage unit, and a seventh high-voltage unit, the at least one transistor unit includes a first transistor unit, a second transistor unit, a third transistor unit, a fourth transistor unit, a fifth transistor unit, a sixth transistor unit, a seventh transistor unit, and an eighth transistor unit, and the operational amplifier circuit further includes a first input module and a second input module; The first end of the first transistor unit is used to receive the power supply voltage, the second end is connected to the first end of the first high-voltage unit, the control end is connected to the control end of the second transistor unit, and the control end of the first transistor unit is further connected to the second end of the first high-voltage unit; The first end of the second transistor unit is used to receive the power supply voltage, and the second end is connected to the first end of the second high-voltage unit; The first end of the third transistor unit is used to receive the power supply voltage, the second end is connected to the first end of the third high-voltage unit, the control end is connected to the control end of the fourth transistor unit, and the control end of the third transistor unit is further connected to the second end of the third high-voltage unit; The first end of the fourth transistor unit is used to receive the power supply voltage, and the second end is connected to the first end of the fourth high-voltage unit; The control end of the first high-voltage unit is connected to the control end of the second high-voltage unit, and the second end is connected to the first end of the fifth high-voltage unit; The second end of the second high-voltage unit is connected to the first end of the first input module and the first end of the second input module; The control end of the third high-voltage unit is connected to the control end of the fourth high-voltage unit, and the second end is connected to the first end of the sixth high-voltage unit; The second end of the fourth high-voltage unit is connected to the first end of the seventh high-voltage unit and is also connected to the output end of the operational amplifier circuit; The second end of the fifth high-voltage unit is connected to the first end of the fifth transistor unit; The control end of the sixth high-voltage unit is connected to the control end of the seventh high-voltage unit, the second end is connected to the second end of the second input module, and the second end of the sixth high-voltage unit is further connected to the first end of the seventh transistor unit; The first end of the seventh high-voltage unit is connected to the output end of the operational amplifier circuit, the second end is connected to the second end of the first input module, and the second end of the seventh high-voltage unit is also connected to the first end of the eighth transistor unit; The control end of the fifth transistor unit is connected to the control end of the sixth transistor unit, and the second end is grounded; The first end of the sixth transistor unit is used to receive a bias current, the control end is connected to the first end of the sixth transistor unit, and the second end is grounded; The control end of the seventh transistor unit is connected to any one of the control end of the fifth transistor unit and the control end of the sixth transistor unit, and the second end is grounded; The control end of the eighth transistor unit is connected to the control end of the seventh transistor unit, and the second end is grounded; The third end of the first input module is used to receive the first input signal of the operational amplifier circuit, and the third end of the second input module is used to receive the second input signal of the operational amplifier circuit.

4. The operational amplifier circuit according to claim 3, characterized in that, The first high-voltage unit, the second high-voltage unit, the third high-voltage unit, and the fourth high-voltage unit include P-type LDMOS transistors, and the control end of the P-type LDMOS transistor is used to receive a first bias voltage; The fifth high-voltage unit, the sixth high-voltage unit, and the seventh high-voltage unit include N-type LDMOS transistors, and the control end of the N-type LDMOS transistor is used to receive a second bias voltage.

5. The operational amplifier circuit according to claim 1, characterized in that, The operational amplifier circuit further includes a bias sub-circuit, the bias sub-circuit includes a first bias current branch and a second bias current branch, the first bias current branch includes a ninth transistor unit, a tenth transistor unit, an eighth high-voltage unit, and a ninth high-voltage unit, and the second bias current branch includes an eleventh transistor unit, a twelfth transistor unit, a tenth high-voltage unit, an eleventh high-voltage unit, and a resistor unit; The first end of the ninth transistor unit is used to receive a power supply voltage, the control end is connected to the control end of the eleventh transistor unit, and the second end is connected to the first end of the eighth high-voltage unit; The control end of the eighth high-voltage unit is connected to the control end of the tenth high-voltage unit, and the second end is connected to the first end of the ninth high-voltage unit; The control end of the ninth high-voltage unit is connected to the control end of the eleventh high-voltage unit, and the second end is connected to the first end of the tenth transistor unit; The control end of the tenth transistor unit is connected to the control end of the twelfth transistor unit, and the control end of the tenth transistor unit is also connected to the first end of the ninth high-voltage unit; The first end of the eleventh transistor is used to receive a power supply voltage, the control end is connected to the second end of the tenth high-voltage unit, and the second end is connected to the first end of the tenth high-voltage unit; The second end of the tenth high-voltage unit is connected to the first end of the eleventh high-voltage unit; The second end of the eleventh high-voltage unit is connected to the first end of the twelfth transistor unit; The second end of the twelfth transistor unit is connected to the first end of the resistor unit; The second end of the resistor unit is grounded.

6. The operational amplifier circuit according to claim 5, wherein The bias sub-circuit further includes a first bias voltage branch and a second bias voltage branch. The first bias voltage branch includes a thirteenth transistor unit, a twelfth high-voltage unit, and a first voltage division module. The first bias voltage branch includes a fourteenth transistor unit, a thirteenth high-voltage unit, and a second voltage division module; The first end of the first voltage division module is used to receive the power supply voltage, the second end is connected to the first end of the twelfth high-voltage unit, and the second end of the first voltage division module is also connected to the output end of the first bias voltage branch. The output end of the first bias voltage branch is used to output a first bias voltage; The control end of the twelfth high-voltage unit is connected to any one of the control ends of the ninth high-voltage unit and the eleventh high-voltage unit, and the second end is connected to the first end of the thirteenth transistor unit; The control end of the thirteenth transistor unit is connected to any one of the control ends of the tenth transistor unit and the twelfth transistor unit, and the second end is grounded; The first end of the fourteenth transistor unit is used to receive the power supply voltage, the control end is connected to any one of the control ends of the ninth transistor unit and the eleventh transistor unit, and the second end is connected to the first end of the thirteenth high-voltage unit; The control end of the thirteenth high-voltage unit is connected to any one of the control ends of the eighth high-voltage unit and the tenth high-voltage unit, and the second end is connected to the first end of the second voltage division module. The second end of the thirteenth high-voltage unit is also connected to the output end of the second bias voltage branch. The output end of the second bias voltage branch is used to output a second bias voltage; The second end of the second voltage division module is grounded.

7. The operational amplifier circuit according to claim 6, wherein The eighth high-voltage unit, the tenth high-voltage unit, and the thirteenth high-voltage unit include P-type LDMOS transistors, and the ninth high-voltage unit, the eleventh high-voltage unit, and the twelfth high-voltage unit include N-type LDMOS transistors.

8. The operational amplifier circuit according to claim 1, wherein The operational amplifier circuit further includes a capacitor unit. The first end of the capacitor unit is connected to the output end of the operational amplifier circuit, and the second end of the capacitor unit is used to receive the power supply voltage.

9. The operational amplifier circuit according to claim 1, characterized in that The operational amplifier circuit further includes at least one Zener diode unit, and the Zener diode unit is disposed across the voltage clamping target device.

10. A chip, characterized in that, It includes the operational amplifier circuit according to at least one of claims 1-9.

11. An electronic device, characterized in that, It includes the operational amplifier circuit according to at least one of claims 1-9.

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