Structure for improving interconnection equal arm branch topology signal quality and circuit board

Abstract

The utility model discloses a structure and a circuit board for improving interconnection equal armed branch topology signal quality, comprising a topology trunk and a plurality of levels of topology branches, the topology branches are symmetrically arranged, the topology trunk is divided into a first trunk line connected with a control chip and a second trunk line connected with the first level of topology branch, and the second trunk line is connected with the second level of topology branch. The characteristic impedance of the first trunk line is smaller than that of the second trunk line, and the length of the first trunk line is not smaller than that of the second trunk line. According to the utility model, by controlling the characteristic impedance of the routing of the main part of the topology in a segmented manner, the accumulation of reflected signals at near-end particles is reduced, and the energy loss of the signals in the transmission process is reduced. And secondly, due to mutual offset of positive reflection and negative reflection, back-and-forth reflection oscillation of the signal in the topological structure is reduced, excess energy is reduced, and the stability and reliability of signal transmission are improved. In addition, the structure also optimizes the impedance continuity of a signal transmission path, reduces signal reflection and distortion caused by impedance mismatching, and further improves the integrity of the signal.

Description

Technical Field

[0001] The utility model relates to the technical field of topological structures, and more specifically, to a structure and a circuit board for improving the signal quality of an interconnected equal-arm branch topology. Background Art

[0002] With the continuous upgrade of DDR (Double Data Rate Synchronous Dynamic Random Access Memory) technology, the signal transmission rate is constantly increasing, which poses higher requirements for the interconnection design of PCBs. In high-speed multi-load application scenarios, due to the influence of capacitive loads and parasitic capacitances, the non-ideal effects on the PCB become particularly significant.

[0003] Specifically, ordinary vias, chip packages, and chip dies on the PCB will all generate parasitic capacitances, and these capacitances will significantly affect the effective characteristic impedance of the signal path during the transmission of high-frequency signals. Due to the existence of capacitive loads, the signal will encounter impedance discontinuities during transmission, thereby causing signal reflections, which restricts the implementation of high-speed multi-load DDRX interconnection design. In addition, traditional designs optimize the signal transmission performance by making the characteristic impedances of each section of the same signal equal, but in a high-speed multi-load environment, due to the influence of capacitive loads, the actual effective characteristic impedance often deviates from the preset value, further exacerbating the signal integrity problem.

[0004] The above deficiencies need to be improved. Summary of the Invention

[0005] In order to solve the problem in the prior art that in high-speed multi-load application scenarios, due to the influence of capacitive loads and parasitic capacitances, the implementation of high-speed multi-load DDRX interconnection design is restricted, the utility model provides a structure and a circuit board for improving the signal quality of an interconnected equal-arm branch topology.

[0006] The technical solution of the utility model is as follows:

[0007] A structure and a circuit board for improving the signal quality of an interconnected equal-arm branch topology, including a topological main trunk and multiple levels of topological branches. Each level of the topological branches is symmetrically arranged. The topological main trunk is divided into a first main line connected to a control chip and a second main line connected to the first level of the topological branches. The characteristic impedance of the first main line is less than that of the second main line, and the length of the first main line is not less than that of the second main line.

[0008] Further, the characteristic impedances of the branches in each level of the topological branches are the same.

[0009] Further, the lengths of the branches in each level of the topological branches are the same.

[0010] Furthermore, the characteristic impedance of the second main line is the same as that of the topological branch.

[0011] Furthermore, the characteristic impedance of the first main line is 70% of the characteristic impedance of the second main line.

[0012] Furthermore, the length of the first main line is 1 - 2 times the length of the second main line.

[0013] Furthermore, the length of the first main line is 1 times the length of the second main line.

[0014] Furthermore, the length of the first main line is 1.5 times the length of the second main line.

[0015] Furthermore, the length of the first main line is 2 times the length of the second main line.

[0016] A circuit board includes the structure for improving the signal quality of the interconnected equal - arm branch topology as described above.

[0017] For the present utility model according to the above - mentioned solution, the beneficial effects are as follows: By segmentally controlling the characteristic impedance of the trace in the topological main part, the present utility model realizes the control of the reflected signal, effectively reducing the accumulation of the reflected signal at the proximal particles, and reducing the energy loss during signal transmission. Secondly, the mutual cancellation of positive and negative reflections significantly reduces the back - and - forth reflection oscillation of the signal within the topological structure, reduces the redundant energy, and improves the stability and reliability of signal transmission. In addition, this structure also optimizes the impedance continuity of the signal transmission path, reduces the signal reflection and distortion caused by impedance mismatch, and further improves the integrity and quality of the signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present utility model, the following will briefly introduce the drawings required for use in the embodiments or the description of the prior art. Obviously, the following - described drawings are only some embodiments of the present utility model. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0019] Figure 1 It is a schematic diagram of the topological structure of the prior art;

[0020] Figure 2 It is a schematic diagram of the simulation waveform when Z1 = Z2 = Z3 = 50Ω in the prior art;

[0021] Figure 3 It is a schematic diagram of the topological structure of the present utility model;

[0022] Figure 4The simulation waveform diagram when Z2 = Z3 = 50Ω, Z1 = 0.7Z2 = 35Ω, and L11 = L22 in the present utility model;

[0023] Figure 5 The simulation waveform diagram when Z2 = Z3 = 50Ω, Z1 = 0.7Z2 = 35Ω, and L11 = 1.5L22 in the present utility model;

[0024] Figure 6 The simulation waveform diagram when Z2 = Z3 = 50Ω, Z1 = 0.7Z2 = 35Ω, and L11 = 2L22 in the present utility model;

[0025] Figure 7 The structural diagram for calculating the impedance of a microstrip line;

[0026] Figure 8 The structural diagram for calculating the impedance of a stripline.

[0027] Among them, the reference numerals in the figure: 1, the topological backbone; 101, the first main line; 102, the second main line; 2, the topological branch; 201, the first-level topological branch; 202, the second-level topological branch; 3, the control chip; 4, the load chip. Detailed implementation manners

[0028] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present utility model clearer and more understandable, the present utility model will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present utility model and are not used to limit the present utility model.

[0029] It should be noted that when a component is referred to as "fixed" or "set" or "connected" to another component, it can be directly or indirectly located on that other component. The orientations or positions indicated by the terms "upper", "lower", "left", "right", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientations or positions shown in the drawings, and are only for the convenience of description and cannot be construed as a limitation to the technical solution of the present application. The terms "first", "second", etc. are only used for the purpose of convenient description and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of technical features. The meaning of "plural" is two or more, unless otherwise clearly and specifically defined. The meaning of "several" is one or more, unless otherwise clearly and specifically defined.

[0030] Such as Figure 1As shown in the figure, in an embodiment of the present utility model, a structure for improving the signal quality of an interconnected equal-arm branch topology includes a topology backbone 1 and multiple levels of topology branches 2. Each level of topology branches 2 is symmetrically arranged. The topology backbone 1 is divided into a first main line 101 connected to the control chip 3 and a second main line 102 connected to the first-level topology branch 201. The characteristic impedance of the first main line 101 is less than that of the second main line 102, and the length of the first main line 101 is not less than that of the second main line 102.

[0031] Specifically, the topology branch 2 includes two levels. There are 2 first-level topology branches 201 and 4 second-level topology branches 202. Each first-level topology branch 201 is connected to two second-level topology branches 202 respectively, and the second-level topology branches 202 are respectively connected to a load chip 4. In practical applications, the topology branch 2 can be provided with three levels, four levels, etc., and the last-level topology branch 2 is connected to the load chip 4.

[0032] This structure controls signal reflection and reduces oscillation by controlling the characteristic impedance and length of each section of the topology backbone 1, thereby improving signal integrity and signal quality. Specifically, the topology backbone 1 is divided into a first main line 101 directly connected to the control chip 3 and a second main line 102 connected to the first-level topology branch 201. By adjusting the characteristic impedance of the first main line 101 to be lower than that of the second main line 102 and ensuring that the length of the first main line 101 is not less than that of the second main line 102, when the signal propagates along the first main line 101 to the second main line 102, due to impedance mismatch, a reflected wave will be generated. The reflected wave can meet the reflected wave from the branch during the subsequent propagation process and produce positive and negative reflection effects due to the phase difference, thereby canceling each other out, effectively reducing the back-and-forth reflection oscillation of the signal within the topology structure, reducing signal attenuation and distortion, and improving the overall quality of the signal.

[0033] In this embodiment, through the above-mentioned interconnected equal-arm branch topology structure, the transmission quality of signals in a high-speed multi-load environment is improved. First, by segmentally controlling the characteristic impedance of the trace of the topology backbone 1, the control of the reflected signal is realized, effectively reducing the accumulation of the reflected signal at the proximal particles and reducing the energy loss of the signal during transmission. Second, the mutual cancellation of positive and negative reflections significantly reduces the back-and-forth reflection oscillation of the signal within the topology structure, reduces redundant energy, and improves the stability and reliability of signal transmission. In addition, this structure also optimizes the impedance continuity of the signal transmission path, reduces signal reflection and distortion caused by impedance mismatch, and further improves signal integrity and quality.

[0034] As Figure 2 shown, in a preferred example, the characteristic impedance of each branch in each level of topology branches 2 is the same.

[0035] The lengths of all branches in each level of the topological branches 2 are the same.

[0036] The characteristic impedance of the second main line 102 is the same as that of the topological branch 2.

[0037] By keeping the characteristic impedance and length of each branch in each level of the topological branches 2 consistent, and matching the characteristic impedance of the second main line 102 with that of the topological branch 2, the impedance of the signal is continuous when passing through different branches, thereby reducing the signal reflection caused by impedance mismatch. At the same time, since the lengths of all branches are the same, the propagation time of the signal between branches is also consistent, which helps to control the phase relationship of the reflected waves within the topological structure, enabling the reflected waves from different branches to meet and cancel each other at specific positions. In addition, the matching of the characteristic impedance between the second main line 102 and the topological branch 2 further reduces the impedance mutation during signal transmission, reduces unnecessary reflections, and improves the smoothness of signal transmission.

[0038] In this embodiment, due to the symmetry and consistency of the topological branch 2, the signal transmission within the topological structure is more stable, reducing signal attenuation and distortion caused by impedance mismatch and length difference. Secondly, the mutual cancellation of the reflected waves is further enhanced because the reflected waves of all branches have similar phases and amplitudes, making it easier to form positive and negative reflection effects at specific positions, thereby effectively reducing the accumulation of reflected signals within the topological structure, improving signal integrity, reducing the noise level during signal transmission, and enabling the signal to remain clear and stable in a high-speed multi-load environment.

[0039] As Figure 2 shown, in a preferred example, the characteristic impedance of the first main line 101 is 70% of the characteristic impedance of the second main line 102.

[0040] In this embodiment, by precisely setting the ratio of the characteristic impedance between the first main line 101 and the second main line 102, the impedance gradient enables the signal to experience a smooth impedance change process when transitioning from the first main line 101 to the second main line 102, rather than a sudden impedance jump, effectively reducing the reflection intensity of the signal during the transition between main lines and reducing signal attenuation and distortion caused by impedance mutation. The setting of the impedance gradient optimizes the phase relationship of the reflected waves, enabling the reflected waves from different branches to cancel each other more effectively when they meet at specific positions. In addition, the introduction of the impedance gradient also enhances the mutual cancellation effect of the reflected waves, further reducing the accumulation of reflected signals within the topological structure and improving the integrity and stability of signal transmission.

[0041] Specifically, the characteristic impedance of each level of the topological branches 2 and the characteristic impedance of the second main line 102 are both 50Ω, and the characteristic impedance of the first main line 101 is 35Ω.

[0042] On the premise of the stack-up being determined, by changing the line width of the trace, the characteristic impedance of the trace is changed, so that the characteristic impedances of the first main line 101 and the second main line 102 are different.

[0043] In PCB design, in order to reduce or increase the characteristic impedance (Z0) of the trace, when the stack-up structure has been determined (the stack-up of different single boards will be different, that is, Er, T, and H in the characteristic impedance calculation formula of the trace are different. If the stack-up of the single board is determined, Er, T, and H are determined accordingly), according to the microstrip line impedance and stripline impedance calculation formulas, the impedance adjustment can be achieved by increasing or decreasing the corresponding trace width (W in the formula):

[0044] As Figure 7 shown, the microstrip line impedance (surface trace):

[0045]

[0046] (Valid·when·0.1<W / H<2.0·and·1<Er<15)

[0047] Z0 represents the characteristic impedance; Er represents the dielectric constant; W represents the trace width; T represents the trace copper thickness; H represents the distance between the trace and the adjacent reference plane.

[0048] As Figure 8 shown, the stripline impedance (inner layer trace):

[0049]

[0050] (Valid·when·W / H<0.35·and·T / H<0.25)

[0051] Here, H represents the distance between adjacent reference planes.

[0052] As Figure 2 shown, in a preferred example, the length of the first main line 101 is 1 - 2 times the length of the second main line 102.

[0053] The length of the first main line 101 is 1 times the length of the second main line 102.

[0054] The length of the first main line 101 is 1.5 times the length of the second main line 102.

[0055] The length of the first main line 101 is 2 times the length of the second main line 102.

[0056] The following is the simulation comparison of specific values:

[0057] Simulation parameter settings: In the simulation model, the parameters such as DDR4 address, control signals, and routing topologies are the same. The signal rate is 1600 Mbps. The driving chip uses an Intel FPGA, model 1SX110HN2F43E2VG, with a driving internal resistance of 34 ohms. The receiving chip uses Micron, model MT40A2G8JC.

[0058] In the traditional method, the routing topology is as Figure 1 shown. The characteristic impedance Z1 of the first main line 101, the characteristic impedance Z2 of the second main line 102, and the characteristic impedance Z3 of the topology branch 2 are equal, that is, Z1 = Z2 = Z3 = 50 Ω. The length of the topology main trunk 1 is L1. The model simulation waveform is as Figure 2 shown, and the eye height of the eye diagram is 461.034 mV.

[0059] In a preferred example, the routing topology is as Figure 3 shown. The characteristic impedance Z2 of the second main line 102 of the topology main trunk 1 and the characteristic impedance Z3 of the topology branch 2 are equal, that is, Z2 = Z3 = 50 Ω. The characteristic impedance Z1 of the first main line 101 is 70% of the characteristic impedance Z2 of the second main line 102, that is, Z1 = 0.7Z2 = 35 Ω. The length L11 of the first main line 101 is equal to the length L12 of the second main line 102, that is, L11 = L12, and L11 + L12 = L1. The model simulation waveform is as Figure 4 shown, and the eye height of the eye diagram is 559.715 mV, which is 98.681 mV higher than the traditional method, improving the system margin by 21.4%.

[0060] In a preferred example, the routing topology is as Figure 3 shown. The characteristic impedance Z2 of the second main line 102 of the topology main trunk 1 and the characteristic impedance Z3 of the topology branch 2 are equal, that is, Z2 = Z3 = 50 Ω. The characteristic impedance Z1 of the first main line 101 is 70% of the characteristic impedance Z2 of the second main line 102, that is, Z1 = 0.7Z2 = 35 Ω. The length L11 of the first main line 101 is 1.5 times the length L12 of the second main line 102, that is, L11 = 1.5L12, and L11 + L12 = L1. The model simulation waveform is as Figure 5 shown, and the eye height of the eye diagram is 595.775 mV, which is 134.741 mV higher than the traditional method, improving the system margin by 29.2%.

[0061] In a preferred example, the routing topology is as Figure 3As shown, the characteristic impedance Z2 of the second main line 102 of the topology backbone 1 is equal to the characteristic impedance Z3 of the topology branch 2, that is, Z2 = Z3 = 50 Ω. The characteristic impedance Z1 of the first main line 101 is 70% of the characteristic impedance Z2 of the second main line 102, that is, Z1 = 0.7Z2 = 35 Ω. The length L11 of the first main line 101 is 1.5 times the length L12 of the second main line 102, that is, L11 = 2L12, and L11 + L12 = L1. The model simulation waveform is as Figure 6 shown. The eye height of the eye diagram is 620.957 mV, which is 159.923 mV higher than that of the traditional method, improving the system margin by 34.7%.

[0062] As Figure 1 shown, a circuit board described in an embodiment of the present invention includes the structure for improving the signal quality of the interconnected equal-arm branch topology as described above.

[0063] In this embodiment, through the above-mentioned interconnected equal-arm branch topology structure, the positive and negative reflections cancel each other out, significantly reducing the back-and-forth reflection oscillation of the signal within the topology structure, reducing the redundant energy, improving the stability and reliability of signal transmission, and improving the transmission quality of the signal in a high-speed multi-load environment.

[0064] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, and improvements made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A structure for improving the signal quality of an interconnected equal-arm branch topology, characterized in that It includes a topological backbone and multi-level topological branches. Each level of the topological branches is symmetrically arranged. The topological backbone is divided into a first main line connected to a control chip and a second main line connected to the first-level topological branches. The characteristic impedance of the second main line is the same as that of the topological branches. The characteristic impedance of the first main line is 70% of the characteristic impedance of the second main line. The length of the first main line is 1.5 times or 2 times the length of the second main line.

2. The structure for improving the signal quality of the interconnected equal-arm branch topology according to claim 1, wherein The characteristic impedance of each branch in each level of the topological branches is the same.

3. The structure for improving the signal quality of the interconnected equal-arm branch topology according to claim 1, wherein, The length of each branch in each level of the topological branches is the same.

4. A circuit board, characterized in that, It includes the structure for improving the signal quality of the interconnected equal-arm branch topology according to any one of claims 1-3.

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