Semiconductor IGBT device
By introducing trench structure and doped layer into IGBT devices, the on-voltage drop is optimized, and the heat increase problem caused by fast switching is solved, and the stability and reliability of the device are improved.
Patent Information
- Application Number
- CN202422158930.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-04
- Publication Date
- 2025-07-11
- Estimated Expiration
- 2034-09-04
AI Technical Summary
The switching speed of existing IGBT devices is getting faster and faster, resulting in an increase in heat and affecting working stability.
A first trench and a second trench are introduced in the IGBT device, and a conductive polysilicon and an oxide layer are provided therein, combining an N-type heavily doped emitter region and an N-type heavily doped intermediate layer to optimize the structure to reduce the on-voltage drop.
It reduces power loss and heat generation of IGBT devices, and improves device reliability.
Smart Images
Figure CN223094109U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of semiconductor devices, in particular to a semiconductor IGBT device. Background Art
[0002] The IGBT insulated gate bipolar transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor and a field effect transistor. The trench gate IGBT device has lower conduction loss and has become the mainstream product in the market. Due to its combination of the advantages of both BJT and FET, namely, the characteristics of high input impedance and low conduction voltage drop, it has good switching characteristics and is widely used in fields with characteristics such as high voltage and strong current.
[0003] However, with the gradual reduction of IGBT devices, the switching speed of existing IGBT devices is getting faster and faster, resulting in more and more heat, which also affects the working stability of IGBT devices. Summary of the Invention
[0004] The purpose of the utility model is to provide a semiconductor IGBT device, which reduces the conduction voltage drop when the IGBT device works, thereby reducing the power loss and the generated heat, and improving the reliability of the IGBT device.
[0005] To achieve the above purpose, the technical solution adopted by the utility model is: a semiconductor IGBT device, comprising: a silicon wafer, a P-well region located on the upper part of the silicon wafer, and an N-type lightly doped drift layer located below the P-well region. An N-type electric field blocking layer is arranged between a P-type heavily doped collector region located at the lower part of the silicon wafer and the N-type lightly doped drift layer;
[0006] A first trench and a second trench located in the P-well region respectively extend into the N-type lightly doped drift layer. The first trench and the second trench respectively have a first conductive polysilicon and a second conductive polysilicon. The first conductive polysilicon and the second conductive polysilicon respectively have a first oxide layer and a second oxide layer between them and the inner walls of the first trench and the second trench respectively;
[0007] A first N-type heavily doped emitter region and a second N-type heavily doped emitter region are respectively arranged around the first trench and the second trench. An N-type heavily doped intermediate layer is located between the first trench and the second trench. The N-type heavily doped intermediate layer is located between the bottom of the P-well region and the N-type lightly doped drift layer;
[0008] The upper surfaces of the first conductive polysilicon and the second conductive polysilicon are respectively covered with a first dielectric layer and a second dielectric layer. An emitter metal layer covers the upper surfaces of the first N-type heavily doped emitter region, the second N-type heavily doped emitter region, and the P-well region located between the first N-type heavily doped emitter region and the second N-type heavily doped emitter region. A collector metal layer covers the surface of the P-type heavily doped collector region opposite to the N-type field stop layer.
[0009] The further improved solutions in the above technical solutions are as follows:
[0010] 1. In the above solution, the lower ends of the first trench and the second trench are located above the N-type lightly doped drift layer.
[0011] 2. In the above solution, the lower end of the N-type heavily doped intermediate layer is located below the first trench and the second trench.
[0012] 3. In the above solution, the depth ratio of the first N-type heavily doped emitter region to the P-well region is 1:3 to 5.
[0013] 4. In the above solution, the depth ratio of the second N-type heavily doped emitter region to the P-well region is 1:3 to 5.
[0014] 5. In the above solution, the emitter metal layer covers the surfaces of the first dielectric layer and the second dielectric layer.
[0015] Due to the application of the above technical solutions, the present invention has the following advantages compared with the prior art:
[0016] For the semiconductor IGBT device of the present invention, a first N-type heavily doped emitter region and a second N-type heavily doped emitter region are respectively provided around the first trench and the second trench. An N-type heavily doped intermediate layer is located between the first trench and the second trench. The N-type heavily doped intermediate layer is located between the bottom of the P-well region and the N-type lightly doped drift layer, reducing the on-state voltage drop when the IGBT device operates, thereby reducing power loss and generated heat, and improving the reliability of the IGBT device. BRIEF DESCRIPTION OF THE DRAWINGS
[0017] Attached Figure 1 is a schematic structural diagram of the semiconductor IGBT device of the present invention.
[0018] In the above figures: 1. silicon wafer; 2. P-well region; 3. N-type lightly doped drift layer; 4. P-type heavily doped collector region; 5. N-type electric field blocking layer; 61. first trench; 62. second trench; 71. first conductive polysilicon; 72. second conductive polysilicon; 81. first oxide layer; 82. second oxide layer; 91. first N-type heavily doped emitter region; 92. second N-type heavily doped emitter region; 101. first dielectric layer; 102. second dielectric layer; 11. N-type heavily doped intermediate layer; 12. emitter metal layer; 13. collector metal layer. Detailed implementation manners
[0019] The present patent can be further clearly understood through the following specific embodiments, but they do not limit the present patent.
[0020] Embodiment 1: A semiconductor IGBT device includes: a silicon wafer 1, a P-well region 2 located above the silicon wafer 1, and an N-type lightly doped drift layer 3 located below the P-well region 2. An N-type electric field blocking layer 5 is provided between a P-type heavily doped collector region 4 located below the silicon wafer 1 and the N-type lightly doped drift layer 3.
[0021] The first trench 61 and the second trench 62 located in the P-well region 2 respectively extend into the N-type lightly doped drift layer 3. The first conductive polysilicon 71 and the second conductive polysilicon 72 are respectively provided in the first trench 61 and the second trench 62. The first conductive polysilicon 71 and the second conductive polysilicon 72 respectively have a first oxide layer 81 and a second oxide layer 82 between them and the inner walls of the first trench 61 and the second trench 62 respectively.
[0022] A first N-type heavily doped emitter region 91 and a second N-type heavily doped emitter region 92 are respectively provided around the first trench 61 and the second trench 62. An N-type heavily doped intermediate layer 11 is located between the first trench 61 and the second trench 62. The N-type heavily doped intermediate layer 11 is located between the bottom of the P-well region 2 and the N-type lightly doped drift layer 3.
[0023] The upper surfaces of the first conductive polysilicon 71 and the second conductive polysilicon 72 are respectively covered with a first dielectric layer 101 and a second dielectric layer 102. An emitter metal layer 12 covers the upper surfaces of the first N-type heavily doped emitter region 91, the second N-type heavily doped emitter region 92, and the P-well region 2 located between the first N-type heavily doped emitter region 91 and the second N-type heavily doped emitter region 92. A collector metal layer 13 covers the surface of the P-type heavily doped collector region 4 opposite to the N-type electric field blocking layer 5.
[0024] The lower ends of the above-mentioned first trench 61 and second trench 62 are located above the N-type lightly doped drift layer 3.
[0025] The depth ratio of the above-mentioned first N-type heavily doped emitter region 91 to the P-well region 2 is 1:4, and the depth ratio of the above-mentioned second N-type heavily doped emitter region 92 to the P-well region 2 is 1:4.
[0026] The above-mentioned emitter metal layer 12 covers the surfaces of the first dielectric layer 101 and the second dielectric layer 102.
[0027] Embodiment 2: A semiconductor IGBT device, comprising: a silicon wafer 1, a P-well region 2 located on the upper part of the silicon wafer 1, and an N-type lightly doped drift layer 3 located below the P-well region 2. An N-type electric field blocking layer 5 is provided between a P-type heavily doped collector region 4 located at the lower part of the silicon wafer 1 and the N-type lightly doped drift layer 3;
[0028] The first trench 61 and the second trench 62 located in the P-well region 2 respectively extend into the N-type lightly doped drift layer 3. The first trench 61 and the second trench 62 respectively have a first conductive polysilicon 71 and a second conductive polysilicon 72. The first conductive polysilicon 71 and the second conductive polysilicon 72 respectively have a first oxide layer 81 and a second oxide layer 82 between them and the inner walls of the first trench 61 and the second trench 62 respectively;
[0029] A first N-type heavily doped emitter region 91 and a second N-type heavily doped emitter region 92 are respectively provided around the first trench 61 and the second trench 62. An N-type heavily doped intermediate layer 11 is located between the first trench 61 and the second trench 62. The N-type heavily doped intermediate layer 11 is located between the bottom of the P-well region 2 and the N-type lightly doped drift layer 3;
[0030] The upper surfaces of the first conductive polysilicon 71 and the second conductive polysilicon 72 are respectively covered with a first dielectric layer 101 and a second dielectric layer 102. An emitter metal layer 12 covers the upper surfaces of the first N-type heavily doped emitter region 91, the second N-type heavily doped emitter region 92, and the P-well region 2 located between the first N-type heavily doped emitter region 91 and the second N-type heavily doped emitter region 92. A collector metal layer 13 covers the surface of the P-type heavily doped collector region 4 opposite to the N-type electric field blocking layer 5.
[0031] The lower end of the above-mentioned N-type heavily doped intermediate layer 11 is located below the first trench 61 and the second trench.
[0032] The above-mentioned emitter metal layer 12 covers the surfaces of the first dielectric layer 101 and the second dielectric layer 102.
[0033] The depth ratio of the above-mentioned first N-type heavily doped emitter region 91 to the P-well region 2 is 1:3.5, and the depth ratio of the above-mentioned second N-type heavily doped emitter region 92 to the P-well region 2 is 1:3.5.
[0034] When the above-mentioned semiconductor IGBT device is adopted, its first trench and the second communication periphery respectively have a first N-type heavily doped emitter region and a second N-type heavily doped emitter region. An N-type heavily doped intermediate layer is located between the first trench and the second trench. The N-type heavily doped intermediate layer is located between the bottom of the P-well region and the N-type lightly doped drift layer, reducing the on-state voltage drop during the operation of the IGBT device, thereby reducing the power loss and the generated heat, and improving the reliability of the IGBT device.
[0035] The above embodiments are only used to illustrate the technical concept and features of the present invention. The purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly, and it cannot be used to limit the protection scope of the present invention. All equivalent changes or modifications made according to the spirit and essence of the present invention should be covered within the protection scope of the present invention.
Claims
1. A semiconductor IGBT device, characterized in that: Including: A silicon wafer (1), a P-well region (2) located above the silicon wafer (1), and an N-type lightly doped drift layer (3) located below the P-well region (2). An N-type electric field blocking layer (5) is provided between a P-type heavily doped collector region (4) located below the silicon wafer (1) and the N-type lightly doped drift layer (3). A first trench (61) and a second trench (62) located in the P-well region (2) respectively extend into the N-type lightly doped drift layer (3). A first conductive polysilicon (71) and a second conductive polysilicon (72) are respectively provided in the first trench (61) and the second trench (62). A first oxide layer (81) and a second oxide layer (82) are respectively provided between the first conductive polysilicon (71), the second conductive polysilicon (72) and the inner walls of the first trench (61), the second trench (62) respectively. A first N-type heavily doped emitter region (91) and a second N-type heavily doped emitter region (92) are respectively provided around the first trench (61) and the second trench (62). An N-type heavily doped intermediate layer (11) is located between the first trench (61) and the second trench (62). The N-type heavily doped intermediate layer (11) is located between the bottom of the P-well region (2) and the N-type lightly doped drift layer (3). The upper surfaces of the first conductive polysilicon (71) and the second conductive polysilicon (72) are respectively covered with a first dielectric layer (101) and a second dielectric layer (102). An emitter metal layer (12) covers the upper surfaces of the first N-type heavily doped emitter region (91), the second N-type heavily doped emitter region (92) and the P-well region (2) located between the first N-type heavily doped emitter region (91) and the second N-type heavily doped emitter region (92). A collector metal layer (13) covers the surface of the P-type heavily doped collector region (4) opposite to the N-type electric field blocking layer (5).
2. The semiconductor IGBT device according to claim 1, characterized in that: The lower ends of the first trench (61) and the second trench (62) are located above the N-type lightly doped drift layer (3).
3. The semiconductor IGBT device according to claim 1, characterized in that: The lower end of the N-type heavily doped intermediate layer (11) is located below the first trench (61) and the second trench (62).
4. The semiconductor IGBT device according to claim 1, characterized in that: The depth ratio of the first N-type heavily doped emitter region (91) to the P-well region (2) is 1:3 - 5.
5. The semiconductor IGBT device according to claim 1, characterized in that: The depth ratio of the second N-type heavily doped emitter region (92) to the P-well region (2) is 1:3 - 5.
6. The semiconductor IGBT device according to claim 1, wherein: The emitter metal layer (12) covers the surfaces of the first dielectric layer (101) and the second dielectric layer (102).