IGBT device structure

Abstract

The utility model discloses an IGBT (Insulated Gate Bipolar Translator) device structure, which is characterized in that a first groove, a second groove and a third groove which are positioned in a P well region respectively extend into an N-type lightly doped drift layer, and are respectively provided with first conductive polycrystalline silicon, second conductive polycrystalline silicon and third conductive polycrystalline silicon; a first oxide layer, a second oxide layer and a third oxide layer are respectively arranged between the first conductive polycrystalline silicon, the second conductive polycrystalline silicon and the third conductive polycrystalline silicon and the inner walls of the first groove, the second groove and the third groove; and a first N-type heavily doped emitter region, a second N-type heavily doped emitter region and a third N-type heavily doped emitter region are respectively arranged at the peripheries of the first groove, the second groove and the third groove. According to the utility model, the conduction voltage drop when the IGBT device works is reduced, the power loss and the generated heat are reduced, the reliability of the IGBT device is improved, the switching speed is also improved, and the switching loss is reduced.

Description

Technical Field

[0001] The utility model relates to the technical field of semiconductors, in particular to an IGBT device structure. Background Art

[0002] An IGBT insulated gate bipolar transistor is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar transistor and a field effect transistor. The trench gate IGBT device has lower conduction loss and has become the mainstream product in the market. Due to its combination of the advantages of both BJT and FET, namely the characteristics of high input impedance and low conduction voltage drop, it has good switching characteristics and is widely used in fields with characteristics such as high voltage and strong current.

[0003] However, with the gradual reduction of IGBT devices, the switching speed of existing IGBT devices is getting faster and faster, resulting in more and more heat, which also affects the working stability of IGBT devices. Summary of the Invention

[0004] The purpose of the utility model is to provide an IGBT device structure, which not only reduces the conduction voltage drop when the IGBT device works, reduces power loss and generated heat, improves the reliability of the IGBT device, but also improves the switching speed and reduces switching loss.

[0005] To achieve the above object, the technical solution adopted by the utility model is: an IGBT device structure, including: a silicon wafer, a P-well region located on the upper part of the silicon wafer, and an N-type lightly doped drift layer located below the P-well region. An N-type electric field blocking layer is arranged between a P-type heavily doped collector region located at the lower part of the silicon wafer and the N-type lightly doped drift layer;

[0006] A first trench, a second trench, and a third trench located in the P-well region respectively extend into the N-type lightly doped drift layer. A first conductive polysilicon, a second conductive polysilicon, and a third conductive polysilicon are respectively arranged in the first trench, the second trench, and the third trench. A first oxide layer, a second oxide layer, and a third oxide layer are respectively arranged between the first conductive polysilicon, the second conductive polysilicon, and the third conductive polysilicon and the inner walls of the first trench, the second trench, and the third trench respectively;

[0007] A first N-type heavily doped emitter region, a second N-type heavily doped emitter region, and a third N-type heavily doped emitter region are respectively arranged around the first trench, the second trench, and the third trench; an N-type heavily doped intermediate layer is located between the first trench and the second trench. The N-type heavily doped intermediate layer is located between the bottom of the P-well region and the N-type lightly doped drift layer. The P-well region between the second trench and the third trench is in contact with the N-type lightly doped drift layer;

[0008] The upper surfaces of the first conductive polysilicon (71), the second conductive polysilicon (72), and the third conductive polysilicon (73) are respectively covered with a first dielectric layer (101), a second dielectric layer (102), and a third dielectric layer (103). An emitter metal layer covers the upper surfaces of the first N-type heavily doped emitter region, the second N-type heavily doped emitter region, and the P-well region located between the first N-type heavily doped emitter region and the second N-type heavily doped emitter region. A collector metal layer covers the surface of the P-type heavily doped collector region opposite to the N-type electric field stopping layer.

[0009] The further improved solutions in the above technical solutions are as follows:

[0010] 1. In the above solution, the lower ends of the first trench and the second trench are located above the N-type lightly doped drift layer.

[0011] 2. In the above solution, the lower end of the N-type heavily doped intermediate layer is located below the first trench and the second trench.

[0012] 3. In the above solution, the emitter metal layer covers the surfaces of the first dielectric layer and the second dielectric layer.

[0013] 4. In the above solution, the depth ratio of the first trench, the second trench, the third trench to the P-well region is 10:10:10:6 - 8.

[0014] Due to the application of the above technical solutions, the present utility model has the following advantages compared with the prior art:

[0015] The IGBT device structure of the present utility model has a first N-type heavily doped emitter region, a second N-type heavily doped emitter region, and a third N-type heavily doped emitter region respectively around the first trench, the second trench, and the third trench; an N-type heavily doped intermediate layer is located between the first trench and the second trench, the N-type heavily doped intermediate layer is located between the bottom of the P-well region and the N-type lightly doped drift layer, and the P-well region between the second trench and the third trench is in contact with the N-type lightly doped drift layer; it not only reduces the on-state voltage drop during the operation of the IGBT device, reduces the power loss and the generated heat, improves the reliability of the IGBT device, but also improves the switching speed and reduces the switching loss. Description of the Drawings

[0016] Appendix Figure 1 is a schematic structural diagram of the IGBT device structure of the present utility model.

[0017] In the above figures: 1. silicon wafer; 2. P-well region; 3. N-type lightly doped drift layer; 4. P-type heavily doped collector region; 5. N-type electric field blocking layer; 61. first trench; 62. second trench; 63. third trench; 71. first conductive polysilicon; 72. second conductive polysilicon; 73. third conductive polysilicon; 81. first oxide layer; 82. second oxide layer; 83. third oxide layer; 91. first N-type heavily doped emitter region; 92. second N-type heavily doped emitter region; 93. third N-type heavily doped emitter region; 101. first dielectric layer; 102. second dielectric layer; 103. third dielectric layer; 11. N-type heavily doped intermediate layer; 12. emitter metal layer; 13. collector metal layer. Detailed implementation mode

[0018] The present patent can be further clearly understood through the following specific embodiments, but they do not limit the present patent.

[0019] Embodiment 1: An IGBT device structure includes: a silicon wafer 1, a P-well region 2 located above the silicon wafer 1, and an N-type lightly doped drift layer 3 located below the P-well region 2. An N-type electric field blocking layer 5 is provided between a P-type heavily doped collector region 4 located below the silicon wafer 1 and the N-type lightly doped drift layer 3.

[0020] The first trench 61, the second trench 62, and the third trench 63 located in the P-well region 2 respectively extend into the N-type lightly doped drift layer 3. The first trench 61, the second trench 62, and the third trench 63 respectively have a first conductive polysilicon 71, a second conductive polysilicon 72, and a third conductive polysilicon 73. The first conductive polysilicon 71, the second conductive polysilicon 72, and the third conductive polysilicon 73 respectively have a first oxide layer 81, a second oxide layer 82, and a third oxide layer 83 between them and the inner walls of the first trench 61, the second trench 62, and the third trench 63 respectively.

[0021] A first N-type heavily doped emitter region 91, a second N-type heavily doped emitter region 92, and a third N-type heavily doped emitter region 93 are respectively provided around the first trench 61, the second trench 62, and the third trench 63. An N-type heavily doped intermediate layer 11 is located between the first trench 61 and the second trench 62. The N-type heavily doped intermediate layer 11 is located between the bottom of the P-well region 2 and the N-type lightly doped drift layer 3. The P-well region 2 between the second trench 62 and the third trench 63 is in contact with the N-type lightly doped drift layer 3.

[0022] The upper surfaces of the first conductive polysilicon 71, the second conductive polysilicon 72, and the third conductive polysilicon 73 are respectively covered with a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 103. An emitter metal layer 12 covers the upper surfaces of the first N-type heavily doped emitter region 91, the second N-type heavily doped emitter region 92, and the P-well region 2 located between the first N-type heavily doped emitter region 91 and the second N-type heavily doped emitter region 92. A collector metal layer 13 covers the surface of the P-type heavily doped collector region 4 opposite to the N-type field stop layer 5.

[0023] The lower ends of the above-mentioned first trench 61 and second trench 62 are located in the upper part of the N-type lightly doped drift layer 3.

[0024] The lower end of the above-mentioned N-type heavily doped intermediate layer 11 is located below the first trench 61 and the second trench.

[0025] The depth ratio of the above-mentioned first trench 61, second trench 62, third trench 63 to the P-well region 2 is 10:10:10:7.

[0026] Embodiment 2: An IGBT device structure includes: a silicon wafer 1, a P-well region 2 located above the silicon wafer 1, and an N-type lightly doped drift layer 3 located below the P-well region 2. An N-type field stop layer 5 is disposed between a P-type heavily doped collector region 4 located below the silicon wafer 1 and the N-type lightly doped drift layer 3;

[0027] The first trench 61, second trench 62, and third trench 63 located in the P-well region 2 respectively extend into the N-type lightly doped drift layer 3. The first trench 61, second trench 62, and third trench 63 respectively have a first conductive polysilicon 71, a second conductive polysilicon 72, and a third conductive polysilicon 73. The first conductive polysilicon 71, second conductive polysilicon 72, and third conductive polysilicon 73 respectively have a first oxide layer 81, a second oxide layer 82, and a third oxide layer 83 between them and the inner walls of the first trench 61, second trench 62, and third trench 63 respectively;

[0028] A first N-type heavily doped emitter region 91, a second N-type heavily doped emitter region 92, and a third N-type heavily doped emitter region 93 are respectively located around the first trench 61, second trench 62, and third trench 63; an N-type heavily doped intermediate layer 11 is located between the first trench 61 and the second trench 62. The N-type heavily doped intermediate layer 11 is located between the bottom of the P-well region 2 and the N-type lightly doped drift layer 3. The P-well region 2 located between the second trench 62 and the third trench 63 is in contact with the N-type lightly doped drift layer 3;

[0029] The upper surfaces of the first conductive polysilicon 71, the second conductive polysilicon 72, and the third conductive polysilicon 73 are respectively covered with a first dielectric layer 101, a second dielectric layer 102, and a third dielectric layer 103. An emitter metal layer 12 covers the upper surfaces of the first N-type heavily doped emitter region 91, the second N-type heavily doped emitter region 92, and the P-well region 2 located between the first N-type heavily doped emitter region 91 and the second N-type heavily doped emitter region 92. A collector metal layer 13 covers the surface of the P-type heavily doped collector region 4 opposite to the N-type field stop layer 5.

[0030] The lower ends of the above-mentioned first trench 61 and second trench 62 are located above the N-type lightly doped drift layer 3.

[0031] The above-mentioned emitter metal layer 12 covers the surfaces of the first dielectric layer 101 and the second dielectric layer 102.

[0032] The depth ratio of the above-mentioned first trench 61, second trench 62, third trench 63 to the P-well region 2 is 10:10:10:6.5.

[0033] When the above IGBT device structure is adopted, a first N-type heavily doped emitter region, a second N-type heavily doped emitter region, and a third N-type heavily doped emitter region are respectively provided around the first trench, the second trench, and the third trench; an N-type heavily doped intermediate layer is located between the first trench and the second trench. The N-type heavily doped intermediate layer is located between the bottom of the P-well region and the N-type lightly doped drift layer, and the P-well region located between the second trench and the third trench is in contact with the N-type lightly doped drift layer; not only the on-state voltage drop during the operation of the IGBT device is reduced, the power loss and the generated heat are reduced, the reliability of the IGBT device is improved, but also the switching speed is increased and the switching loss is reduced.

[0034] The above embodiments are only used to illustrate the technical concept and features of the present invention, and the purpose is to enable those who are familiar with this technology to understand the content of the present invention and implement it accordingly, and cannot be used to limit the protection scope of the present invention. Any equivalent changes or modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims

1. An IGBT device structure, characterized in that: Comprising: A silicon wafer (1), a P-well region (2) located above the silicon wafer (1), and an N-type lightly doped drift layer (3) located below the P-well region (2). An N-type electric field blocking layer (5) is provided between a P-type heavily doped collector region (4) located below the silicon wafer (1) and the N-type lightly doped drift layer (3); A first trench (61), a second trench (62), and a third trench (63) located within the P-well region (2) respectively extend into the N-type lightly doped drift layer (3). A first conductive polysilicon (71), a second conductive polysilicon (72), and a third conductive polysilicon (73) are respectively provided within the first trench (61), the second trench (62), and the third trench (63). A first oxide layer (81), a second oxide layer (82), and a third oxide layer (83) respectively exist between the first conductive polysilicon (71), the second conductive polysilicon (72), and the third conductive polysilicon (73) and the respective inner walls of the first trench (61), the second trench (62), and the third trench (63); A second N-type heavily doped emitter region (92) is provided around the second trench (62). A first N-type heavily doped emitter region (91) is provided around the side of the first trench (61) close to the second trench (62). A third N-type heavily doped emitter region (93) is provided around the side of the third trench (63) close to the second trench (62). An N-type heavily doped intermediate layer (11) is located between the first trench (61) and the second trench (62). The N-type heavily doped intermediate layer (11) is located between the bottom of the P-well region (2) and the N-type lightly doped drift layer (3). The P-well region (2) between the second trench (62) and the third trench (63) is in contact with the N-type lightly doped drift layer (3); The upper surfaces of the first conductive polysilicon (71), the second conductive polysilicon (72), and the third conductive polysilicon (73) are respectively covered with a first dielectric layer (101), a second dielectric layer (102), and a third dielectric layer (103). An emitter metal layer (12) covers the upper surfaces of the first N-type heavily doped emitter region (91), the second N-type heavily doped emitter region (92), and the P-well region (2) located between the first N-type heavily doped emitter region (91) and the second N-type heavily doped emitter region (92). A collector metal layer (13) covers the surface of the P-type heavily doped collector region (4) opposite to the N-type electric field blocking layer (5).

2. The IGBT device structure according to claim 1, characterized in that: The lower ends of the first trench (61) and the second trench (62) are located above the N-type lightly doped drift layer (3).

3. The IGBT device structure according to claim 1, characterized in that: The lower end of the N-type heavily doped intermediate layer (11) is located below the first trench (61) and the second trench.

4. The IGBT device structure according to claim 1, characterized in that: The emitter metal layer (12) covers the surfaces of the first dielectric layer (101) and the second dielectric layer (102).

5. The IGBT device structure according to claim 1, wherein: The depth ratio of the first trench (61), the second trench (62), the third trench (63) to the P-well region (2) is 10:10:10:6 - 8.

Images